zao Family

Questions & A nswers

This apphcation note contains the most commonly

asked questions about the Zilog ZBO Family They
aredividedinto 1onowing sections:

ZBO CPU
ZBO DMA
PIO

zeo

zao crc

Z80 SIO, ZBO OART

Obviously, nol every questions on ZBO Family

components are answered. However, this application
note should give you a good feel for the ZBO Family
devices.Along with the technicalManual, Product
Specification and sorne other application notes, it
should help make your ZBO design tamilyalittleeasier.
Also,thisApplication Noteis applicable
to the Z80 KIO and other ZBO family based Super
Integra
tion
Devices.

ZBO CPU

O Are theZ80 CPU 6 and BMHz docks sensitivalike

their predecessors?
A. Yes, spedfications for risa and fall times and clock
voltage levels must be met.

O:Can the risingedge onthe CLK input affectthe

oWhat is the dock input impeadance

(load)? A. Capacitive load only (35pF max)
O: Will Non-maskable interrupts continue occurring
and executing it the NMIline pulses prior to the f
nish
of the service routine?
A: Yes Non-Maskable interrupts can not be disabled
by user. Even though Non-Maskable lnterrupts are
nega flve edge triggered ,if theinput to the CPU pulses
before tennination of the service routine, then the
service routine w1llbeg1n again

How
does
the
Non-Maskable
lnterrupt
acknowledge cycle and RETN instruction actually
work?
A :When
a
Non-Maskablelnterrupt
is
acknowledged,nter rupt flip-flop #1 (IFF1) is
actually cleared to inhibit the acknowledgement of
maskable interrupts. The state of
1nterrupt flip-flop #2 (IFF2)
This is lhe
is n
ot altered only can
time that the contents of
and
disagree
IFF1 When the RETNinstruct
ion IFF2 the state of IFF2
executes.
F1.
This allows
is copied back into
the state of
fore
a
IF
maskable interrupts. beNon
Maskable lnterrupl
to be restored after service routine execution.
Q How are subtraction operations performed?

A: Atthough the actual operation s probably a 2's

comple mentaddition, the 11ags are affectedas if it
were a logical subtraction operation.

operation ot the CPU?

O What is the setup time to recognize an NMI?

spikeon any pin wthout back bias will forward-bias A Through characterization of the CPU Zilog has found
that
asetup
time
of
120nS(@4MHz)is
the
dode
that
existsbetweenthe
N+
requiredinorder to assure that NMI 1s recognized
materialconnected to the pad and p-type substrate.
before INTis recogThis action causes thein
jectionof many electronsinto the substrate. Once
nized.
inthe substrate, they are free to dritt into any
Q What do the El and DIinstruct1on actually do?
region of higher polential,whichis the N+ regionat
A" Only the 1nterrupt control flip-flops (IFF1 and IFF2)
Vcc of storage nades sloring a "1". Since storage
are alfected by those instructions. The DI instruction
holds don't store much
will ciear both IFF1 and IFF2 and prvent any further
charge (in order to minimiza capacitance), these
maskabfe interrupt from being recognized from that
elec tronsin the substrate can be swept across the
point on. The El instruct1on will set both IFF1 and
junction and destroy the "1" stored there This
IFF2, but maskable interrupts
reaction obvi ously affects the operation of the
1 will not be recogni2ed
Also, on CMOS devices, pos1tive spikes on any pin exceeding Vcc voltage
could
cause "t.Atch-up"
till the
completion
of the next instruction
part.
A Very much so. For NMOS devices, a negative voltage

3-129

...-

3-130

Q:What is ttie status of the output drivers when lhe

CPU is in a power-down situation?
.
A: When the CPU is without power, the output
dnvers
appear to bein a highimpedance state.

O:Howcan 1use the onchp refresh mechanism ot the

Z80 CPU to handle refresh1ng ol 64K 0-RAMs?
A Here are sorne suggestions (assuming 256 cyde re
fresh)

1. Use an externa!counter to count 128 M1 cycles

and toggle refresh address line A7.

2. Use eemal hardware to generate an NMI

every

2mS andchange the state olbtt 07 in the

R Register via software.
3. Use refresh address bit A6 lo toggle lhe state of
refresh address bit A7

O:Is there a melhodfor testing hardware without

removing
the Z80 CPU from lhe socket?
A Two melhods are available

1. Use BUSREO to tri-slate all control s1gnals and

then use externa! hardware to simulate the
logic;
2. Remove power and ground from the CPU, ali
signals should go to a high-impedance.

oDoes the CPU tristate M1 during reset?

A: No.

O: Is Zilog going to add a 3.15 Volt current drive spec

for designers using 74HCxx series of cornponents?

A:No. There is a choice of either using 74HCTxx

logic or using our CMOS ZSO CPU.

O: tt NMI 1s aciivated DURING reset, will the processor

execute the NMI or address OOOOh after reset goes
high?

A: Since NMI input is "edge-tnggered" input, if the CPU

has active NM1 duringreset, CPUwon'tdetect NM

1andwill

exeoJte !he instruction at OOOOh. lf

NMI goeslow alter RESET goes inact1ve, then CPU
will process NMI.

O l've heard the CPU is astatic device Can 1 usethe

dock
to single step it?

A.

ll's <ifferent for NMOS and CMOS.

NMOS: No. it violates the clock specs.
CMOS Yes You can do that.

O: 1 don't seem to gel the correct state of the rnterrupts

when usrng the LO A ,Iand LO A.A instructions
toread
state of IFF2 Why is this? How can 1 get aro nd
lth
h1s?

A'. On CMOS Z80 CPU, we've fixed this problem On

NMOS

zeo CPU,in certain nanoWly defined cirm-

stances, the Z80 CPU 1nterrupt enablelatdl, IFF2,

does not necessarily reflect the true mterrupt status.
The two 1nstruclions LD A,R and LO A,I copy the
state of interrupt enablelatch (IFF2) into the parity
flag and modifies the accumulator contents (See
table 7 0.1 in the Z80 CPU technical manual for
detai s) Thus. it 1s possible to determinewhether
interrupts are enabled or
d1sabledalthetime that theinstrudion1sexecuted. Th1s
facil ty is necessary to save the complete stale of
the machine. However, if an interrupt 1s accepted by
the CPU dunng the execuhon of the instruction -
implying that the interrupts must be enabled- the
PN flag is cleared.Th1s 1ncorrectly asserts that
interrupts were d1sabled at the time the instruction

was executed.
This paradox can be traced to the mtemal timing of !
he CPU Theproblem is that the interrupt flip-flop
{IFF2) is cleared before il s actually transferred to
the PN flag. The state of lhe interrupt enable latch is
notcopied into the parity flag unlil after the interrupt
time, occurring during the executon of the
mslruct1on, has been ac cepted S1nce the
acceptance of theinterrupt automati cally clears the
interrupt enablelalch. the parity flagis also cleared,
despite the fact that interrupts were en abled when
the instruction started executing
A neat solulion to this anomaly relies on the fact that
at least oneitem -- the old PC value-is saved on the
stack when an interrupt 1saccepted. The ne:xt entry"
position on the stack (the word below the address
currently held
in the stack po1nter) may be deared before executron of
LO A,I (or LDA,R) lf that zero value haschangedby
the time thal the nex1instruction in the routine is
executed,
then
an
inlerrupt
must
havebeen accepted.This implies that interrupts were
enabled, even if the state of the
parity flag suggests that they were not. Of course.if
the parity flag is found to be set after LD A,R (LO
A,1) has be enexecuted,there is no need to check
thestack top.
lnterrupts are definitely enabledif the parity flag is
inthis state
:rwo routnes are listed here Both retum carry clear
if 1nterrupts are enabled,set otherwise . Bolh corrupt
the A register. it does nol contain the value in the 1
(or A) register on exit The status of all flags except
the carry flag are undefined on exit
The first rout1ne may be loaded anywhere in memory
except "page zero" - OOOOh to OOFFh. This small
restriction comes about because the routine checks
ony the most significant byte of lhe "nexf stack
entry . ThisbyteWi_ll
benon-zero afteraninterrupt
hasoccurred if and only if the routineitself is not on
page 2ero. The secondroutine tests both bytes of the
"next'' entry and. therefore. overcomes this restriction.

caution, these roulines presume that the service

rou tine tor any acceptableinterrupt will reenableinterrupls before illerminates. This is almost
always the case. They may not retum the correct
result il an lnterrupt serv?ce routne. which does nol
re-enable interrupts, is
enlered atter the execution of LO A,I (or LO A,R).
Usting 1. This roultne may not be loaded m page
zero
(OOOOh to OOFFh).

GETIFF

XOR

PUSH A
F POP AF
lD
A,I
RET PE
DEC
SP
DEC SP
POP AF

ANO

RET

NZ

SCF
RET

ENO

;C flag, acc. =

;stack bottom := OOxxh

;Restore SP
;P flag := IFF2
;Exit if enabled
;May be disabled.
;Has stack bottom been
;overwritten ?
;lf not OOxxh, INTs were
;actually enabled
;Otherwise, they really
are
;disabled.

Lisl ng 2This roullne may be loaded anywherein

memory.

GETIFF
PUSH HL
XOR

LD
H.A
lD
L,A
PUSH HL
POP HL

LD

A,I

JP

PE,

;Save HL conlents
;C flag, acc. := O
;HL := OOOOh
;Stack bottom :=
OOOOh
;Restore SP
;P flag := IFF2

RET

POPHL ,Exit if isn't

enabled SP ;May be
disabled
SP
;Let's see if stack
bottom HL
;is still OOOOh
A,H
;Are any bits selin
HL
;or in L ?
Hl
;Restore old contenls.
NZ
;HL <> O :isn't enabled.
;Otherwise, they really
are
;disabled.

POP

HL

DEC
DEC
POP

LO

OR
POP

RE
T

SC
F
POPHL:

RET
END

;Exit when P flag

1s
;set by LO A,I

Q Are all olthe Z80 control lines internally

synchronized? A:The inputs in question are INT, NMI,
BUSREO. WAIT. and AESET. In lhe past, it seems
that sorne of our customers have assumed thal those
inputs are totally

asynchronous with respect to the system clock (Le.

no setuptimerequired).Zilog's officialposition on this
topic is as lollows.

Ali asynchronousinputs tolhe Z80 family CPUs

should be extemally synchronized with lhe CPU
dock. The required synchronization is specilied by
the setup and hold times for asynchronous inputs to
the CPU. The synchronizallonis automatically
providedfor by the Z80
Family
peripherals
thal
are
capable
of
drivmg theasyn chronous inputs to the CPU.
ln the Z80 CPU Technical Manual (Pages 70 and 72.

footnote 6), it is st.ated thal "Ali control signals are

intemally synchronzed so that they are totally asyn
chronous with respect to the clock." Th1s statement
should be amended to say "When interfacing the Z80
CPU to the Z80 family penpherals. the interface control
signals are interna! ly synchronzed w1th lhe
system dock by !he peripherals themselves. When
interfacing
lo the Z80 CPU with other devices. these control s1gnals
should be synchronized with respect to the system
clock." Note that the lormer statement has been re
moved from the data book andthe CPU product
speci ficat1on. bul has not been removed from the
technical
manualyet

The basis for lhe synchrornza!ion of the input

control signals isthe potenlialfor the occurrence of a
phenome non called a "meta-stable state". The
detai s of the meta-stable state are complex, but
the concept is fairly simple. A meta-slable state
occurs in b-slable logic devices at the interface
between an asynchronous and synchronous
environment. All two-state logic dev1ces spend
sorne finita amount of time 1n the "linear reg1on"
(between thelogic state of one and zero) .The
lenglhol
time spent m the lmear reg1on depends
uponttleswtch ing speed of the device. lf a
synchronous system samples asynchronous inputs
at !he precise point in time that it passeslhrough
the linear region,the output of the sampling logre
may spend time in an undefined logic state (the
meta stable state) The settling time to a validlogic
state is proportionaltolheinverse exponen tialof the
speed of the switchrng devices. More impor tanlly,
if thedev1ce in the meta-stable state isconnected
to severa!other bi-state dev1ces 1nthe system,the
pos sibility exists for each of these bi-slate de vices
lo inter
pret lhe non-b1nary (or meta-stable) input differently.
The
final resullstate
can for
be aansequential
undefinedstate
or machine
unpredictable
such as the zao
CPU

3-131

There are severa! pointslhat should be

remembered concerning lhese

asynchronous inputs:

Z80 CPU

e;

'-------------------------1. All

interfaces
between
synchronous
and
asynchro nous system thal use clocked bi-stable
devices are subject to the "meta-stable"
phenomenon.
2.The probability of occurrence of a meta-stable
stateis
directly proportional of the frequency of changes
in the state at the inter1aceand inversely
proportionalto the exponentialof the switching
speedof the devices used.

O: How to interface the Z80 CPU to a 8259 using

Mode O
interrupt?
A. The Z80 CPU's interrupt mode "Mode O" is the

rnode whch mainlains the "software compa1ibility"

with the 8080.it is NOT fully compatible.
In this interrupt mode, during INTAC'K cycle. the
Z80 CPU fetches the data on the bus as an
"instruction" and executes it, like the 8080. However,
from the hardware stand point, it's not true.
The 8080 generales three INTA pulses during
theinter rupt acknowledge cycle while the Z80 CPU
generales only one INT ACK signal(whichcan
bedecoded from M1 and AD).
Th1s system works fine if you are not usingthe 8259
and

pul "RST'' (restart) instruction onto the bus during

the lnterruptAcknowted gecycle,whichisa one byte
instruc tion.
However. if youwant touselhe 8259 with the Z80
CPU, you'll have a problem. That is:
The 8259 expects three INTA pulses but the Z80
CPU genera es only one INTACK cycle.
The bestway tosolve the problern is
"simulating an8080 interrupt acknowledge cycle"
-which means generating a total of three "INTA"
pulse for the 8259 from the Z80 CPU's interrupt
acknowledge cycle by externa!logic. Following figure
(Figure 1.) is the one xample of the im
plementation.

''""'
A

Th1sarcu1t works aslollows (Assume that the 1nstructlon

senl by the 8259 is "CALL" instruction):
On interrupt acknowledge cycle, the decoded INTA
sig na!is sent as an INTA pulse for the 8259 and
at the same time sets the LS74 to indicate that
aninterrupt acknowledge cycle has started.

on the call instruct1on, this circuil generales

two additonal INTA pulses for the 8259 and also
masks off the read signa!lor the memory to avo id
bus con tention problems
On the followng write cycle, WR signal resetslhe
LS74 to indicate that the interrupt acknowledge
cycle is completed.
By usingthis circuit. you can usethe8259 wilh280 CPU.

Z80 DMA
Q: Does DMA recogrnze only 8-bit 1/0 addresses?
A The DMA device does not care whether the 1/0
ad dresses ar memory addresses are 8bit or 16-bi .
The Z80 DMA can address jusi as many 1/0
locations as il can memory local ons.
Q: What is the importance on !he placement of the "LOAD"
commands?
A: The "LOAD" command only loads the contents of
the
source
addressregister
intothe
source
addresscounler. The contents of the destination
address register are automatically loaded into the
destination
address counter the firstlime the
destination
address
gets
incre
mented
or
decremented.

'ts08

Figure 1.

zso

CPU to 8259 interface example

When usmg the variable t1m1ng modes. are there

in settrng uplhe two ports thal the

0 any eonstrainls
user

should beaware of?

A" ves Whenusingthe earty cycleendtimng feature of
the DMA. il is strongty recommended that both
ports be 1nitialzed with the same tming constraints
0 Is there any way to reset the DMA besdes the
RESET command and power-down?
AWith the CMOS DMA:On 44-pin PLCC package,
there is a newly aclded "hardware reset pin" on pin
12 (This pin is left open on NMOS PLCC) Also, we
ve added special funct1ons to the M1 s1gnal l1ne
that allows you to resel C-MOS DMA. During
anachve M1 signa!. without
an ac11ve AD or IOAQ, lhe DMA 1s reset. This
feature is the same as thal with
PIO
With NMOS,the only way to reset the DMA is by
reset command. Aciually, the RESET command
can only resel the DMA i1 the CPU has control of
the bus if the DMA has control of the bus there 1s
no way to reset it other than powering down the
system (or the DMA).

zao

Howlongdoes powerneed toberemovedfrom the DMA

for an interna! reset to occ:ur?
A Zilog tesis the power-onresetc1rcuit al 10mS.lf the
user 1s 901ng to remove power from the DMA, Ziiog
recom mends that it be done with the CLK input high

A Yes. bul there are sorne ma1or concems m domg 1t

Remember thal when Port A is programmed into
lhe bdirectional moda (mode 2), the handshake
lines from Port B are used as input handshake fines
for Port A. Sorne confus1on occurs withm the PIOif
Port B as also
programmed 1nto the input mode (mode 1) and tries
to usethe handshake hnes.A comb1nation of
software and hardware canbeusedto insure that
datawillnot change untilbolh ports can be read.

O Is the PIO port protected against hysteres1s?

A No
ODoyou have tosirobe data into thepon tor proper mode
1 operation?
A: Yes, if you want to generate 1nterrupts for mode 1
operation.11youonly want to read the port dala.
then lhe STBinput can be heldlowto make !he input
datalatches transparent.

O: How can 1 gel Port B interrupt in Mode 3 and

Port A interrupt in Mode 2?

A. You can gel them, bu! it can cause severe 1nterrup1

conflicts if you choose that opt1on. Port B intenupts
are used by Port A in bidirectional rnode lor receave
data interrupts To preven! interrupt confhcts. Pon B
1nter rupts should be enabled.but allbits of Port
Bshould be masked trom attect1ng the interrupts. In
the PIO Tech nical Manual it states that. the same
interrupt vector will beretumed for a Mode 3 mterrupt
on Port B andan 1npul 1nte1rupt dunng Mode 2
operation of Port A'" (Sect1on 5.3)

O What limitabons are not specified 1n!he data book?

A For NMOS DMA, when us1nglhe DMA 1n BURST
mode wilh2 cycte tim1ng,an extra transact1on
isgenerated al the end of the burst.
For CMOS DMA, we've fixed all hmitations
O Howcan 1use the DMA to transf er a page of
infonnatron but do il one l1ne al a time and wait
between lines? (Printer applicatton)
A: Operate the DMA 1n the Sur mode and use the
pnnter VO REAOY line lo control DMA. Program
the DMA for auto restart mode to lransfer the same
"page'' area continuously When the printer is
unable to accept a "line", lhe DMA will allow lhe
CPU to control the bus

zao P10
O When us1ng a port of the PIOin b1I mode (mode 3).
can any ot the bits, programmed as outputs, affect
the ln er rupt conditions sel for recogniz1ng inputs?
A While 1t is undocumented,itis possble thal the state of
lhe bits programmed as outpu1s could be used as
sabsfy1ng conditions for the mode 3 interrupt
equatt0n. 11 tS recommended that all bits not
needed for the mterrupts be masked off
Q Can the PIO be programmed to provide a 16-bit

input PDrt and an 8-bit b1drrectional port al the same

time?

Can the PIOcontrol registe< bewntten whilethe

P10IUS bit 1s set?

A.Yes

But it 1s a saler programming practice to program

the device alter the RET! command

Q:The on-ch1ppower-on reset does not always work

pror erly How can 1 gel around this?
A:Use the externa! hardware reset condition Actvate
M1 for a mnimum of two clock cycles without
act1vating either RO of IORQ.
Q: When using lhe PIO in Mode 2, a 55h 1s written to
the port Onthe port side. an OAAh 1s storobed
1ntothe port. via BSTB When the processor reads
the data pon,lhe 55h 1s read back instead of the
OAAh.Why and How?
A :The only way that the system can read the same
data that rt wrote into the PIO was if the ASTB
s1gnal was active (place lhe 55h onto the port bus)
afld the BSTB went active to strobe it mio the data
reg1ster.Suggest that system log1c inhibit bolh
strobe s1gnals from be com1ng actrve dunng the
same time

3-133

Q:Onwhich clock edgeis the PIOreset (with M1active

and IORQ and AD inactiva)?
A: The actual reset function will take place when!he
M1 signa!goeslow active (must have been active
a mini mum of 2 clock cydes).

'LS123

O: Can the PIO catch pending interrupts while

interrupts are disabled?
A: Yes. Enabling the interrupts allow the interrupt daisy
chainlo function and the interrupl under service flip
flops to be set.

'LS123
B

O: A question carne in conceming how the ZSO

PIO handled its interrupts. Is the PIO capable of
storing pending interrupts or must aninterrupt be
serviced and cleared (via either RESET or RETI)
before anolher interrupt can be accepted?
A: lt seems thal the ZBO PIOinterrupt structureis
designad so that pendinginterrupts can be stored.
There are to caveats lo watch for in this however.
he only way to store a pending interrupt is while
another one is under
service,and only one pendinginterrupt can be
stored. Beaware that if you are operatingin Modes
0,1or 2. the transition of the STB signal can cause
new data to be latched into the input data register
and generate a
pendinginterrupt. Besurethat any previous data
can be read from the PIO before any new data is
strobedin.
The storage for pending interrupts is only one
deep. This means that a second interrupt conrtion
cannot be stored if the first one has not been
acknowtedged.

O:Does aninterrupt maskword have to follow the

interrupl control word (assuming bit 4 was set) if
the PIOis not programmed for Mode 3 operation?
A: Ye. Follow!he interrupt control word with a
dummy write lo reset the PIO's write control
logic.

O: How can you get two PIOs to talk with each other
in

Mode 2 operation?
N Suggest using ARDY1 andBRDY2 to generate astrobe
pulse for ASTB1 and BSTB2. Sama setup could be
used tor ARDY2 and BRDY1 anc1 for ASTB2 and
BSTB1 .The logic basically consists e>f a 74LS123
(one shot) and a 74LS08 (ANO gate). The ARDY1
and BROY2 s1gnals are ANDedtogether and
suppiled as B TRG for generating ASTB1 and
BSTB2. The ARDY2 and BRDY2 signals are ANDed
together and supplied as the ATRG for generating
BSTB1 and AST82.The A TRG tor geneting
ASTB1andBST82is
alwayslow
(grounded).Inthts
manner.the port control signals are usedto set the
priority for strobe signa! generation.
Please refer to Figure 2 and Table 1.

Figure 2 . l/F circuit example

ARDYI 8RDY2 BRDY IARDY2

o
o

-lmm

l
l

-SS'l'IJ1 iredioo

1
1

oo

o
o

1
J

2-71

2-i> l

1
l

o
o

2-- l
,

1-72
1-::> 2
1
2

Table 1. Truth Table f or strobe signal generation

O: How can the PIO be reprogrammed without having

pending interrupts locking lhe system?
A:Try the lollowing procedure.

1. Disable

CPUinterrupts;

2. Disable interruptin the PIO;

3. Clear any pendinginterrupts wilhinlhe PIO by

using the interrupt control word with bit D4 set;
4. Reprogram the PIO as desired;and
5 Re-enable CPU interrupts.

O:The PIO generales false interrupts during the

program ming suence. What can cause this?

A:This symptom is almos! always the resull of a

program
ming error.Dependingupon the details of the
problem, there are severa!solutions.

1. The interrupts

shouldbe enabled las!inthe

initializa tionsequence.The lntenupt Control
Wordshouldbe written with interrupts disabled so
that the logical interrupt equationshould be set
(Mode3). Finish the
initiallzation with the lnterrupt Enable ConlrolWOrd
(83H)lo enable the interrupts.

2.Ttie STB and RDY signals should be in a

defined state. A transition on the STB input
could cause a
pendinginterrupt to be storedandexecuted

assoon
as nterrupts are enabled.
3.A change in bit pattem (whilein Mode 3) may
cause an interrupt. A detined state for extemal
inputsis recomrnended for power-up sequences.
O: How can 1 get aroundthe fact that only one "bit set"
can
be detected al a time in the OR bit mode?
A:one possibility would be to "mask" that bit during
the interrupt service routine. Another possibility is
to use externa! hardware to "mask" the bit.

o:

A : Use an externa! gate to qualify the dock input lo

lhe counter.

O: When does the time constant (from the time

constan! register) gel loaded into the downcounter?

A :Onlhe first down count --- ? verily.

Q:The CTC product specification

states that no
addit1onal wait states (other than the automatic wait
slate 1nserted by the CPU) are allowed in the 1/0
cycles. Why?
A : lt is not that the the wait states aren't allowed. il is
jusi that lhey don't accomplish any1hing.The dala will
arrive al a particular time for the read cycles, and the
interna! write strobe is generated as a result of the
clo<:k edges that willbe avalaible.Dunng the
readcycle. 1t is possible that an improper value of
the down-counter could be released onto lhe bus if
additional wait states were added (the counter
could change in the middle of the read operation).

How can 1 gelthe PIO to give me interrupts on

both transition of an input signal (Mode 3) ?
A: One method to use would require the PIO to be
repro grammed with a different logic equation
during the interrupt service routine for the lirst
transition.When the
second transition occurs, then a new interrupt can be
generated andthelogic equationcouldbeset back to
zao s10
its original state. Another method wouldrequire the
use of extemal hardware to change the state of
This sectioncontainsthe rnost commonly asked queslions
interrupting bit.
about the Zilog SIO. hey are dividedinto followinggroups.
Sorne possiblelogic could be to use an output
portalong
Features
with an exclusive-or (XOR) gale to controlthe state
of theinput bits.
Registers

Z80 CTC
O:How does the software reset commandto the CTC
affect the rest of the CTC's operation?
A : The data book and the technical manual differ in
the inforrnation that ispresenledon thissubject. A
software reset command stop the counter from
counting any further. In arder to start the counter
again, a new time constant must be loadedinto the
time constant register. AH bits in a mode control word
will cause the operation of the CTC to be affected.

O:What is the maxmum frequency of the counter?

A:11 extemalinput is synchronized to the system clock,
it's hall that of the CLK (system clock) input. lf it's
not, 1/3 of the system clock.
OAre there any other uses far the CTC besides
counting and timing?
A:Yes,the CTC makes a very nice interrupt controller
for

lhe280 bus.By programmingthe counter tor a

terminal count of one and delirnng the transition of
the lrigger, you can interface non-vectored
interrupting devices onto the 280 bus.
Q How can 1 have control overan individual counter

sothat it cannot be started. stopped, and s1arted

again?

lnterrupt
Modem control signals

Enable & Disable Tx & Rx. Auto enable mode

Questions around DMA
lntemal timings
Externa!interface
Asynchronous mode of operation
Synchronous mode
Questions about SDLC mode

Features
O: What is the maximum data rate of the SIO?
A: 1/5 of the system clock rate. So it is 1.6Mbls

max for 8MHz version

Q: What are the differences between 280 SIO/O, /1 ,/2 and
/4?
A :The ditterences between those tour dev1ces 1s "a
com binatton of Channel 8 Modem s1gnals". In fact.
the SIO die itself has 41 pins intemally. But a 40
pin 01P pack age has only "40 PINs", so we
made three kinds of SIO's:
1. Z80 SIO/O: Have ali channel B modem signals,
exceptlxCB and RxCB, bonded togetherinternally .

3-135

in the service rout ne. The special condition locks

the FIFO and guarantee that 1he DMA will not
transter any character unllthe special condition has
beenservced.

2. 280 $1011: Lacks "OTRB"

3. 280 SI0/2 Lacks "SYNCB"
ForPLCCpackagesweare only offering "SI0/4",which
covers an, since PLCC has 44 p1ns to bond out ali
signals.
O: What are the drfferences between !he SIO and
ZBO DART?
A:The Z80 DART (DualAsynchronous
Receiverffransmit
ter)is the dvice which only supports asynchronous
mode of operation
The functionality,inlemal
architec ture and AC/OC characteristics are
identicallo the SIO
in asyncllronous mode Also pin assignment of it
is dentcal to Z80 SlO/O with the exception of
one signa! name. The "SYNC" pinonSIO/Ois "Al"
(Ringlndicator)
on S10/0. bu1thef unctionality is exaclly the same as
the
SIO/O tn asynchronous mode.

O: When a speaal conditlon occurs due to parity error.

will a receiveinterrupt for that byte still be
generated?
A: No.In the case ol Rece1ve nterrupton
Specalcondtion only mode, the interrupt will not
occur until after the character with the special
condition is read.In the case ol Receive inlerrupt
011 First characteror Special condi tion
mode,theinterruptis generated on every charac
ter whether or not it has a special condition.

Q: What is the funcfion ol the Error FIFO?

A:The Error FIFObuffers the error conditions status
bitslor each of the received characters
O: When should the status in RR1 be checked?

A: Atways read AR1 before reading the data

O: Whal mformation is contamed inlhe Error FIFO?

A:

Registers

oHow do you read the status regsters?

A ReadslromARO (Read RegisterO)
are accomplishedby
simply doing a read lrom the SIO RMds from
RRl or AR2 are accomphshed by writing a regisler
pointer to the SIO (WRO) and 1hen do1ng a read
operation
Q What happens when you read an empty
FIFQ? A You will read the last characterin the
bufler

O How do you avo1d an overruninlhe receiver FIFO?

Endof trame.CRC/Framingerror, Receive overrun

error and Parity enor These are alicontainedinAR1 as
well The other status offeredin AR 1is not part of an
Error FIFO.
The Overrun and Parily error bits are held 1nthe FIFO
untilthey are reset by 1ssuing the Error Reset Com
mand They willnot beoverwntten by new error informa
lion.

O: How many register po1nters does the SIO have?

A he SIO has one foreach channel So ils possibleto set
the pointers for each channel first, then access1ng
each channel's reg1ster afterward But its not
recommended, since program readability gets
worse,

A. The receivo buffer must be read before the recently

received data ch;iracter on the serial input
1s shfted nto the rece1ve data FIFO This FIFO is
three bytes deep. Ths. if the bufferis not read.the
fifth character thal jusi amved caused an overrun
condtion Thereis no set or reset bit to disable the
buffenng

rue

When the FIFO gets locked

to an enor
cond1tion. can 1t sttll rece1ve?
A he SIO contnues to rece1ve unttl an overrun
error occurs

lnterrupt
O W'hat are the various lnterruptng conditions?
A The SIO can generate 1nterrupts from 1he
rece1ver. Transmitter and Extemal/status for each
channel (6 sources) Thts 1s a list of ali
condit1ons that could poss1bly generate an
1nterrup1(one channel onlylisted).
Transm1tter

O When does the FlO bufferlock on an error

cond1tion?
A The eoeve data FIFO gets locked when the following
recetver mtenupt modes are selected:

Recetve mtemipt on SpeC1al condihon only

Receive mterrupt on First character or Special
conditoo.

Rece1ver

ransmit Butter Empty

Rece1ver Character Available,
Parity Error. Fram1ng Elror,
Receive Overrun Error

In bolh ot these modes the spec1al cond11ton

1nterrupt oc.curs atter the dlarJcler w11h the
specmlco11dlt1on has been road The enor status
has to be valid when read

ExlemaVStatus
ransition on
OCDJ

CTS. SyndHunl Transm1t,

Underrun/EOM,
BreaWAbort Oetection

can the IP bits be set while the SJOis servicing other

interrupts?
A:ves lf thernterruptingcondition has a higher priority
than
theinterrvpt currently being serviced it wll cause an
other rnterrupt, thus nesting the interrupt service.

A .Yes There aresevera!methods that canbe used to

elear the rnterrupt condrtions. lf 1t is a transmitter

interrupt. then !he transmitter must e1ther be loaded
wrth data or the Reset Transm1t lnterrupt Pendrng
command must be issued 11 theinterrupt is for
External/Status. thenlhe Reset ExtemaVStatus
lnterrupt command must be issued 11 the interrupt
is for a rece1ve character being available.t henthe
receive character must beread lf the nterrupt is for
an error condition, then the Error Reset command
must be given

How many levels of pending rnterrupls are there

0. and
how does the interna! daisy chain operate?

A .Eachpossiblesource of an interrupt (6possible} has

one fevel of pendmg mterrupts The interna! daisy
charn operares rn the same manner as would an
externa!
daisy chain

oDoes the AETI lnstruction reset any status

register? A:No.

11 the CPU does not have the Retum From

lnterrupt sequence (RETIinstruction on the Z80
CPU), how may the SIO be informed ol the
completion of interrupt
handl ng?
A This may be done by wting the Return From
lnterrupt comrnand (38h) to WRO in Channel A of
the SIO.
Q: Can the IUS bits be accessed?

A: No.

O When do IUS bits gel set?

A: TheIUS bits will be set dunng an interrupt
acknowledge cycle on the falling edge of RO.

O When respond1ng to an lnterrupt, can you have the

lollowing sequence.
lnt Ack, Oisable INT, RETI, Clear interrupt
condition?

A:No. The correct sequence is : lnt Ack, Disabfe

INT..
Reset

Willenabling
lnterruptafter
atransition
on
theSyncJHunt bit cause lnterrupt to oc:cur?
A No.ExtemaVStatus lnterrupt should be enabled belore
the transit1on occurs
Note lt is advisable to execute tha Reset
ExVStatus lnterrupt command in advance, so that
the status of ARO. bit 04 rellects the curren!
condition.
O

Wny is the Reset/Status lnterrupt command

recom mendedlo be used severa!times in SIO
setup?
A:Because many of the status brts that reflect
interrupting
condtions are latchedbits and needto bereset to
relleci current status rather than what may have
occurred due to ear11er lntarrupts (changas in
state).
O:Willthe SIO continua to request 1nterruptil!he
condrhon has not been satisfied?

O What cond11ions cause the transm1t IP to be set?

A. Either

the buffer empty or the flag alter CRC is

be1ng loaded.

O. How do the extemal/status bits aHect the interrupts?

A The external/status interrupt structure 1s affected by
bits 07-03 of ARO These bits can be "reset" by
e1ther a hardwarereset. a channel reset orby the
Reset Exter nal/Status command The first status
change on any one of the five bits after the reset will
cause an 1nterrupt to be issued and also willcause
alllive status bits lo be tatched. The fatch1ng effect
1s caused whether or not Extemal/Status 1nterrupts
are enabled lf the curren! status at the time ol reset
is dfferent than the latched status. lhen another
lnterrupt request 1s generated
immediately To clear the nterrupt structure. two
resets are necessary The configuration of theSIOcan
change the defint1on of sorne ot these s1gnals 11
the state of the bit changes across definition
boundanes an interrupt can be generated. lssue
the Reset External/Status lnterrupts cornmand after
definition To process an extenal!Status 1nterrupt.
the Reset Extemaf;Stalus lnterruptscommand must
be issued atter read1rig these status bits and before
tne RETI.
O.

Can you use the SIO without aninterrupt

acknowledge cycle sequence (280 CPU)?
A Resetthe responsble interrupt pend1ngbit (IP).The INT
fine willlollow the IP bit.

O 11 lhe CPU can beinterrupted but cannot be used

with vectored 1nterrupts, how should processing be
done?
A: lmmediately alter being interrupted, proceedin a man
ner similar to polling the SIO for both receive and
transm1t Altemalt vely the Status attects vector btl
(81t
02 rn WR1) may be set and a o byte placed into the
interrupt vector register(WR2 in channel 8) Then.
the contents of 1he interrupt vector reg1ster can be
used to determme the cause of the interrupt and the
channelon which the interrup1occurred.Thrs is
queed by reading reg1ster RA 1 of cnannelB.
Also. !El is tied high and M1 1s lted hrgh,No
equivalen! to an interrupl acl<nowledge 1s 1ssued.

3-137

l ! !; \I:. 3'1M'7JA

----------------------- - ==
o wnen 1nterlacing the SIO to the CPU other lhan the Z80
CPU,is rt poss1ble to assert M1 and IORQ at the
same ltme as the lnterrupt acknowledge cycie to
s1mulate Z80 trm1ng?

no max1mum specs on the RxC perrod. and lhe

edges are used to sample the data. lf there are no
edges. no data is sampled.

A The SIO requires "Interna! da1sy cha1n settle time" even

11 you don'Ihave devices other lhan the SIO on Enable&Disable Tx&Rx , Auto enable mode
the interrupl da1sy cham The period for that
purpose rs "M1 is active bul IORO is inacltve", and
O Whal happens to the character be1ng assembledif lhe
is alleas! 1OOnS (for 4MHz cfock Parameter # 16,
receiver becomes d1sabled?
IEHEO delay Irme)
A: Assembly of a character stops 1mrnediately and the
character islost.

Modem control signals

O What s the stale of lhe transmitter oulpulwhen dala
is no longer available in the follow1ng modes?

a) Asynchronous?
b)Synchronous
e) SDLC?
A a) In asynchronous modes, the transm1tter goes tnlo
a markmg state whenever all data has been sent
b) Inthe synchronous mode the SIO willsendout 16
bits ol CRC (2 bytes, 11 programmed and the
Transmrtter underrun/EOM atch has been reset)
followed by the appropnate number of Sync
character The line will lhen conltnue lo 1dte sync
characters
e) Inlhe SDLC mode lhe SIO w1ll send out 16 bits of
CRC (2 bytes ; 11 programmed and lhe
Transm1tter underrunJEOM Latch has been reset)
followed by the
SDLC flag character (7Eh). The hne willthen
contrnue loidte SDLC flag characters.

O What is the delay Irme for RTS/ to TxD?

A Two Tx clocks for asynctironous and synchronous, 7

O What happens to the characters already in the

rece1ve FIFO 11the receiver becomes disabled?
A They willremain 1nthe FIFO untilthey are either
readby the CPU or DMA, or until the channelis
resel.

O: When Auto enable bit is set, will OCD & CTS going
true cause an lnterrupt?

A: lnterrupl wtll occur only onlransilron of OCD &

CTS s1nce both are edge triggeredif WR 1,DO 1s set
for Ext lnt enable
However s1nce these are latched conditrons in Status
Register ARO (03 & D5). current status must only
read alter 1ssuing Reset ExVStatus lnterrupl
command.

OIn the auto enable mode whal happens when CTS

goes 1nactive (High) in the middle of transferring a
byte?

A' 11 lhe Auto Enable modes selected, ttie C TS pin is an

i (ldeally.
enable for
enable bit 1s
transm1tter
Transm1tter
ANOed with the status of CTS) So when CTS is
1nactive, transm1t stops 1mmedrately (The data
be1ng shifted out wrll be sending out completely,
however)

Tx clodls for SDLC

O What rs lhe delay time for the transm1t buffer empty to

RTS?
A Two Tx docks for asynchronous gate delays for synchro
nous and SDLC

O Does the frequency of the CTS or DCDs19nals have

any adverse affects on the External/Status lnterrupt'

(even 11aU1o enable 1s nol programmed)?
A
S1nce
every
transitton
locks
the
ExternaVSlatuslatches you could gel constant
1ntenupts (11 E)(temaltStatus lnterrupt are enabled)
or constant status latches
O: Is ti possibte to deacltvale the DTR output without
repro
gramm1ng WRS?
A Only by resetbng the channel or chip.

O Can vou gale data by strelch1ng ttie rece1ve clock?

A Youcanholdthccl ockunt1lyouhavevclhddata Thereare

Ouestions around DMA

Q Can lhe SIO operare with a DMA in full duplex on

each channel?

A No The SIOhas only one ready hneper channel and

can only operate 1n hall duptex mode.
lf full duplex operat1on is required under DMA
control, both channels A & B need to be used
:Onelor transm1t and onelor receive.
Q Can both channels make s1mu1taneous DMA requesls?

A Yes.

O What happens when youprogram the SIO tointerrupton

Butter Empty and the DMA to act on Butter Empty?
A This would not be a wise th1ng 10 do However lhe
lnterrupt occurs, the DMA will lake over the bus
before lnterrupt has acknowledged.The buffer wiU
beliDed by
lhe DMA and the fnterrupt Request willgo away due to
a Butter Fullcondibon and thelnterrup tAcknowledge

w1ll

3 138

occurcausingbusconfuson. The same thingoccurs

on Receive buffer empty interrupl and DMA on
Receive character.
How can the SIO OMA combination be used for
0 syn chronous communications and ensure that the

CRC
characters are afso transmitted?
A' Try the following procedure:

1 lnitialize

the S10for use of the AEADY funcllon

with a OMAcontroller andthenpoll(orinterrupt on)
exter naVstatus (nol transmit buffer empty).

lnffialize DMA controller for data lransfer and

bus ralease at end-of-block. 00 NOT ENABLE
DMA YETI
3 Send first byte of data to SIO for transmission
fol
lowed by a Reset Transmit Underrun/EOM Latch
command.
4 Enablethe DMA controller now (it should take
control of the bus).
5 When the end-of-blockis reached, the DMA
control
ler should releaselhe bus back to the CPU

o When doeslhe SIO tenninate the REAOY signa!?

A;The interrupt occurs a max1mum of 9 dock

periodsfrom the Txc clock edge that causes the
buffer to become empty.The exact time is highly
dependent upon the mode of operabon andis
transparent to the user
Q:Whenis the data available at the top of the FIFO?
A Data IS available after a maximum of 13 clock
periods from the rsrng edge of RxC.
Q: What is the del ay time between transm1t shrft reg1ster
to the TxD pin?
A:Two Tx clocks for asynchronous and synchronous
Seven Tx clocks (frve for zero inserter twolor 1ntemal
delay) for SOLC

Q: Does an lntenupt occur on RxC for tast data bit as

sembled or does 1t occur relativa to the RxC, but
de layad?
A: lnterrupt occurs when data is moved from the
receive shift reg1ster to FIFO.The relationship of
this even1rs relativa to an externa! dock edge.
Th1s relationship however, isof no concem to the
user.There1s.however a specific delay from the
extemal clock edge to the interrupt caused by
intemal SIO logic.

A The rising edge of the system clock that samplesIORQ

low causes REAOY to go inactive. The delay is speci
fied by parameter 19 in the data sheet.

O:When does the REAOY s1gnal become active alter an

access to the SIQ?
A:The READY signal will be inactiva for a mnimum of
5 dock cycles andwill become active again 700 nS
alter CE goes rnactive

Interna! tlming
O When the transmtter is dsabled. when does the

Externa! interface
O: Can a sloppy system clock cause problems in
SIO operation?
A. Yes. The specs on this system clock are verylight and
must be metto prevent SIOmalfunctiori The specrca
t1ons are

Symbol

Descriptron

VIHC
VIHL

Clod< "H"
Clocl< "L''

Min

Max

Vcc-0 6 5. 5
-0 3 0.45

TxD ne go to a marl<ing state?

A: One bi1 bme atter the last bi1 of the data leaves !he
transmit shift
reg1ster.

O When the transmitter is empty. does status register

ARO, bit 02 indicate that the buffer 1s now empty or
that the las! data in the buffer is in the process of
bemg shlt1ed out?

A 1t tncicates the buffer s now empty fhe status

register
has nothing to do wrth the transmit shift register.

O Doesthe Transmt intemrpt occurvien

TransmilBuffer

rs empty or Transmitteritself is empty?

A lnterrupt occurs when the Transmit Bufferis empty.

O.Howmany bit times from externa! clock 1s the

Clock nse/Fall time = 30nS each

edge
( or N-MOS,
deV1ce)
4MHz

Unit
Volt

Volt

Shouldthere be any ringingorundershooVovershoot on

the dock rnput the SIO could behalf in any number
of 1ndetennnable ways
Q Must the system clock, fed to !he SIO. have a 50%

duty cyde?

A: The duty cycle doesn't have to be 50% as long as the

mrnimum specrficatonis met
O.Areinput control finesto the SIOsynchron12ed to system
ciocks solhat gart>age may exist on the buses
anyt1me before setup requ1rements are satisfied?
A . Ys

Transmrt Bvtter Empty lnterrupt delayed?

3-139

Q; Since setup time for CE and JORO may be

satisfied during T2,is time T1 required?

.
.
.
A : u the Z80 CPU is being used, then T1 t1mmg stte
is
rired inorder to utilize theinterrupt structure.
(1nter rupt request. acknowledge, and RETI).
No, if not using the Z80.
Q:Dowart stales have to be addedto provide VO
response to the SIO in non Z80 based systems?
(The Z80 adds wait states automatically)
A :No.As long as setup times as specified for the
SIO are
mel. The SIO does nol know about wait states
mserted by!he Z80. The Z80 puts inwait states
inorder to match the Z80 SIO setup times.
Q:What pinsare noise sensitlve and should be
strappedto avoid strange interrupts?
A : The Ext Sync pin, andany Extstatus pinthatis
not used.
Also, ali inputs are sensitive to signal ringing and
undershoot probfems.
Q: Is M 1 required if no lnterrupts are usedin the SIO?

A :No.M1 should then belied high.

O:Can you uselhe Ready output for an lnterrupt
request? A:Yes.for byte move actioninor out and
Respondto lnter rupt. However,it is not recommended
to use Ready for
lnterrupt with lhe CPU.
O:How long must AD andlhe other control signals
remain actJve?
A: Although AD and IORQ are latchedinternally, they
must remain active lor a mnimum of two system
clock periods.

O:Are there any timing specilicalions for "Access

recovery

time"?

A:No.

A: No, X1 synchrontzalon can be selected but the

user must maintaindata synchronizationwithlhe
clock. The start bit detectionlogic does not work in
X1 mode and the 1.Sstopbit cannotbe used in X1
Inother words, Xl Mode for Async modeis NOT
asynchronous mode, its a "clocked serial channel".

O:What does the SIO recognize as the Break character ?

A:A character of all zeros including stop bits (indicating

a framing error)

O:When attemptinglo detecta break condition by

sensing the break/abort status bit, is it necessary
to enable Extemal/Status interrupts?
A- No The External/Status latches work regardless of
whether or not the external/status interrupts are en
abled.Th1s can be confusingbecause once the
latches are slrobed, the status in RRO is frozen
unlila Reset Extemal/Status lnterrupt command is
ssued. 11 you desire the true curren! status, issue
this command before read1ng ARO.

O:Can a break sequence be sent for a f1xed number or

character periods?
A: Yes. Break 1s continuously transmitted as logc 1
by setting bit 4 of WR5. You can t hen send
characters to the transmitter as long as the break
level persists. A Break signa!rather than
thecharacters sentis 1ransmil
ted. but each bit ot each character sent will be
cfocked asif it were transm1tted The Ali sent bit,bit
O or ARO, is set to 1 when the last bit of a
characler is clocked for
lransmission.This may be used to determine when
to reset bit 4 of WR5 and stop the Break signal.
O:lf a Break sequence is initiated by setting bit 4 of
WRS. will any character in the processof
beingtransmitted, be completed?
A: No. Break is etfective immediately when bit 4 of
WRS IS set. The "ali sent" bit in RR1 should be
monitored to determine when is safe to initiate a
Break sequence.

OWhen using the SIO only in Asynchronous mode,

Asynchronous Mode
O:Wtry are there different Clock factors?
A :These clocklactors enable the SIOto sample the
center
of the data cell.Inthe X 16 mode, the SIO divides
the bit cellinto 16 counts and samples on count s.

O: For asynchronous mode ol operat1on, must the ctock

rates selected be the same for Receiver andT
ransmit ter?
A :No.However, the multiplier for both RxC & TxC mus!
be the same because of interna/ logic.
OWhen runninginthe Async mode,isit necessary to
use the X16 dock scalar?

can the SYNC pin have any use?

A: lt may beusedas a general purpose input. For
example. by connecting it to a modem ring
indicator, thestatus of that ringindicator can be
monitored by the CPU.

O:Howcanthe SIObeusedto transmit characterscont

n ing fewer than 5 bits?
A: First, sel bit 6 and5 in WA5 to ndicate that five or
fewer bits per character will be transmilfed The
SIO then determines the number of bits to actually
transmilfrom the data byte tself. Thedata byte
shouldconsist of zero or more 1s. three zeros, and
the data tobetransmitted. Thus, be9inning the data
byte with 1111001 will cause only thelast bit to be
transmilted.

,
33-144c0
==========================::::::::::=-

,,.. . . . . . . . . . . . ----

Contents of data bytes(O=arbl!rary value)

07 D6 05 04 03 02 01
1

2
3
4

1
1
O

1 1 1 0 0
1 1 0 0 0
1 O O O d
0 0 0 d d
O O d d d

Q
d
d
d
d

d
d
d
d
d

synchronous Mode

o.Can you

cause interrupls on CRC error bit

(RR1 ;06)
changes?
A No.1he CRC error status 1s not one of the special
rece1ve condihons. Perhaps. explanation of cyclic re
dundancy block checkingand how the 810operates for
CRCis relevan!

CRC
Cyclic AedundanctChecking 1s a method of
checklng for errors in serial data transm1ssion. ltis
also known as the polynomial error code ched< The
polynomial is an algebraiclunction used to create a
constant from the message bit pattern This
constan!, generated and accumulated in both the
Transmitter and Receiver, is usedto divide the
binary numeric valueof the character The quotient is
discarded and the remainder added to the
nex1character wtlich again 1s divrded This contin
ues until!he last character when thc
rema1ri<1eristrans mit1ed to !he receiver for
compariso11 with the Re ceiver's remainder An
equal companson indicated no errors, while an
unequal companson rndicates an error in
transmission

SIO-CRC
The SIO conta1ns CRC generation and check1ng in
the
Transmitter and Aeceiver
11 allows for eilher of two polynom1als to be used.

a) xu+X'5+X2+1 Called CRC-16, generally used

insyn

chronous communicahon

b) X''+X'2+X5+1 CalledCRC CCITT, generallyused 1n

SDLC commun1cation and also recommended
by the CCITT

CRC Error Check

Status reg1ster AR1 which contains error concfrtions, al locates bit

06 for CRC error status Since CRC check mg is a contrnuous
process and takes place character

by character and intermediate results

are shitted 1nto the Rece1ve Error
FIFO continuously, bit 06 of RR1 is
continuously updated becauseit is not
latched.
However,check1nglhestatus ol th1s bit
alany rnterme diate point in time rn the
middle of a transmission 1s
meaningless. lt must be remembered
that the result of a CRC check 1s valid
only on completion ol a message
Also,in most cases, bit 06 will usually
be a "1" in lhe middle ot a message
since most serial bit combinatrons
result in a non-zero CRC. Unless it is at complellon of
a message transmiss1on.
The SIO does not generate an lnterrupt
lor CRC :.rror Status

Q:Suggest ahardwareway tocount or determine when

the

16 or 20 bit limes have passed befare

the CRC check is valid in BiSync
mode?
A: Allow two "buffer full" interrupts to occur
to determine that 16 b1tllmes have
elapsed, or have an externa! clod<
count 20 bit times

and read,wait forthe next receive characten nterrupted

andstop eRC
accumulation. then read the next received character
After the next character is mterrupted, d1sable the
re ce1ver and read the status byte

Q:In switched camer B1sync application the dock may

go away before CRC calculate is complete since
only one pad will be rece1ved. How can valid CRC
be ensured?
A: SIO spec requires al least two pads for a vald CRC
check in Bisync mode

Q:Is CRC enabled automatically atter first data in a

non SDLC node?

A. Only if itis programmed to be so.

Q Are Sync patterns (or flags) incfuded 1n CRC?
A SDLC - No

Yes for Bisync - CRC must be turned onloH as

required or Sync will beincluded in CRC

O: In synchronous mode, does CRC gel stripped

from data?

A Not normally, bu!it is possible if the CAC byte

happens to match the contents of WA6 and the
sync characier load mhibit teature is enabled.
Othel'Wlse, SIO won t delate the CRC bytes from the
data stream.

Q How do you read the CRC error status brt

when recerv ing data in the
mode?
A: This is ene possible method.

brsync

Al1er two CRC bytesnave been rece1ved

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-monosync and 16-bits for bisync). In order to

match on pattems that are not integer mulliples of
8-bits. the sync character must overlay the pattem
stored in the sync register, or use "Extemal Sync
mode''.

o:

What is the proper sequence for a valid reading of

the CRC error status bit?
A: To check the CRC error status andireadthe CRC
bytes. The followng sequence is recommended
because of delaysin Recerve logic and the 1ime al
which EOM lnterrupt occurs.

1 lnterrupl,read and discard - 1st CRC byte.

2 lnterrupt, read and discard - 2nd CAC byte.

3 lnterrupt, read 1st pad character and discard.
4. Disable CRC

5 lnterrupt. read CRC status then read 2nd

pad and discard.

Q:Are sync characters subject to

parily? A: No.
O: Assumi ng that there are characters available in the
FIFO,what happensto themif the receiver goes into
the hunt mode?
A: They will remainin the FIFOunlilthey are either
read by the CPU or DMA, or untl the channel is
resel.

O: In Monosync. is the Sync Comparison done in

the Receive shift register or the Sync register?
A: Sync comparison 1s done in the Sync Register
againsl the contents of WA7.

Q: Is sync characlerlransmission suppressed when

O: For Monosync, which regster contains the Sync

O:

char ac1er for comparison?

A: Wrile Register 7. Comparison is done in the Receive
Sync Register

O How does the SIO avoidlosing a single sync

character 1n the case of back-toback Bisync
messages that are separated by a single sync pad?
A: 11 does not. The SIOloses sync characters because
the
B1sync spec requires a mnimumof two
padcharacters.

O: Do Sync pattems (or flags) indata get stripped

andstill cause lnterrupfs?

the SIO is programmed for externa!sync operation?

A: Yes.
Howis rt possble far the SIOto achieve
synchronization on erroneous sync pattems (in
monosync and bisync modes)?
A: The design of the SIO is such that the sync
register serves as the CRC delay register atter
synchronization has been achieved.lf the SlO goes
out of synchroniza tion or is placed into the hunt
mode, the CRC delay register again becomes the
sync register but il's con tents are nolcleared.
Any data 1nit can be used by the comparison logic
for synchronizalion.The besl solution is to disable
the reoeiver each time you place 11 in hunt
modeandthen re-enableit This sequence will reset
the contents of the sync register.

A: AA leading sync pattems (and all flags) are stripped

automatically. In SDLC, sync characters (flags)
will cause lnterrupts if programmed to. Sync
characters may or may not be stripped inBisync
depending on the state of the Sync Character
Load
lnhibit
Bit
(WR3,01).
Any
data
slrippedlromthe data stream cannot cause a
receive character available interrupt but may
cause olherinterrupts (such as Extemal/status for
Sync/Hunt and special receive condihon for
EOM). In SDLC, programming Sync Character
Loadlnhibilwill cause stripping ol the address field
and not cause lnterrupts.

SDLC mode
O: How does the SIO send CRC?
A: The SIO can be programmed to automat1cally send
the CRC. Firsl.write the firstbyte of the message to be
sent. This guarantees the transmitteris full. Then.
reset the Transmit Underrun/EOM latch (WR0,10h}.
Write the
resi of tl'le data frame. When lhe transmit buffer
under
runs,
lhe
CRC
willbesent.
Thefollowmgtabledescnbes the action takenbythe
SIOfor the bit orentedprotocols.

O Do interrupts occur after each Sync pattem?

A Yes, i1 programmedlo do so (Extemal/Status nter

Tx Underrun

rupls).

EOM Latch Bit

O.Do sync pattems automalically gettransmitted m

Bisync
mode when Transmit Buffer becomes empty?
A. Yes.butlhe CRC bytesmay beallowedto
precede those sync characiers
OHow does the SIOhandle synchronous prolocols

which
use less than 8-bit sync characters?
A The sync charcter match log1c within the Sto only
mak.es companson on 8 bit boundanes (8-btts for

Action

Comment

Upon hUnderrun
Send CRC+Flags
Send Flags

Valid Frame
Software
CRC
Q:In SDLC mode, when do you get the End of Message
(EOM) mterrupt?

A.

The EOF interrupt occurs after the 1st CRC 1s

loadedto the lransmit buffer and 2 bit tmes before the
2nd CAC is loaded to the buffer

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How can you make sure lhat a flag is transm1t1ed

0 alter
CAC?

A: usethe extemal status Endof Message (EOM)

interrupt tostart the CAC transmission.then enable
the transmt buffer empty interrupt When you get
the interrupl, it
means that the buffer is empty, a flag 1sloaded n
the
shilt register, and you can send the next packet of
intonnalion.

o:When

using the SIOm the SDLC modeof operahon.

the transmrtter loses two data bits (gels shitted by
two bit positions) when the last character before lhe
closing flag 1s transmitted T ransmil dala is looped
to lhe recerver and CRC is not enabled?
A:The transmitter is working. The rece111er actually
causes the shft of two bits upon recognition of the
closng flag.

Q:Why s the second CRC byte inlherecerver FIFOnot

the f ull CRC byte?
A' The 2nd CRC byte readfrom the FIFO is not the full
8bit byte The transmitted byteis madeupof the
tasitwo bli s of the 1si CRC byte and the hrsl 6 bits
oflhe 2nd CRC byte. This is because of the delay rn
the Recei11e path and the point in time when the
EOM lnterrupt occurs causmg transfer of contents of
the Rece1ve Shift Regis
ler 1nto the FIFO.
However, since the above 2 bytes arelo be drscarded
by !he user, rt does not matter
Excepl in cases where users may want to nclude
two bytes of data inplace of CRC itis rmportantlo
note that the las! byte will be otf by two bits.

O In SOLC, when do you reset the CRC generator and

checker?

A: Thc reselTx CRC generator commandshoutd beissued

when transmitter 1s enabled and rdling (WRO) ThlS
needs to be done only once al 1nitralrzat1on time for
SDLC mode.

011 the SIO sidling flags and a byte ol data s toaded

nto the transmit butfer. what wrll be transm1tted?
Data takes pnonty o ver flags .
and
willbe loaded mto the
shift regrster and transmitted

A.

OWhat does the SENO ABORT commanddo to the

SDLC transmit sequenoe?
A The t ransmissron ol the curren!character IS aborted
and asequence ol 8one s are rnsertedintolhe data
stream Thrs means that the user may see between
8 and 13 one's in the data stream because ol the
zeroinserter.11 lhere is data 1nthe transmrl buffer 1t
1s destroyed anda T rnnsmit Buffer Empty rnterrupt
1s pended

O: Can the SIO detect multiple aborts?

A The SIO searches for seven consecuhve 1's on
the receive data line for the abort detectron
Ths condition may be allowed to cause an
extemal status interrupl After these seven 1s
are received, the receiver auto matically enters
Hunt mode,where it looks for llags So even if
more than se11en 1 s are rece111ed in case ol
multiple aborts. only the first sequence ol 1's is
srgnifi canl

O: In the SDLC rnode of operahon, what 1s the

O: Does Hunt 1nSDLC conllnue untilthe Address Fieldhas

been recogrnzed?
A lt does if the address search mode feature has been
programmed

O:Does IBM SOLC specify

parity? A No

O: Can the SIO include parity in SDLC mode'

A Yes 11 s appended at the end of the character

relahonship between lhe TxD output and

transmitter 1nterrupts?
A Transm1tter inlerrupts occur when the data from
the transm1t buffer rs loaded mto the transmit
shrft regster The output to the TxD pin is
delayed by 6 bit limes (flve for the zero inserler
and one for the prn delay)lrom the
last brtleaving the shft regrster

O: Is it possible to monitor all received characters,

nclud ing flags, in the SOLC mode?
A No if you want to monitor everything then use
the SIC in another mode ol operatron where the
sync pattern has no spec1almeaning

O. Can interrupts be generated on the 1dle lne

A

flag in SDLC?
Upon receiptof seven continuous ones. the
breaklabort bit will be set to 1ndicate the abort
condit1on Th1s brt will rema1n set unlilthe SIO
rece111es a zero

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