CPIT210 : Computer Organization and Architecture

Chapter 3: A Top Level View of Computer Function and

Interconnection
Tutorial
T.A. Khalid Alharbi
Department of Information Technology
Faculty of Computing and Information Technology
King Abdulaziz University

Problems:
3.1: The hypothetical machine of figure 3.4 also has two I/O instructions:
0011= Load AC fro I/O
0111= Store AC to I/O
In these cases the 12-bit address identifies a particular I/O device. Show the program
execution (using format of figure 3.5) for the following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.
Assume that the next value received from device 5 is 3 and that location 940 contains
value of 2.

0940

Memory
0002
..

1000
1001
1002

1000
3005

3005
5940
7006

PC
AC
IR
I/O AR
I/O BR

1001

1001

PC
AC
IR
I/O AR
I/O BR

3005
0005

3005
0005
0003
Step 3

Step 2

Step 1

1001
0003
3005
0005
0003
Step 4

PC
AC
IR
I/O AR
I/O BR

1001
0003
5940
0005
0003
Step 5

PC
AC
IR
I/O AR
I/O BR

1002
0005
7006
0005
0003
Step 7

PC
AC
IR
I/O AR
I/O BR

1003
0005
7006
0006
0003
Step 8

PC
AC
IR
I/O AR
I/O BR

3+2=5

1002
0005
5940
0005
0003
Step 6

1003
0005
7006
0006
0005
Step 9

PC
AC
IR
I/O AR
I/O BR

PC
AC
IR
I/O AR
I/O BR

PC
AC
IR
I/O AR
I/O BR

To device 6

3.2) The program execution of figure 3.5 is described in the text using six steps. Expand
the this description to show the use of the MAR and MBR.
Memory
300
1940
301
5941
302
2941

940
941

300
1940

0003
0002

PC
AC
IR
MAR
MBR

1940
0940

PC
AC
IR
MAR
MBR

Step 2

Step 1

301
0003
5941
0940
0003
Step 5

301

PC
AC
IR
MAR
MBR

302
00003
5941
0941
0003
Step 6

PC
AC
IR
MAR
MBR

301

PC
AC
IR
MAR
MBR

1940
0940
0003
Step 3

302
0003
5941
0941
0002
Step 7

PC
AC
IR
MAR
MBR

301
0003
1940
0940
0003
Step 4

302
0005
5941
0941
0002
Step 8
3+2=5

302
0005
2941
0941
0002
Step 9

PC
AC
IR
MAR
MBR

303
0005
2941
0941
0002
Step 10

PC
AC
IR
MAR
MBR

303
0005
2941
0941
0005
Step 11

PC
AC
IR
Memory
MAR
302
2941
MBR

940
941

0003
0005

PC
AC
IR
MAR
MBR

PC
AC
IR
MAR
MBR

3.3) Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed

of two fields: the first byte contains the opcode and the remainder the immediate
operand or an operand address.
a) What is the maximum directly addressable memory capacity (in bytes)?
= 2 24 Words

(Word=4 byte)

=2 24 X 4 bytes
b) Discuss the impact on the system speed if the microprocessor bus has
1. a 32-bit local address bus and a 16-bit local data bus, or
2. a 16-bit local address bus and a 16-bit local data bus.
If the address bus is 32 bits, the whole address can be transferred to memory at once
and decoded there; however, since the data bus is only 16 bits, it will require 2 bus
cycles (accesses to memory) to fetch the 32-bit instruction or operand.
In a hypothetical case of a 16-bit address bus, will have the processor perform two
transmissions in order to send to memory the whole 32-bit address; this will require
more complex memory interface control to latch the two halves of the address before it
performs an access to it. In addition to this two-step address issue, since the data bus is
also 16 bits, the microprocessor will need 2 bus cycles to fetch the 32-bit instruction or
operand.
C) How many bits are needed for the program counter and the instruction register?
PC= 24 bits

, IR= 32bits

3.4) Consider a hypothetical microprocessor generating a 16-bit address (for example,

assume that
the program counter and the address registers are 16 bits wide) and having a 16-bit data
bus.
A) What is the maximum memory address space that the processor can access directly if
it is connected to a 16-bit memory?
Max. memory address space= 216 X 2 bytes = 128 Kbytes
B) What is the maximum memory address space that the processor can access directly if
it is connected to a 8-bit memory?
Max. memory address space= 216 X 1 byte = 64 Kbytes
C) What architectural features will allow this microprocessor to access a separate I/O
space?
Having separate instructions for I/O operations in the Instruction Set of the
microprocessor would allow it to have a separate I/O space.
D) If an input and an output instruction can specify an 8-bit I/O port number, how many
8 bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain.
With an 8-bit I/O port number the microprocessor can support
28 = 256 unique 8-bit I/O ports.
With an 8-bit I/O port number the microprocessor can support
28 = 256 unique 16-bit I/O ports.
The size of the I/O port does not affect the number of I/O ports because the number of
I/O ports that can be supported only depends on the number of bits used to represent
the I/O port number which in both cases is 8 bits.