ECE 304: Current Mirror Solutions

Design of Bipolar Mirror

1. PAPER DESIGN. From Fig. 1
1. Compliance voltage VComp = 6V
2. Output DC current at V = VComp is IN = 7mA

Estimate RE from handout Eq. 2: RE (VCompBE)/IN 760.

From KVL in the reference side of the mirror, estimate R Val as
RVal(VCCVComp)/IN 1.29k.
Nearest 10% tolerance standard resistor values are RE = 820 and RVal =
1.2k.
2. PAPER ESTIMATE OF NORTON RESISTANCE

From CURRENT MIRROR handout, RN [1+ RE/(r + RE +REqui)]rO. To find

rO and r we put the paper design into PSPICE as shown in Fig. 1.

Figure 1: Schematic using paper design values of RE and RVal. Dummy source
"MIRROR" for current marker.

From the output file we find:

NAMEQ_Q2Q_Q1
MODELQ2N2222Q2N2222
RPI6.82E+026.87E+02
BETAAC1.81E+021.82E+02
RO1.06E+041.06E+04

Accordingly, we estimate the Norton resistance as R N 800k, close to the

specified value of 801k in Fig. 2. In fact, the PSPICE simulation below shows
this estimate is accurate, and RN is about 800k.
1

3. FIGURES

Figure 2: DC IV characteristic showing compliance voltage of VComp = 5.94V, slightly

better than spec, and output current of IN = 7mA, at spec.

Figure 3: PROBE plot of output resistance. RN = 801.267 k.

Figure 4: PROBE plot of the output capacitance of the current mirror. CN = 9.805 pF.

4. NORTON EQUIVALENT

The Norton equivalent circuit is a DC current source of value I N in parallel with the
Norton resistance of RN = 801k. Actually, because of the current drawn by the
Norton resistance, we should select IN a little smaller than the current mirror
output current at V = VComp so the total current (IN + VComp/RN) = IMirror. The result is
shown in Fig. 5.

Figure 5: Norton equivalent circuit. Dummy source "NORTON" for current marker.
5. TRANSIENT PROBE PLOTS

Running the schematic with the Norton equivalent and the current mirror on the
same schematic we can obtain plots like Fig. 2 and Fig. 5 of the handout.

Figure 6: Current mirror output current for VOUT = 10V and Vac = 2.4V, 3V, and 4.1V.

At Vac = 4.1V the current mirror output current shows a downward spike as a
result of driving the output transistor into saturation, suggesting the compliance
voltage is approximately 104.1 = 5.9V because there is some tolerance of
saturation.

Figure 7: Comparison of Norton equivalent and current mirror for VOUT = 10V and Vac =
4.1V.

It is clear that the Norton equivalent shows no spiking because it does not model
the mirror when saturation of the output transistor occurs.

Design of MOSFET Mirror

1. PAPER DESIGN. From Figs. 4 and 5
1. Compliance voltage VComp = 8.5V
2. Output DC current at V = VComp is IN = 6.6mA
3. Norton resistance at VComp = 21.5k
PAPERESTIMATEOFNORTONRESISTANCE

Unlike the bipolar case, we dont have an estimate for V GS analogous to the
bipolar estimate VBE =0.7V. Instead, we have to take into account that V GS varies
significantly with the current. Instead of using V GS as variable, the approach used
here is to find the unknowns RE, W/L, and RN in terms of the drain to source
voltage of the MOSFET VDS and to solve the equations using a spreadsheet, as
shown in Fig. 8.
Supply Voltage
Comp Voltage
DC Norton Current
Norton Resistance
IN*RN

VCC =
VC =
IN =
RN =
IN*RN =

First
Trial

Second
Trial

Third
Trial

15
8.57
6.57E-03
2.15E+04
141.255

KP =
5.0000E-05
Lambda = 2.0000E-02

GOAL

VDS
RE
W/L
4.8 573.8204 10.40716
4.9 558.5997 9.968524

IN*RN
144.65
140.81

gm
rO
0.002738 8340.944
0.002682 8356.164

4.81
4.82
4.83
4.84
4.85
4.86
4.87
4.88
4.89
4.9

572.2983
570.7763
569.2542
567.7321
566.21
564.688
563.1659
561.6438
560.1218
558.5997

10.36204
10.31721
10.27266
10.22839
10.1844
10.14068
10.09724
10.05406
10.01116
9.968524

144.26
143.87
143.48
143.10
142.71
142.33
141.95
141.56
141.19
140.81

0.002732
0.002726
0.00272
0.002715
0.002709
0.002704
0.002698
0.002693
0.002687
0.002682

8342.466
8343.988
8345.51
8347.032
8348.554
8350.076
8351.598
8353.12
8354.642
8356.164

4.88
4.881
4.882
4.883
4.884
4.885
4.886
4.887
4.888
4.889
4.89
4.891
4.892

561.6438
561.4916
561.3394
561.1872
561.035
560.8828
560.7306
560.5784
560.4262
560.274
560.1218
559.9696
559.8174

10.05406
10.04976
10.04546
10.04116
10.03687
10.03258
10.02829
10.024
10.01972
10.01544
10.01116
10.00688
10.00261

141.56
141.53
141.49
141.45
141.41
141.38
141.34
141.30
141.26
141.22
141.19
141.15
141.11

0.002693
0.002692
0.002692
0.002691
0.00269
0.00269
0.002689
0.002689
0.002688
0.002688
0.002687
0.002687
0.002686

8353.12
8353.272
8353.425
8353.577
8353.729
8353.881
8354.033
8354.186
8354.338
8354.49
8354.642
8354.795
8354.947

Figure 8: EXCEL spreadsheet used to find the correct values for MOSFET circuit. VDS is
incremented to find values that bracket the GOAL for INRN. Then the bracketed range of
VDS is subdivided and the process is repeated until the GOAL is determined to sufficient
accuracy.

SETTINGUPTHESPREADSHEET

First, we find an equation for RE. When the output voltage is at the
compliance voltage VC, the current IN flows thought RE, so KVL at the
output is VC = VDS + INRE, or RE = (VCVDS)/IN.
Second, we use small-signal analysis to find a formula for the small-signal
output resistance of the MOSFET current mirror. The result is
RN = rO + (1 + gmrO) RE. Multiplying by IN we find
INRN = INrO + (1 + gmrO)INRE = INrO + (1 + gmrO) (VC VDS)
From basic definitions, gm = {2INKp(W/L)(1+VDS)}1/2 and rO = (1+VDS)/
(IN).
Third, we note that when the MOSFET is on the border between the ohmic
and the active mode, the gate is Vto above the drain voltage, VG = VD +
Vto, or VGS = VDS + Vto. Therefore the current is given by IN =
Kp1/2(W/L)VDS2(1+VDS). This relation can be solved for W/L in terms of
VDS.
Putting formulas for RE, W/L and the product INRN into a spreadsheet as
shown in Fig. 8, we can tabulate all three quantities as a function of
VDS. Because the value of IN RN is known from the specifications, we
can search down the table until the tabulated values of I NRN bracket
the known goal value. Then we can subdivide this bracketing interval
of VDS and so forth. Figure 8 shows three such trial subdivisions that
lead to the estimate VDS 4.9V, W/L 10 and RE 560. These
values then are our paper design. PSPICE can be used to refine the
design, if needed.
2. OUTPUT RESISTANCE OF THE MOSFET
g DS

I D
1W
I D

K p VGS Vto 2
VDS V
2 L
1 VDS
GS const

3. FIGURES

Figure 9: Schematic for paper design of MOSFET mirror at the compliance voltage.

Figure 10: DC IV characteristics of MOSFET current mirror showing compliance

voltage of VC 8.6V and Norton current of IN 6.6 mA.

Figure 11: AC small-signal output resistance of current mirror at VOUT = 8.6V showing RN
21.5 k.

Figure 12: Output capacitance of MOSFET mirror at VOUT = 8.6V.

4. NORTON EQUIVALENT

Figure 13: Norton equivalent of MOSFET mirror. The Norton source has a value chosen
so the output current at the compliance voltage matches that of the current mirror.
5. TRANSIENT ANALYSIS

Figure 14: Transient analysis of current mirror for an AC output voltage of OUT(t) = 10V
+ Vac sin(2ft) with Vac = 1.4V, 1.6V, and 2V. At Vac = 2V the output current is no longer
sinusoidal and dips to a lower value than the sinusoid, indicating that the output
MOSFET has left the active region and gone ohmic. The compliance voltage is about 10
2 = 8V, showing some tolerance of entering the ohmic mode of operation.

Figure 15: Comparison of Norton equivalent and MOSFET mirror for Vac = 2V. Unlike the
MOSFET mirror, the Norton equivalent shows no distortion when the output MOSFET
goes into the Ohmic mode. The Norton equivalent does not work in this regime.