4614

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014

Hybrid Multilevel Inverter Using

Switched Capacitor Units
Ebrahim Babaei, Member, IEEE, and Saeed Sheermohammadzadeh Gowgani

AbstractIn this paper, two new topologies are proposed for

multilevel inverters. The proposed topologies consist of a combination of the conventional series and the switched capacitor inverter
units. The proposed topologies reduce the number of switches and
isolated dc voltage sources, the variety of the dc voltage source
values, and the size and cost of the system in comparison with
the conventional topologies. In addition, the proposed topologies
can double the input voltage without a transformer. There is no
need for complicated methods to balance the capacitor voltage.
The simulation and experimental results of single-phase 25- and
17-level inverters are given to prove the correct operation of the
proposed topologies.

Fig. 1.

Basic unit.

Index TermsMultilevel inverter, series inverters, series

parallel connection, switched capacitor.

I. I NTRODUCTION

HE MULTILEVEL inverter is one of the most important converters in power electronic fields. Nowadays,
the renewable energy sources such as photovoltaic (PV) are
developing more and more. The multilevel inverters have been
considered as a key element in such grid-connected systems
[1][3]. Producing an acceptable sinusoidal voltage waveform
at the output and boosting the output voltage are two challenging issues [3]. Using a transformer in the boost multilevel
inverter increases the size and cost and decreases the efficiency
of the system due to its bulky inductors [4].
The switched capacitor multilevel inverter can produce the
desired sinusoidal voltage waveform and boost the input voltage without any bulky transformer [5]. Because of the inherent
voltage unbalancing of capacitors in the switched capacitor
multilevel inverters, using complicated capacitor voltage balancing is necessary. Capacitor voltage balancing techniques
will be more complex when higher number of voltage levels
is produced at the output [6][8]. In order to mitigate this
problem, the hybrid-source switched capacitor topologies can
be used. By using this kind of inverter with fewer switching
devices and simpler control methods, it is possible to achieve a
greater number of voltage levels at the output [9]. The hybridsource switched capacitor topologies can be used in electric
vehicle application and PV systems.

Manuscript received April 9, 2013; revised August 2, 2013; accepted

October 14, 2013. Date of publication November 20, 2013; date of current
version March 21, 2014.
The authors are with the Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz 51664, Iran (e-mail: e-babaei@tabrizu.ac.ir;
sheerster@gmail.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2013.2290769

Fig. 2. (a) Capacitor charging (vL = vc = vdc ). (b) Capacitor discharging

(iL = ic = is ).

The multilevel inverters that use seriesparallel connection

of dc voltage source and capacitors attract more attention due
to simple control for capacitor voltage control [5].
In this paper, two new topologies are proposed for multilevel
inverters. The proposed topologies work by combination of the
conventional series and the seriesparallel switched capacitor
multilevel inverters. The proposed topologies have a modular
structure and can benefit the advantages of the series multilevel
inverters [10][13]. The fundamental switching method is used
in this investigation. In addition, to produce all voltage levels
at the output (even and odd), a new algorithm for the determination of the magnitude of the isolated dc voltage sources is
proposed. Finally, the loss calculation is done, and the performance of the proposed topologies is verified by simulation and
experimental results of single-phase 25- and 17-level inverters.
II. BASIC U NIT
Fig. 1 shows the basic unit for the proposed multilevel
inverter. The switches P and S connect the capacitor in parallel
and series with the dc voltage source, respectively. When the
switch P is turned on, the capacitor is charged to the voltage
Vdc , and when the switch S is turned on, the capacitor starts to
discharge. It should be noted that the switches P and S have
complementary operation with each other. It means that, when
the switch P is on, the switch S must be off and vice versa.
Otherwise, a shorted circuit occurs across the dc voltage source.
When the switch S conducts, the diode D becomes reverse
biased and prevents capacitor discharging to the dc voltage
source. Thus, in the case of series connection of the capacitor
and dc voltage source (S is on), the capacitor current only flows
to the load. Fig. 2 shows the operating modes of the basic unit.

0278-0046 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

BABAEI AND GOWGANI: HYBRID MULTILEVEL INVERTER USING SWITCHED CAPACITOR UNITS

Fig. 3.

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Proposed switched capacitor unit.

III. P ROPOSED S WITCHED C APACITOR T OPOLOGY

Fig. 3 shows the proposed switched capacitor unit. This
topology is yield from series combination of several basic units.
In this figure, the switches Si (i = 1, 2, . . . , n) connect the
capacitors in series, and the switches Pi connect the capacitors
in parallel with the dc voltage sources. To produce zero and
negative voltage levels, an H-bridge has been used at the
output.
The blocked voltage by each switch in Fig. 3 is Vdc . Thus,
the proposed switched capacitor unit is also proper for a highfrequency application that is not the aim of this paper. The
other advantage of the proposed topology is the boosting ability
of the input dc voltage without using any transformer. This
feature reduces the size and cost of the system and increases
its efficiency.
The maximum numbers of output voltage levels (Nstep ),
required insulated-gate bipolar transistors (IGBTs) (NIGBT ),
and diodes (Ndiode ) for the proposed topology shown in Fig. 3
are calculated by the following equations, respectively,
Nstep = 2n + 3

(1)

NIGBT = 2n + 4

(2)

Ndiode = n

(3)

Fig. 4. (a) First proposed topology. (b) Second proposed topology.

The general form of the equations that show the number of

voltage levels and the number of IGBTs can be expressed as
follows:

k

(5)
Nstep = a (bnj + c) + d
j=1

NIGBT = 2

nj + ek + f

(6)

j=1

where a, b, c, d, e, and f are the integer numbers that depend

on the unit connection order.
In order to produce the maximum number of voltage levels
at the output with using a specified number of IGBTs, (6) can
be rewritten as follows:
NIGBT = 2(n1 + n2 + . . . + nk ) + ek + f = cte.

(7)

It can be concluded that

where n is the number of capacitors.
The maximum output voltage that can be produced (Vo,max )
is equal to
Vo,max = (n + 1)Vdc .

(4)

In order to reduce the capacitor voltage drop during the series

connection, the pulsewidth-modulation switching pattern can
be used between the ith and (i + 1)th consecutive voltage
levels (i = 0, 1, 2, . . . , n), which, in turn, will increase
the losses. On the other hand, more capacitors are needed
to produce more levels at the output. Greater number of series capacitors increases their voltage drop. Thus, generating
a desirable voltage waveform without using of filtering elements will be difficult and requires more complex switching
schemes.
To produce greater number of voltage levels at the output and
reduce the capacitor voltage drop, several units shown in Fig. 3
can be used in series. In this condition, the first unit, the second
unit, . . ., and the kth unit have n1 , n2 , . . . and nk capacitors
and dc voltage sources with magnitudes of V1 , V2 , . . . and Vk ,
respectively.

n1 + n2 + . . . + nk =

NIGBT ek f
= cte.
2

(8)

Considering (5) and (8), the number of voltage levels in (5) will
be maximum when the following condition is satisfied:
n1 = n2 = . . . = nk = n.

(9)

From (8)(10), Nstep is obtained as follows:

Nstep = a(bn + c)

NIGBT f
2n+e

+ d.

(10)

Equation (10) will be maximum when n gets its minimum

value. Thus, the proposed topologies produce the maximum
number of voltage levels at the output for n = 1. This result
is independent of the units connection order. The proposed
topologies have been presented in the next sections with considering n = 1.
A. First Proposed Topology
Fig. 4(a) shows the first proposed topology. In this topology,
the switched capacitor units have been connected in series by

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014

using H-bridges. Each unit can only produce positive voltage

levels. The H-bridge produces zero and negative voltage levels.
There are a lot of ways to determine the magnitude of the
dc voltage sources. Some of these algorithms are not able to
produce all voltage levels at the output, and some of them produce repetitive voltage levels. In order to prevent the mentioned
problems and produce the maximum number of voltage levels,
the magnitude of the dc voltage sources in the jth unit can be
as follows:
Vj = (5j1 )

V1 .

TABLE I
C ALCULATION OF D IFFERENT PARAMETERS OF THE
P ROPOSED T OPOLOGIES

(11)

Voltage and current ratings of the switches in a multilevel

inverter play important roles in the total cost of the inverter. In
all topologies, the currents of all switches are equal to the rated
current of the load. This is, however, not the case for the voltage. Hence, there is a need for a criterion to evaluate the
multilevel inverter from the viewpoint of blocked voltage by
power switches and the total cost of system. This criterion is
captioned as standing voltage [14]. The standing voltage is
equal to the sum of all blocked voltages by power switches in a
converter.
The standing voltage of the switches is equal to the sum of
the blocked voltages by switches S and P and the H-bridge
switches for all units.

TABLE II
C OMPARISON OF THE F IRST P ROPOSED T OPOLOGY W ITH THE
T OPOLOGIES P RESENTED IN [9] AND [15][19]

B. Second Proposed Topology

Fig. 4(b) shows the second proposed topology. In this topology, each unit is bypassed when the switch Pj and the diode
D2,j are on and the switch Zj is off. When the switch Zj is
on, the diode D2,j becomes reverse biased. Thus, the diode
D2,j prevents the backward current flowing during the unit
bypassing when an inductive load is used at the output. In other
words, the second proposed topology can produce the desirable
voltage waveforms for resistive loads. On the other hand, by
replacing the diode D2,j with a power electronic switch, the
second proposed topology can be used for resistive-inductive
loads.
The magnitude of the dc voltage sources and the number of
voltage levels can be calculated as follows:
Vj = (3j1 )

V1 .

(12)

The number of voltage levels (Nstep ), the number of required

IGBTs (NIGBT ), the number of diodes (Ndiode ), the maximum
output voltage (Vo,max ), the standing voltage of the switches
(Vstand ), the number of dc voltage sources (Ndc ), and the
variety of the dc voltage source magnitude (Nvariety ) can be
calculated for the first and second proposed topologies, as
shown in Table I.
IV. C OMPARISON OF THE P ROPOSED T OPOLOGIES W ITH
OTHER C ONVENTIONAL T OPOLOGIES
In this section, the first proposed topology has been compared with three main topologies of multilevel inverters,
namely, the diode-clamped multilevel one [15], capacitor-

clamped multilevel one [16], and cascaded multicell multilevel

one [17]. Also, the proposed topology has been compared
with a cascade-boost switched capacitor converter multilevel
inverter [18], a switched capacitor boost multilevel inverter
[19], and a hybrid-source switched capacitor multilevel inverter
[9]. Table II shows the numbers of switches, diodes, capacitors,
and voltage levels for the proposed topology and the topologies
presented in [9] and [15][19]. Table II proves the advantages
of the proposed topology.
In order to show the advantages of the proposed topologies
in comparison with some recently presented topologies that
use isolated dc voltage sources, the proposed topologies have
been compared with the cascaded multilevel inverter using
bidirectional switches (CMIBS) [14], cascaded multilevel inverter using binary units (CMIBU) [20], optimal topologies
for cascaded submultilevel inverters (OCSMI) [21], cascaded
multilevel inverter with reduced number of components for
high-voltage applications (CMIHV) [22], multilevel inverter
with reduced number of power electronic components (MIRC)
[23], and multilevel inverter using switched series/parallel dc
voltage sources (MISSP) [24] from different aspects.
Fig. 5 shows the number of required IGBTs for producing
specified voltage levels at the output of the proposed topologies
and the topologies presented in [19][24]. As can be seen,
the proposed topologies need fewer IGBTs for realized Nstep
voltage levels at the output.

BABAEI AND GOWGANI: HYBRID MULTILEVEL INVERTER USING SWITCHED CAPACITOR UNITS

4617

Fig. 5.

Comparison of the required numbers of IGBTs to realize Nstep .

Fig. 8. Comparison of the variety of dc source magnitude to realize Nstep .

Fig. 6.

Comparison of the required gate driving circuits to realize Nstep .

Fig. 9. Variation of G coefficient versus Nstep .

Fig. 7.

Comparison of the required dc voltage sources to realize Nstep .

Fig. 6 compares the topologies from the viewpoint of the gate

driving. The second proposed topology has a good agreement
with the topology presented in [19] and reduces the gate driving
circuits into the topologies presented in [20] and [22][24]. The
first proposed topology has reduced the gate driving circuits
into the topologies presented in [22] and [24].
Fig. 7 shows the required isolated dc voltage sources versus
a specified number voltage levels at the output. As seen, the
proposed topologies need fewer isolated dc voltage sources for
realizing Nstep voltage levels at the output.
The variations of the variety of the dc voltage source magnitude are shown in Fig. 8. The behavior of the first proposed
topology is accorded to the topology presented in [23] and has
less variety of dc voltage source magnitude than the topologies
presented in [19][22]. The second proposed topology has reduced the variety of dc voltage source magnitude in comparison
with the topologies presented in [19][22].
The cost of the multilevel inverter has a direct relationship
with the number of its components such as IGBTs, gate driving
circuits, and dc voltage sources. This is true for multilevel

Fig. 10. Comparison of the standing voltage to realize Nstep .

volume and size. Considering this fact, in order to compare the

proposed topologies with other multilevel topologies from the
viewpoint of cost and size, the G coefficient can be defined as
follows:
G = (NIGBT ) (Ndriver ) (Ndc ) (Nvariety ).

(27)

Fig. 9 shows the variation of G coefficient versus the number

of voltage levels at the output. The smaller G means lower
cost, weight, and size of the multilevel inverter. Fig. 9 shows
that the proposed topologies have lower cost and size than the
topologies presented in [19][24].
Fig. 10 shows the standing voltage versus the number of
voltage levels. The proposed topologies have a good behavior
in this comparison. In other words, the switches have less stress
than the other topologies.
V. C ALCULATION OF L OSSES
The loss calculations contain switching losses, capacitor
voltage ripple losses, and conduction losses of the capacitors

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The times tj, and tj, are calculated as follows, respectively,



(aj, 2 5j1 )V1
1
1
tj, = sin
(31)


Vref
aj, V1
1
tj, = sin1
(32)

Vref
where = 2fref and aj, can be obtained from the following
recursive relationship:
aj, = 5 aj1, 2
1
a0, = +
5


1 Nstep
+1
= 1, 2, . . . ,
2
5j

Fig. 11. Output voltage levels and sinusoidal reference signal.

and switches. The calculations have been done for the fundamental frequency switching scheme. Fig. 11 shows the output
voltage levels and the sinusoidal reference signal in this switching scheme. In this figure, Vref and fref show the magnitude
and frequency of reference signal, respectively. The number of
onoff times in one cycle and the conduction intervals of all
switches have been calculated as a function of output voltage
levels.

A. Losses Calculation for the First Proposed Topology

The calculation of losses for the first proposed topology
includes following sections.
1) Switching Losses: In this section, the switching losses
of the proposed topologies caused by the charging and the
discharging of the parasitic capacitance of the switches are
calculated. The number of on and off of the switches must be
determined in one cycle for this calculation. The number of
on and off of each of S, P , and T switches in the jth unit is
obtained as follows for one cycle:


Nstep
.
(28)
Nj = 4
5j
The total power loss due to the charging and the discharging
of the parasitic capacitance of the switches in one cycle is
calculated as follows:
Ppc

k



1
Nj 5Vj2
= Cpc
2
j=1

(29)

where Cpc is the parasitic capacitance of the switch.

2) Capacitor Losses: The capacitor loss calculation includes capacitor voltage ripple losses [4] and conduction losses.
The voltage ripple of the capacitor Cj is given by

Vj =

1
Cj

iL dt
tj,

where shows the times of ON states of the switch Sj in the

0 t (1/4fref ) interval.
The total power loss due to capacitor voltage ripple (Pr ) is
calculated as follows:

1
Cj (Vj )2
Pr = fref
2
j=1

tj,i

k
1 
iL
= fref

C
j=1 j i=1
k

0t

1
4fref

iL dt
. (34)

dt +
1
2fref

tj,i

tj,i

The total conduction loss due to of the internal resistance of the

capacitor (Pint ) is obtained by

1
tj,i
2fref tj,i



rint i2L dt+

Pint = 2fref
rint i2L dt

(35)
j=1 i=1

tj,i

1
2fref

tj,i

where rint is the internal resistance of the capacitor.

3) Conduction Losses of Switches: The total conduction
loss of the first proposed topology is equal to the sum of the
conduction losses of the switches S, P , and T and the diode D
Pcon = PcS + PcP + PcT + PcD .

(36)

It should be noted that the switches S and P operate in a

complementary manner. In one cycle, two T -type switches are
on. Thus, the total conduction loss can be calculated as follows:
Pcon = 2fref

k

j=1 i=1
tj,i

1
2fref

tj,i

ron i2L dt+



(30)

where tj, to tj, is the interval that the switch Sj is on and the
capacitor Cj is connected in series with the dc voltage sources
Vj . In this condition, the load current (iL ) flows through the
capacitor.

1
2fref

tj,i

tj,i

tj,

(33)

iL
2

tj,i

ron i2L
1

2fref tj,i
1
2fref tj,i

dt+

dt+
1
2fref

(ron +rD )

tj1,i

(ron + rD )

iL
2

dt

tj1,i

1
2fref

ron i2L dt

+2fref
0

(37)

BABAEI AND GOWGANI: HYBRID MULTILEVEL INVERTER USING SWITCHED CAPACITOR UNITS

4619

Fig. 12. (a) 25-level inverter based on the first proposed topology. (b) 17-level
inverter based on the second proposed topology.

where ron and rD show the internal resistances of the switch

and the diode, respectively.
Considering (29), (34), (35), and (37), the total loss of the
first proposed topology is given by
Ploss = Ppc + Pr + Pint + Pcon .

(38)

B. Loss Calculation for the Second Proposed Topology

The losses of the second proposed topology can be calculated
according to Section V-A. The number of on and off of each of
S, P , and Z switches in the jth unit is obtained as follows for
one cycle:


Nstep + 1
Nj = 4

1
.
(39)
3j
It should be noted that each T -type switch becomes on and off
once in one cycle.
The time interval that the switch Sj is on and the capacitor
Cj is connected in series with the dc voltage sources Vj (tj, to
tj, ) is obtained as follows:
 j

3 ( 13 ) V1
1
sin1
tj, =
(40)

 j
Vref
3 V1
1
tj, = sin1
(41)

Vref
where shows the times of ON states of the switch Sj in the
0 t (1/4fref ) interval


Nstep + 1
= 1, 2, . . . ,
.
(42)
2 3j
VI. S IMULATION AND E XPERIMENTAL R ESULTS
To examine the performance of the proposed topologies, a
simulation has been done for the single-phase 25- and 17-level
inverters to produce 50-Hz sinusoidal voltage waveforms with
the maximum level of 110 V at the output, based on the first and
second topologies, respectively. In the simulation, the PSCSD/
EMTDC software has been used. Fig. 12 shows the simulated
25- and 17-level inverter circuits. In addition, the experimental
prototypes have been implemented for both proposed topologies. The IGBTs utilized in the prototype are BUP306D with
internal antiparallel diodes. The fundamental switching scheme

Fig. 13. Simulated load voltage and current waveforms. (a) 25-level inverter.
(b) 17-level inverter.

has been used to generate gate commands in this study. In order

to generate gate switching signals, the 89C52 microcontroller
by ATMEL Company has been used. According to (11) and
(30), the magnitudes of the dc voltage sources must be chosen
9.2 and 46 V for the 25-level inverter. Considering (12) and
(37), the dc voltage sources are chosen 13.75 and 41.25 V for
the 17-level inverter. The tests have been done on an R L load
with the values of R = 20 and L = 100 mH for the 25-level
inverter and a resistive load R = 40 for the 17-level inverter.
Fig. 13 shows the load voltage and current for the 25- and
17-level inverters. The total harmonic distortion (THD) of the
simulated 25- and 17-level load voltages are 3.25% and 5.47%,
respectively. Due to low-pass filtering characteristic of the R
L, the load current shown in Fig. 13(a) is almost sinusoidal and
contains less high-order harmonics than the output voltage. The
THD of the current waveform is 0.78%.
Fig. 14 shows the capacitor voltage ripples for four cycles.
The maximum voltage ripple occurs when the switch S is on.
The simulation has been done under the following conditions. The IGBT/diode with the internal resistance ron = 0.5
and the snubber resistance rsn = 105 have been used. The
internal resistance of the capacitors has been assumed rint =
0.2 . From the simulation, the losses of the 25- and 17-level
inverters are 14.046 W and 12.815 W, respectively. From loss
calculations, the losses of the 25- and 17-level inverters are
13.796 W and 12.653 W, respectively.
Fig. 15 shows the experimental results of the 25- and
17-level inverters for the load voltage and current. Fig. 16 shows
the capacitor voltage ripples. The experimental results have a
good agreement with the simulation results.

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Fig. 15. Experimental load voltage and current. (a) 25-level inverter.
(b) 17-level inverter.

Fig. 14. Capacitor voltage ripples. (a) 25-level inverter. (b) 17-level inverter.

VII. C ONCLUSION
In this paper, two new topologies have been proposed for
multilevel inverters. The algorithms for the determination of the
dc voltage source values have been presented, and the optimal
number of switches and dc voltage sources to produce the

Fig. 16. Experimental capacitor voltage ripple. (a) 25-level inverter.

(b) 17-level inverter.

BABAEI AND GOWGANI: HYBRID MULTILEVEL INVERTER USING SWITCHED CAPACITOR UNITS

maximum number of voltage levels at the output has been

obtained. The loss calculations have been done. The number
of onoff times in one cycle and the conduction intervals of
all switches have been calculated as a function of the output
voltage levels. The proposed topologies reduce the number of
switches and isolated dc voltage sources, the variety of the
dc voltage source values, and size and cost of the system
in comparison with conventional series topologies. The first
proposed topology produces a 25-level voltage for all load
power factors by using 12 IGBTs, 2 diodes, and 2 isolated dc
voltage sources. The second proposed topology can generate
a 53-level voltage for resistive loads by using 13 IGBTs,
6 diodes, and 3 isolated dc voltage sources. In addition, the
proposed topologies can double the input voltage without any
transformer. The capacitor voltage is balanced by fundamental
frequency switching scheme, and there is no need for complicated switching patterns for this objective. Finally, the operation
correctness of the proposed topologies has been proved by the
simulation and experimental results of single-phase 25- and
17-level inverters.
R EFERENCES
[1] K. Bandara, T. Sweet, and J. Ekanayake, Photovoltaic applications for
off-grid electrification using novel multi-level inverter technology with
energy storage, Renew. Energy, vol. 37, no. 1, pp. 8288, Jan. 2012.
[2] J. Chavarria, D. Biel, F. Guinjoan, C. Meza, and J. J. Negroni, Energybalance control of PV cascaded multilevel grid-connected inverters under level-shifted and phase-shifted PWMs, IEEE Trans. Ind. Electron.,
vol. 60, no. 1, pp. 98111, Jan. 2013.
[3] N. A. Rahim, K. Chaniago, and J. Selvaraj, Single-phase seven-level
grid-connected inverter for photovoltaic system, IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 24352443, Jun. 2011.
[4] A. K. Pandam and Y. Suresh, Performance of cascaded multilevel inverter by employing single and three-phase transformers, IET Power
Electron., vol. 5, no. 9, pp. 16941705, Nov. 2012.
[5] Y. Hinago and H. Koizumi, A switched-capacitor inverter using series/
parallel conversion with inductive load, IEEE Trans. Ind. Electron.,
vol. 59, no. 2, pp. 878887, Feb. 2012.
[6] P. Roshankumar, P. P. Rajeevan, K. K.Mathew, J. I. Gopakumar, and
L. G. Leon, A five-level inverter topology with single dc supply by
cascading a flying capacitor inverter and an H-bridge, IEEE Trans. Power
Electron., vol. 27, no. 8, pp. 35053512, Aug. 2012.
[7] A. K. Sadigh, S. H. Hosseini, M. Sabahi, and G. B. Gharehpetian, Double flying capacitor multicell converter based on modified phase-shifted
pulsewidth modulation, IEEE Trans. Power Electron., vol. 25, no. 6,
pp. 15171526, Jun. 2010.
[8] Y. Ounejjar, K. A. Haddad, and L. A. Gregoire, Packed U-cells multilevel
converter topology: Theoretical study and experimental validation, IEEE
Trans. Ind. Electron., vol. 58, no. 4, pp. 12941306, Apr. 2011.
[9] S. Ding, M. Cheng, Z. Wang, K. T. Chau1, Y. Wang, and W. Wang, A
hybrid-source switched-capacitor multilevel converter for electric vehicles, in Proc. ICEMS, Incheon, South Korea, 2010, pp. 288292.
[10] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, A survey
on cascaded multilevel inverters, IEEE Trans. Ind. Electron., vol. 57,
no. 7, pp. 21972206, Jul. 2010.
[11] M. F. Kangarlu and E. Babaei, A generalized cascaded multilevel inverter
using series connection of submultilevel inverters, IEEE Trans. Power
Electron., vol. 28, no. 2, pp. 625636, Feb. 2013.
[12] K. N. V. Prasad, G. R. Kumar, T. V. Kiran, and G. S. Narayana, Comparison of different topologies of cascaded H-bridge multilevel inverter, in
Proc. ICCCI, Odisha, India, 2013, pp. 16.
[13] C. M. Young, N. Y. Chu, Y. C. Hsiao, and C. Z. Li, A single-phase
multilevel inverter with battery balancing, IEEE Trans. Ind. Electron.,
vol. 60, no. 5, pp. 19721978, May 2013.

4621

[14] E. Babaei, A cascade multilevel converter topology with reduced number

of switches, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 26572664,
Nov. 2008.
[15] A. Nabae, I. Takahashi, and H. Akagi, A new neutral point clamped
PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523,
Sep. 1981.
[16] J. S. Lai and F. Z. Peng, Multilevel convertersA new breed of power
converters, IEEE Trans. Ind. Electron., vol. 32, no. 3, pp. 509517,
May/Jun. 1996.
[17] P. Hammond, A new approach to enhance power quality for medium
voltage AC drives, IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202208,
Jan./Feb. 1997.
[18] B. Axelrod, Y. Berkovich, and A. Ioinovici, A cascade boost switchedcapacitor-converter two-level inverter with an optimized multilevel output
waveform, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 12,
pp. 27632770, Dec. 2005.
[19] M. S. W. Chan and K. T. Chau, A new switched-capacitor boostmultilevel inverter using partial charging, IEEE Trans. Circuits Syst. II,
Exp. Briefs, vol. 54, no. 12, pp. 11451149, Dec. 2007.
[20] E. Babaei and S. H. Hosseini, New cascaded multilevel inverter topology
with minimum number of switches, Energy Convers. Manage., vol. 50,
no. 11, pp. 27612767, Nov. 2009.
[21] E. Babaei, Optimal topologies for cascaded sub-multilevel converters,
J. Power Electron., vol. 10, no. 3, pp. 251261, May 2010.
[22] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, A new topology of
cascaded multilevel converters with reduced number of components for
high-voltage applications, IEEE Trans. Power Electron., vol. 26, no. 11,
pp. 31093118, Nov. 2011.
[23] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, A new multilevel converter topology with reduced number of power electronic components,
IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655667, Feb. 2012.
[24] Y. Hinago and H. Koizumi, A single-phase multilevel inverter using
switched series/parallel dc voltage sources, IEEE Trans. Ind. Electron.,
vol. 57, no. 8, pp. 26432650, Aug. 2010.

Ebrahim Babaei (M10) was born in Ahar, Iran,

in 1970. He received the B.S. and M.S. degrees
(first class honors) in electrical engineering from
the Department of Engineering, University of Tabriz,
Tabriz, Iran, in 1992 and 2001, respectively. He
received the Ph.D. degree in electrical engineering
from the Department of Electrical and Computer
Engineering, University of Tabriz, in 2007.
In 2004, he joined the Faculty of Electrical and
Computer Engineering, University of Tabriz, where
he was an Assistant Professor from 2007 to 2011
and has been an Associate Professor since 2011. He is the author of more
than 230 journal and conference papers. His current research interests include
the analysis and control of power electronic converters, matrix converters,
multilevel converters, flexible ac transmission system devices, power system
transients, and power system dynamics.

Saeed Sheermohammadzadeh Gowgani was born

in 1988. He received the B.S. degree in power
electric engineering from Shahid Madani University,
Tabriz, Iran, in 2010, and the M.S. degree in system
and power electronic engineering from the University of Tabriz, Tabriz, in 2013.
He is currently a Teacher at the University of
Applied Science and Technology of Tabriz, Iran. His
research interests include the analysis and control
of power electronic converters, switched capacitor
multilevel inverters, and grid-connected renewable
energy systems.