MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE

PS21564-P

INTEGRATED POWER FUNCTIONS

600V/15A low-loss 5th generation inverter bridge for three
phase DC-to-AC power conversion

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

For upper-leg IGBTS :Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.
For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply).
Input interface : 3, 5V line CMOS/TTL compatible. (High Active)
UL Approved : Yellow Card No. E80276

APPLICATION
AC100V~200V inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES

Dimensions in mm

TERMINAL CODE
3)
(0~

3.556

321

(2 DEPTH 2)
3.3

7.62 0.3

33

32

(4.62)

7.62 4 (=30.48)

(6.5)
(3.5)

31

(1.5)

1.25
2.5

(41)
42 0.15
49

1
(0.75)

10.5

6.5

35

(17.6)
17.4

34

0.5

35

15.25

1.75

654

1.2

987

0.5
(0.4)

( 1 5

( 3 0

(3.8)
DETAIL C

HEAT SINK SIDE

3.3

(0.5)

12 10
11

(1)

15 13
14

Type name , Lot No.

30.5

29
30

(17.6)
17.4

0.5
28 27 26 25 24 23 22 21 20 19 18 16
17

1
2
3
4
(2.056)
(0.5)
TERMINAL
5
3.556
6
7
(R0
.75
8
)
9
10
11
12
PCB
13
(1)
PATTERN 14
1.2
(1.5) SLIT
15
(ex. PCB LAYOUT)
16
Note1)
17
DETAIL A
18
19
20
21
1
0.5
22
0.5
0.5
23
24
(45
(45
)
)
25
26
27
28
29
30
TERMINAL 32, 35
TERMINAL 1,28
31
32
33
34
35
(0.278)

HEAT SINK SIDE

DETAIL D

All outer lead terminals are with Pb-free solder plating.

(0.5)

1.778 0.15

(0.5)

1.778 26 (=46.228)

VUFS
(UPG)
VUFB
VP1
(COM)
UP
VVFS
(VPG)
VVFB
VP1
(COM)
VP
VWFS
(WPG)
VWFB
VP1
(COM)
WP
(UNG)
VNO Note2)
UN
VN
WN
FO
CFO
CIN
VNC
VN1
(WNG)
(VNG)
P
U
V
W
N

B-B

Note 1 : In order to get enough creepage distance between the terminals, please take some countermeasure such as a slit on PCB.
2 : Treat the terminal VNO of PS21564-P as NC. (just the same as DIP-IPM ver.2) However, external connection of VNO with N terminals is necessary for PS21562-P or PS21563-P.

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)

CBW

CBW+

CBU+

CBV+
CBV

CBU

High-side input (PWM)

(5V line) (Note 1,2)

C1 : Tight tolerance, temp-compensated electrolytic type

(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2 : 0.22~2F R-category ceramic capacitor for noise filtering.

C2

(Note 8)

Input signal Input signal Input signal

conditioning conditioning conditioning

C1

Level shifter Level shifter Level shifter

Protection
circuit (UV)

Protection
circuit (UV)

(Note 6)

Protection
circuit (UV)

DIP-IPM
Drive circuit Drive circuit Drive circuit

Inrush current
limiter circuit
P

AC line input

H-side IGBTS

U
V

(Note 4)

W
C

Fig. 3

AC line output

N1

CIN

(Note 7)

VNC

Z : ZNR (Surge absorber)

C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).

L-side IGBTS

VNO

Drive circuit
Protection
circuit

Fo logic

Input signal conditioning

Control supply
Under-Voltage
protection

(Note 8)

FO CFO
Low-side input (PWM)
(5V line)
(Note 1, 2) Fault output (5V line)
(Note 3, 5)

Note1:
2:
3:
4:

5:
6:
7:
8:

VD
VNC
(15V line)

Input logic is high-active. There is a 2.5k (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10k resistance.
(see also Fig. 8)
The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22F, high voltage type) is recommended to be mounted close to
these P-N1 DC power input pins.
Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.))
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
Please leave VNO open. (no connect)
To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24V, 1W) nearby each pair of supply terminals.

Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT

DIP-IPM

Short Circuit Protective Function (SC) :

SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.

Drive circuit

IC (A)
H-side IGBTS

SC Protection
Trip Level

U
V
W

L-side IGBTS

External protection circuit

N1

Shunt Resistor

(Note 1)

VNC

C R

Drive circuit

CIN
B
C

Collector current
waveform

Protection circuit
(Note 2)

Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0s.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.

0
2

tw (s)

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted)
INVERTER PART
Symbol
VCC
VCC(surge)
VCES
IC
ICP
PC
Tj

Parameter

Condition
Applied between P-N

Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature

Ratings

Applied between P-N

Tf = 25C
Tf = 25C, less than 1ms
Tf = 25C, per 1 chip
(Note 1)

450
500
600
15
30
22.2
20~+125

Unit
V
V
V
A
A
W
C

Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ Tf 100C) however, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ Tf 100C).

CONTROL (PROTECTION) PART

Symbol

Parameter

Condition

VD

Control supply voltage

VDB

Control supply voltage

VIN

Input voltage

VFO
IFO
VSC

Fault output supply voltage

Fault output current
Current sensing input voltage

Applied between VP1-VNC, VN1-VNC

Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC

Ratings

Unit

20

20

0.5~VD+0.5

0.5~VD+0.5
1
0.5~VD+0.5

V
mA
V

Ratings

Unit

400

20~+100
40~+125

2500

Vrms

TOTAL SYSTEM
Symbol

Condition
VD = 13.5~16.5V, Inverter part
Tj = 125C, non-repetitive, less than 2 s
(Note 2)

Parameter
VCC(PROT) Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
Tf
Tstg
Storage temperature
Viso

60Hz, Sinusoidal, 1 minute,

All connected pins to heat-sink plate

Isolation voltage

Note 2 : Tf measurement point

Al Board Specification :
Dimensions : 10010010mm, Finishing : 12s, Warp : 50~100m
Control Terminals

FWDi Chip
18mm

IGBT/FWDi Chip

16mm
Al Board
Groove

IGBT Chip
N W V U P
Temperature
measurement point
(inside the AI board) Power Terminals

Temperature measurement
point (inside the AI board)

Silicon-grease should be applied evenly with a thickness of 100~200m

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
Rth(j-f)Q
Rth(j-f)F

Condition

Parameter
Junction to case thermal
resistance
(Note 3)

Inverter IGBT part (per 1/6 module)

Inverter FWD part (per 1/6 module)

Min.

Limits
Typ.

Unit

Max.
4.5

C/W

6.5

C/W

Note 3: Grease with good thermal conductivity should be applied evenly with about +100m~+200m on the contacting surface of DIP-IPM
and heat-sink.

ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted)

INVERTER PART
Symbol
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES

Condition

Parameter
Collector-emitter saturation
voltage
FWD forward voltage

VD = VDB = 15V
IC = 15A, Tj = 25C
VIN = 5V
IC = 15A, Tj = 125C
Tj = 25C, IC = 15A, VIN = 0V

Switching times

VCC = 300V, VD = VDB = 15V

IC = 15A, Tj = 125C, VIN = 0 5V
Inductive load (upper-lower arm)

Collector-emitter cut-off
current

VCE = VCES

Tj = 25C
Tj = 125C

Min.

Limits
Typ.

0.60

1.45
1.55
1.50
1.20
0.30
0.40
1.50
0.50

Max.
1.95
2.05
2.00
1.80

0.60
2.10
0.80
1
10

Min.

4.9

0.45
1.0
10.0
10.5
10.3
10.8
1.0
2.1
0.8

Limits
Typ.

1.5

1.8
2.3
1.4

Max.
5.00
0.40
7.00
0.55

0.95
0.52
2.0
12.0
12.5
12.5
13.0

2.6
2.1

Unit
V
V
s
s
s
s
s
mA

CONTROL (PROTECTION) PART

Symbol

ID

Parameter

Circuit current

Condition
VD = VDB = 15V
Total of VP1-VNC, VN1-VNC
VIN = 5V
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
VD = VDB = 15V Total of VP1-VNC, VN1-VNC
VIN = 0V
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
VSC = 0V, FO circuit pull-up to 5V with 10k
VSC = 1V, IFO = 1mA
Tf = 20~100C, VD = 15V
(Note 4)
VIN = 5V
Trip level
Reset level
Tj 125C
Trip level
Reset level
CFO = 22nF
(Note 5)

Unit

mA

V
VFOH
Fault output voltage
V
VFOL
V
VSC(ref)
Short circuit trip level
mA
Input current
IIN
V
UVDBt
V
Control supply under-voltage
UVDBr
protection
V
UVDt
V
UVDr
ms
Fault output pulse width
tFO
V
ON threshold voltage
Vth(on)
Applied between UP, VP, WP-VNC, UN, VN, WN-VNC
V
OFF threshold voltage
Vth(off)
Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is
less than 2.0 times of the current rating.
5 : Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure. The fault output pulse width tFO
depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 10-6 tFO [F].

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Condition

Parameter
Mounting torque
Weight
Heat-sink flatness

Mounting screw : M3

Recommended : 0.78 Nm
(Note 6)

Min.
0.59

50

Limits
Typ.

20

Max.
0.98

100

Unit
Nm
g
m

Note 6: Measurement point of heat-sink flatness

Measurement location

3mm

Heat-sink side

+
Heat-sink side

RECOMMENDED OPERATION CONDITIONS

Symbol

Parameter

VCC
VD
VDB
VD, VDB
tdead
fPWM

Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency

IO

Allowable r.m.s. current

PWIN(on)

Allowable minimum input

PWIN(off) pulse width

VNC

VNC variation

Recommended value
Min.
Typ.
Max.

Unit

0
13.5
13.0
1
2.0

300
15.0
15.0

400
16.5
18.5
1

20

V
V
V
V/s
s
kHz

7.5

4.8

0.3

Below rated current

0.5

Between rated current and

1.7 times of rated current

2.0

Between 1.7 times and

2.0 times of rated current

2.6

5.0

5.0

Condition
Applied between P-N
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal, Tf 100C
Tf 100C, Tj 125C
VCC = 300V, VD = VDB = 15V,
fPWM = 5kHz
P.F = 0.8, sinusoidal output
fPWM = 15kHz
Tf 100C, Tj 125C
(Note 7)
(Note 8)
200 VCC 350V,
13.5 VD 16.5V,
13.0 VDB 18.5V,
20C Tf 100C,
N-line wiring inductance less than
10nH
(Note 9)
Between VNC-N (including surge)

Arms

Note 7 : The allowable r.m.s. current value depends on the actual application conditions.
8 : The input pulse width less than PWIN(on) might make no response.
9 : IPM might not work properly or make response for the input signal with OFF pulse width less than PWIN(off).
Please refer to Fig.7.

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 4 THE DIP-IPM INTERNAL CIRCUIT

DIP-IPM

VUFB
VUFS
VP1
UP

HVIC1
VB

VCC

IGBT1

Di1

HO

IN

VS

COM

VVFB
VVFS
VP1
VP

HVIC2
VB

VCC

IGBT2

Di2

HO

IN

VS

COM

VWFB
VWFS

HVIC3

VP1

VCC

WP

IN

VB

IGBT3

Di3

HO

COM

VS

W
IGBT4

LVIC

Di4

UOUT

VN1

VCC

IGBT5

Di5

VOUT

UN

UN

VN

VN

WN

WN

Fo

Fo

IGBT6

Di6

WOUT
VNO
CIN

VNC

GND

CFO
VNO(NC)

CFO

CIN

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 5 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS

[A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input L : IGBT OFF.
a7. Input H : IGBT ON.
a8. IGBT OFF in spite of input H.

Lower-arms control
input

a6 a7

Protection circuit state

SET

Internal IGBT gate

RESET

a3
a2
a1

SC

a4

Output current Ic

a8
SC reference voltage

Sense voltage of the

shunt resistor
CR circuit time
constant DELAY
Error output Fo

a5

[B] Under-Voltage Protection (Lower-arm, UVD)

b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO operation starts.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state

Control supply voltage VD

RESET
UVDr

b1

SET

UVDt

b2

RESET
b6

b3
b4

b7

Output current Ic

Error output Fo

b5

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE

[C] Under-Voltage Protection (Upper-arm, UVDB)

c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input condition, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state

RESET

RESET

SET

UVDBr
Control supply voltage VDB

c1

UVDBt

c2

c5
c3
c4

c6

Output current Ic
High-level (no fault output)
Error output Fo

Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT

5V line

DIP-IPM

10k

UP,VP,WP,UN,VN,WN

MCU
Fo
VNC(Logic)
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the
wiring impedance of the printed circuit board.
The DIP-IPM input section integrates a 2.5k (min) pull-down resistor. Therefore, when using an external
filtering resistor, pay attention to the turn-on threshold voltage.

Fig. 7 WIRING CONNECTION OF SHUNT RESISTOR

DIP-IPM
Wiring inductance should be less than 10nH.
Equivalent to the inductance of a copper pattern
with length=17mm, width=3mm,
and thickness=100m

VNC

N
Shunt resistor
Please make the GND wiring connection
of shunt resistor to the VNC terminal
as close as possible.

Sep. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21564-P
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 8 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1:Tight tolerance temp-compensated electrolytic type
C2,C3: 0.22~2F R-category ceramic capacitor for noise filtering.
C2

VUFB

C1

VUFS

DIP-IPM
P
HVIC1

VP1
C3

UP

C2

VVFB

C1

VVFS
VP1

C3

VCC

VB

IN

HO

COM

VS

HVIC2
VCC

VB

IN

HO

COM

VS

VP

C2
C1

VWFS

CONTROLLER

HVIC3

VP1
C3

VWFB

VCC

VB

IN

HO

WP

COM

VS

LVIC
UOUT

VN1
VCC
C3
5V line
VOUT

UN
VN
WN
Fo

UN
VN

Too long wiring here might

cause short-circuit.

WOUT

WN
Fo

VNO

CIN

VNC

GND

VNO

CFO

C
CIN

CFO
C4(CFO )

15V line

Long GND wiring here might generate

noise to input and cause IGBT
malfunction.

B
C5

R1
Shunt
resistor

If this wiring is too long, the SC level

fluctuation might be larger and cause
SC malfunction.

N1

Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm)
2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler
or transformer isolation is possible.
3 : FO output is open drain type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 10k
resistor.
4 : FO output pulse width is determined by the external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22 nF tFO
= 1.8 ms (typ.))
5 : The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5k (min) pull-down resistor. Therefore, when
using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
6 : To prevent malfunction of protection, the wiring of A, B, C should be as short as possible.
7 : Please set the C5R1 time constant in the range 1.5~2s.
8 : Each capacitor should be located as nearby the pins of the DIP-IPM as possible.
9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. Approximately a 0.1~0.22F snubber capacitor between the P-N1 pins is recommended.
10 : Please leave VNO open. (no connect)
11 : To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24V, 1W) nearby each pair of supply terminals.

Sep. 2005