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Intel Architecture Design

Computing Environment:
End-to-End EDA Computing Solution

Shesha Krishnapura
Principal Engineer
IA Migration Program
Engineering Computing

March 2004
Topics

z Analyze Design Computing Need


z Envision Design Computing Model
z End-to-End Intel® Architecture (IA)
Design Computing Solution
z Linux* Platform Deployment at Intel

2
Intel and the Intel logo are trademarks or registered trademarks of Intel
Corporation or its subsidiaries in the United States and other countries.
Analyze Design Computing Need

z Estimating silicon design complexity and


computing need
– Device/transistor growth
– Computing need for the projected design
complexity
– Estimated computing mix (32- and 64-bit)
– Design productivity initiatives

3
Device/Transistor Growth
Pentium® processor family
Data is layout transistor count 512K L2 Cache
800 MHz BUS

Pentium® 4 processor
.13 micron • 55 M
Pentium® 4 processor
.18 micron • 42 M
Pentium® III processor
.18 micron • 28 M

Pentium® III processor


.25 micron • 9.5 M
Pentium® II processor
• 7.5 M
Pentium® Pro processor
• 5.5 M
Pentium® processor
• 3.1 M

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002
Tape Out

Intel® Xeon™ 2M L3 cache has approximately 100M more


transistors
4
Intel, the Intel logo, Pentium, and Xeon are trademarks or registered trademarks
of Intel Corporation or its subsidiaries in the United States and other countries.
Device/Transistor Growth
Itanium® processor family (IPF)

Data is schematic transistor count; rd


o wa n-
layout transistor count will be T llio or
incrementally more Bi sist
an n
Tr esig
D

Itanium® 2 processor 6M
Core: 40 M
Cache: 320 M
Itanium® 2 processor
Core: 40 M
Cache: 160 M
Itanium® processor
Core: 25 M
Cache: Off-Chip

1999 2001 2002 2003


Tape Out

IPF transistor count continues to increase

5
The Intel logo and Itanium are trademarks or registered trademarks of Intel
Corporation or its subsidiaries in the United States and other countries.
Processor Design Methods
Design Method A Design Method B

Full Chip and FUB Design Hierarchical Design


Inverter
3M Dev

Design Iteration
Design Iteration
HDL
HDL SCH LAY SCH
LAY

z Design’s complexity and logic z Definition of each unit differs at


(not number of transistors) each level in hierarchical design
determine the definition of the method
functional unit block (FUB) z No firm definition of FUB during
z Verification done at the FUB and design
full chip level z Verification done at selected nodes
z Synchronization of each design z No synchronization of design
state (HDL, SCH, LAY) all the time states (HDL, SCH, LAY) at any
given time

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Computing Need for FUB design Complexity
z A typical design case-study
– Approximately 450 functional unit blocks (FUBs)
– About 20 (FUBs) are over 1 million transistors (high end)
– Remaining 430 FUBs have fewer than 200K devices
– Required 64-bit computing capacity expected to be about 10%;
90% of the design need is 32-bit computing
z If FUB has fewer than 200K transistors
– 32-bit computing is sufficient
z If FUB size is more than 300K transistors
– 64-bit computing is required
– Exception: A 1-million-device FUB with many common units can be
designed with 32-bit computing by breaking FUB into smaller
“chunks” treated as black boxes to be managed at the interface level

Transistor count in FUB determines 32-bit versus 64-bit


computing capacity need

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Estimated Computing Mix (32-bit and 64-bit)
z Can the number of FUBs be small, with each FUB containing
more than 300k devices?
– Limiting FUB count to around 100 limits the design-team size and
makes better use of the 64-bit environment
– Verification flow takes a long time for large FUBs
• A 280K-device FUB requires 10 to 15 days for full performance
verification
• If design tool throughput increases dramatically, more 64-bit
computing can be used
z Difficulty
– Partitioning a design based on the number of devices in an FUB
is logically impossible
– FUB size will vary (small/medium/large)
– Though tool throughput is increasing, we still expect more than
50% of the FUBs to have fewer than 200K transistors
In the next 3 to 5 years, we expect our 32-bit and 64-bit EDA computing
mix to change to 70% to 30% from the current 90% to 10%
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Design Productivity Initiatives
z Cell-based design
– To reduce design computation time (capacity and runtime),
the industry is moving to design at the standard cell-level
rather than the transistor level
– The number of transistors on a common standard cell
ranges from 2 to 12
– Assuming 6 transistors for a standard cell, design throughput
increases 6 times, and computation decreases proportionately;
this reduces the need for 64-bit computing
z Increasing the throughput of design tools
– Electronic design automation (EDA) tools are improving,
some by as much as 5 times
z Reducing FUB count
– Keeping the logical partitioning of the design increases the
need for 64-bit computing
EDA tools and design methods define the 32-bit versus 64-bit
computing mix
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Introduction to IC Design Flow
z Front-end design
Logic
Architecture
Design

Front-end stages are independent of the process technology

z Back-end design
Circuit Layout Full Chip
Tape-out
Design Design Design

Back-end stages are dependent on the process technology

Commonly called pre-silicon design flow


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Details of IC Design Flow
Design specification Design capture in HDL
(Micro Architecture Spec – MAS) (Hardware description language =
Verilog*, VHDL) Front-end Design
Register transfer logic
Tape-in Tape-out (RTL) code
(technology independent)
GDS 70% of total
design compute
Physical verification cycles used
(Layout versus Schematic Checks, Simulation and verification
Design Rule Check,
Reliability Analysis (EM, IR, …) ) Process Design
Technology RTL Code Specification
File Rules File
GDS
Synthesis 30% of total
Extraction,
design compute
power, timing , SI verification Gate-level netlist
(SI = Signal Integrity) cycles used
(technology dependent)

GDS
Back-end Design
Physical design (Place, Route) Power and timing analysis

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*Other names and brands may be claimed as the property of others.
End-to-End IA Design Computing Solution
Logic Circuit
Architecture Layout FullChip Tapeout
Design Design

Pentium® 4, Pentium® M Intel® Xeon™ processors Itanium® 2, IA-32e


processors For Cache/CPU-intensive 32-bit processors
For CPU-intensive batch and batch and interactive design flows For large process
interactive design flows design flows

2003
Intel®
Centrino™ mobile All EDA ISVs aligned to
technology standard hardware/OS
platforms running
¾Intel® Pentium® M processor
Linux* on IA-32 and
¾Intel® 855 chipset family
¾Intel® PRO/Wireless 2100 network
Linux on IPF, and to
connection Compute Farms start releasing to
common OS roadmap
High-Bandwidth Network

Pentium® 4 processor Intel® Xeon™ and


with high-end graphics Itanium® 2
card processors with
large RAM
Tapeout
Engines File Servers
Workstations

12
Intel, the Intel logo, Pentium, Itanium, Xeon, and Centrino are trademarks or registered
trademarks of Intel Corporation or its subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others.
IA Design Computing Platforms
z Intel® Centrino™ mobile technology
– Mobile design platform: wired, wireless, and occasionally
unconnected
z Intel® Pentium® 4 and Pentium® M processors
– For CPU-intensive batch and interactive design flows
– Desktop workstation, laptop workstation, and back-room
compute servers
z Intel® Xeon™ processor
– For cache and CPU intensive batch and interactive
design flows
– Majority back room compute servers and some desktop
workstations
z Intel® Itanium® 2 and IA-32e processors
– For large process size design flows
– Back room compute servers

13
Intel, the Intel logo, Pentium, Itanium, Xeon, and Centrino are trademarks or registered
trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Computing Drivers in EDA Market

z Increased pre-silicon verification


z High degree of design automation
z Global design team and collaboration
Computing
growth
z Shorter product development time
z Nano-process technology
z Reduced headcount and cost

Design
complexity
growth

Time

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Computing Drivers in EDA Market
Challenging Trends Solution to Challenges
z Reducing design time z Increased design automation
– Shorter silicon product life due to – Enable reduction in design time and
faster product refresh cycle lower number of engineers
demanding quicker time to market – Better and more EDA tools being used
– Earlier 3-to-2-year projects are to achieve higher automation
now done in 18 to 12 months
z Increased computing cycles
z Reducing design cost – Higher degree of verification due to
– Fewer engineers; increased nanometer technology
engineer productivity; global team – More validation during pre-silicon
for cost advantage design stage to control # of tape- outs
– Silicon is now expected to go
production with 1 to 2 tape-outs z Global computing environment
– Connected and unconnected design
z Increasing design complexity model; mobility for productivity
– More devices due to integration of – Grid-based, scalable, seamless global
several functions computing infrastructure
– Nanometer process technology – Global collaboration environment

High degree of design automation and collaboration


Significantly higher and flexible global computing power
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Future Computing Model
Global IA Computing Environment
Trillions Petabytes
of Compute of Design
Cycles Data

Grid EDA Environment Based on IA

Compute Farms
Infrastructure
Distributed

• Seamless global
compute cycles
Tapeout File Servers
• Design data & EDA Workstations
Engines Vcc
license sharing
• Global IP protection W
GND
BL
BL#

16
Intel, the Intel logo, Pentium, Itanium, Xeon, and Centrino are trademarks or registered
trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Global Computing Environment Parameters
z Design computing environment
– Globally accessible
– Globally uniform
– Globally scalable
– Globally distributed
– Globally secured
z Emerging design computing trend
– Connected design environment is past and present…
– Connected and unconnected design environment is
the future
– Productivity improvement

We can do all of this with IA computing platforms

17
1998 Challenge and Results
z Challenge
– Confronted with rapidly accelerating costs, we needed a
solution that met escalating computing demands while
keeping costs in check
z Results
– Started in 1998 to move register transfer level (RTL)
validation environment of a lead CPU design
– Full production reached in 45 days
– Scaled batch farm from 100 systems to 1,200 systems in
60 days
– Stability of Linux* on Intel® architecture equaled current
UNIX* on RISC*
– Significant savings – 1/4th the cost, and 2 to 3 times the
performance

18
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others.
Where Are We Today?
z December 2003:
– Intel silicon design environment supports 16,000+
engineers at more than 45 design sites worldwide
– 300+ EDA applications, 540+ terabytes of design data
– 27,400+ Intel® architecture workstations and compute
servers running end-to-end, EDA design flows
– 3,600+ desktop Linux* workstations on Intel architecture
– 23,800+ Linux compute servers on Intel architecture in
compute server farms
– 99+% of capital purchase is Linux platform on Intel
architecture
– Less than 1% RISC* platform purchase due to tools
availability
– Total computing capacity – Intel architecture plus RISC:
– 48,600+ systems in 2003

Intel made the move to Linux-based, EDA solutions


19
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others.
Migration to Intel® Architecture –
2003 Status Compute Servers
Compute Server Metrics
z IA/Linux* represents 80+% of total
35000 installed base of 28,900+
IA/Linux 23860
30000
Installed System Count

IA/Windows z Typically high-density, 1U or 2U


25000 RISC
20000
12691 rack-mounted systems in data
15000
6348 centers
4031
1969
10000
1200
z Dual-processor for simultaneous job
5000 runs
0
1998 1999 2000 2001 2002 2003
Workstations/Desktops
z IA represents 85+% of total installed
Workstation/Desktop Metrics base of 19,700+
25000
IA/Linux
IA/Windows Laptops 3628 z Majority Microsoft Windows* XP
20000
Installed System Count

IA/Windows Desktops 1659


RISC 475
z Provide access to UNIX* applications
15000
144 through X11 window
10000
z Trend towards mobile computing
5000 (34% of installed base are laptops)
0 z Linux and Windows are both
1998 1999 2000 2001 2002 2003
growing segments

20
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others.
Migration to Intel Architecture
$824M in Capital Savings (1997 – 2004)
Annual
Annualgrowth
growthrate
ratefor
for
computing
computingcapacity
capacity==105%
105%
IA Migration Savings vs. Spending
$1 Billion
900M Yearly
RISC
800M Year $M’s
Accumulated Savings Replacements
Saved
due to IA Migration 700M

Accumulated Savings
’97-
97-’00 3,413 $99M
600M

IA Migration
2001 6,348 $143M
500M
2002 7,241 $210M
400M
2003 12,887 $330M
300M
2004 1,836 $41.6M
200M
100M Total $824M
0
1995 1996 1997 1998 1999 2000 2001 2002 2003 2004
Projected 2004
Capital Spend ($M) IA savings ($M) Savings

Above savings do not reflect an average 2x performance difference


between IA and RISC – Savings based on 1:1 system replacement

21
Electronic Design
Automation (EDA) Basics
Shesha Krishnapura
Intel® Architecture Migration Program
Engineering Computing

Main contributors:
Biswadeep Chatterjee, ADG/ICG, Intel
Anand Krishnamoorthy, Cadence Design
Systems, Inc

December 2003

Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
EDA Definition**
Short Definition

Electronic Design Automation (EDA):


The use of software to automate electronic
(digital and analog) design

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**Source: http://www.ece.lsu.edu/
EDA Definition**
Long definition

z Electronic design in which …


– The design is entered using design capture
tools …
– Or using a text editor and a hardware description
language, possibly consisting of “parts” from a
vendor’s library
z The functionality of the design is verified by
simulation
z The correctness, testability, and compliance of a
design is checked by software
z And the design is converted to producible form
using synthesis tools

24
**Source: http://www.ece.lsu.edu/
Introduction to IC Design Flow
z Front-end design
Logic
Architecture
Design

Front-end stages are independent of the process technology

z Back-end design
Circuit Layout Full Chip
Tape-out
Design Design Design

Back-end stages are dependent on the process technology

Commonly called pre-silicon design flow


25
Details of IC Design Flow
Design specification Design capture in HDL
(Micro Architecture Spec – MAS) (Hardware description language =
Verilog*, VHDL) Front-end Design
Register transfer logic
Tape-in Tape-out (RTL) code
(technology independent)
GDS 70% of total
design compute
Physical verification cycles used
(Layout versus Schematic Checks, Simulation and verification
Design Rule Check,
Reliability Analysis (EM, IR, …) ) Process Design
Technology RTL Code Specification
File Rules File
GDS
Synthesis 30% of total
Extraction,
design compute
power, timing , SI verification Gate-level netlist
(SI = Signal Integrity) cycles used
(technology dependent)

GDS
Back-end Design
Physical design (Place, Route) Power and timing analysis

26
*Other names and brands may be claimed as the property of others.
IC Design Classifications

z Based on application of IC

Digital Design Analog Design

z Based on level of design automation and


optimization

Custom Design Semi-custom Design ASIC Design

Commonly called silicon design


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ASIC and Semi-Custom Design Flow**
Design spec

Simulation and
RTL coding
verification

LEF RTL Tech .lib

Synthesis

Silicon virtual Power and timing


prototype verification

Modified netlist ASIC = application specific integrated circuit


LEF = library exchange format
DEF = design exchange format
Physical Tech = technology file
design .lib = library of cells
GDSII = graphic design system, 2nd generation

Extraction and physical GDSII


verification

28
**Source: Cadence Design Systems, Inc.
ASIC and Semi-Custom Design Flow**
(continued) Design spec

Simulation and NC-Sim*


RTL coding
verification NC-Verilog*

LEF RTL Tech .lib

RTL compiler
(Get2Chip) Synthesis
BuildGates*
CeltIC*,
VoltageStorm*, or
First Encounter* Silicon virtual Power and timing common
prototype verification timing engine

Modified netlist ASIC = application specific integrated circuit


LEF = library exchange format
DEF = design exchange format
PKS NanoRoute* Physical Tech = technology file
design .lib = library of cells
GDSII = graphic design system, 2nd generation
Fire & Ice*,
Assura*, Celtic*, Extraction and physical GDSII
VoltageStorm* verification

29
**Source: Cadence Design Systems, Inc. *Other names and brands may be claimed as the property of others.
Custom Design Flow**
Design spec

Schematic generation

Common database
Simulation and
verification

Layout generation

Final verification and


sign-off

GDS GDS = graphic design system

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**Source: Cadence Design Systems, Inc.
Custom Design Flow** (continued)
Design spec

Virtuoso*
Schematic
Editor Schematic generation

Common database
Spectre*,
UltraSim*
Simulation and
verification OpenAccess*
database

Virtuoso*
Layout Editor Layout generation

Assura*,
Spectre*,
Final verification and
Pacific sign-off

GDS GDS = graphic design system

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**Source: Cadence Design Systems, Inc. *Other names and brands may be claimed as the property of others.
Digital Design Characteristics**
z Mostly digital logic (greater than 90 percent)
z Large integrated circuits (greater than 1M
transistors)
z Medium-to-high speeds (50 MHz to more than
3 GHz)
z High number of clocks (1 to 50)
z Digital applications
– DSP and microprocessors
z Use of standard cell (pre-characterized) libraries
z Standardized methodologies preferred

**Source: Cadence Design Systems, Inc.

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Analog Design Characteristics**
z 100 percent custom logic
z Small integrated circuits (less than 1M transistors)
– Typical size is 50M to 300M transistors
z Very high speeds (greater than 1 GHz)
z Fewer clocks (1 to 5)
z Analog and custom applications
– ADC, DAC, modems
z Can work the design at various levels, including
transistor level
z Methodologies vary widely

33
**Source: Cadence Design Systems, Inc.
Computing Drivers in EDA Market

z Increased pre-silicon verification


z High degree of design automation
z Global design team and collaboration
Computing
growth
z Shorter product development time
z Nano-process technology
z Reduced headcount and cost

Design
complexity
growth

Time

34
Computing Drivers in EDA Market
Challenging Trends Solution to Challenges
z Reducing design time z Increased design automation
– Shorter silicon product life due to – Enable reduction in design time and
faster product refresh cycle lower number of engineers
demanding quicker time to market – Better and more EDA tools being used
– Earlier 3-to-2-year projects are to achieve higher automation
now done in 18 to 12 months
z Increased computing cycles
z Reducing design cost – Higher degree of verification due to
– Fewer engineers; increased nanometer technology
engineer productivity; global team – More validation during pre-silicon
for cost advantage design stage to control # of tape- outs
– Silicon is now expected to go
production with 1 to 2 tape-outs z Global computing environment
– Connected and unconnected design
z Increasing design complexity model; mobility for productivity
– More devices due to integration of – Grid-based, scalable, seamless global
several functions computing infrastructure
– Nanometer process technology – Global collaboration environment

High degree of design automation and collaboration


Significantly higher and flexible global computing power
35
EDA Market**
z From Q3 2002 to Q2 2003, the EDA EDA Market Share**
(Last 4 quarters: Q3'02-Q2'03)
market generated revenues of
approximately $3.3B** Others
8% Cadence
z Three of the top companies in Synopsys 34%
38%
the EDA market are:
– Cadence Design Systems, Inc.
– Mentor Graphics
– Synopsys, Inc.
Mentor Graphics
z Magma Design Automation, Inc. 20%

is an emerging EDA company; Cadence Synopsys


Mentor Graphics Others
at $25.82M revenue in Q3 2003***

Top EDA ISVs Q2’03 Q1’03 Q4’02 Q3’02 Total Revenue


Cadence $276,437 $255,876 $276,297 $327,236 $1,135,846

Mentor $157,468 $159,340 $180,116 $152,650 $649,574

Synopsys $292,028 $292,028 $268,136 $390,256 $1,242,448

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**Source: IDC
***Source: SEC filings for the company *Other names and brands may be claimed as the property of others.
EDA Conferences and Consortium
z Design Automation Conference (DAC) is the major EDA
event
– www.dac.com

z User group conferences allow end users and other


independent software vendors to participate
– International Cadence Users Group (ICU)
www.cadenceusers.org
– International Mentor Graphics Users Group (MUG)
www.mentorug.org
– Synopsys Users Group (SNUG)
www.snug-universal.org

z EDA Consortium provides support for EDA standards


– www.edac.org

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