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# ECOM, Lab 3:

## Frequency Response of Basic Amplification Stages

0. Introduction
This Lab deals with the analysis of the elements that impose frequency limitations on basic amplifying stages,
and the implementation of the shunt-peaked technique as bandwidth enhancer. It can be considered an extension
of Lab 2, since the circuit designed in Part 4 of that exercise will be used as a starting point.
Remember that the general goal is to design a circuit that amplifies an input signal with a maximum peak
amplitude of 40 mV. The amplifier should provide a precise voltage gain of 13.5180 (22.6 dB) and minimum
10 MHz bandwidth when loaded with a capacitor of 10 pF.
The expected duration of Lab 3 is one session, and you should complete the Pre-Lab before the Lab session. For
the Pre-Lab, you need to use some results obtained from Lab 2, thus it is important that you have completed it.
During the lab session you may also need to compare results against those obtained in Lab 2, thus please make
sure to have access to that report during the laboratory session.

## ECOM Electrnica de Comunicacions

Pre-lab 1
In this preliminary study you will investigate the causes of the frequency limitation observed in the 2-stage
amplifier designed in Lab 2, and calculate the value of a shunt-peaked inductor to extend the bandwidth and thus
fulfill the target gain and bandwidth specs.
In order to complete this pre-lab, you will need the results obtained in Part-2 and Part-4 of Lab 2.
Also, you will need the parasitic capacitances of the transistors. Use the values specified in Table I:
Drain/Source overlap capacitance
Gate oxide capacitance

COVERLAP=0,2 fF/m
COX=1,75 fF/m2

Table I

## Use this schematic as a starting point:

Figure 1

P1.1. Calculate the values of the capacitances CGS and CGD for each of the three transistors designed in the
circuit in Lab 2, taking the transistor widths finally chosen in that Lab.
P1.2. Calculate the input and output capacitances of each of the common-source and common-drain stages. Use
the Miller effect expressions to split Miller capacitances (those between input and output) into their input and
output equivalents 1. For the Miller effect, use the low-frequency voltage gains measured in Q2.3 and Q5.1 in
Lab 2.
P1.3. Calculate input and output resistances of each of the common-source and common-drain stages. For the
calculations, use the small-signal parameters measured in Q4.6 in Lab 2.
P1.4. Calculate the total capacitance and resistance at the input (Vin), intermediate (VoutCS, in Fig. 1), and
output (VoutCD) nodes (dont forget to include the 10 pF load in this last node). Calculate the frequency of the
pole associated to each node.
P1.5. Discuss how the poles calculated in the former section will affect the gain and bandwidth of the amplifier.
P1.6. You now want to extend the bandwidth of the common-source stage by using the shunt-peaked technique.
Calculate the value of the load inductor in order to achieve maximum bandwidth extension. Which is the
expected new bandwidth of this stage?
1

Except for the output of the common-drain; take this output capacitance as just the addition of capacitances connected to this
output node.

## Frequency Response of Basic Amplifying Stages

P1.7. Repeat the previous question but now for the objective of a maximally flat response.
P1.8. Draw a schematic to obtain, by simulation, the small-signal output impedance of the common-source
stage (including Res). Specify clearly the values of the DC voltage sources, the small signal sources, and
the variables to be measured.

Lab Part 1: Finding the input and output capacitances and resistances.
In this section, you want to obtain the input and output resistances and capacitances of each stage through
simulation, as you analytically did in P1.2 and P1.3 in the Pre-lab. You will measure the input and output
impedances of each stage and assume a single-pole approximation for each input and output. Therefore, we
assume that resistance will dominate the impedances for frequencies low enough, while capacitance will
dominate the impedance for frequencies high enough.
When the capacitance dominates the impedance, the magnitude of this impedance is

ZC

1
2 fC

## log Z C log 2 C log f

This means, that, if you make an .AC analysis and represent graphically the impedance vs. frequency, and you
represent both the X axis (frequency) and Y axis (impedance) in logarithmic scale, you will observe a pure linear
relationship. This lets you easily identify the region where capacitive behavior is dominant.
For practical reasons, you can continue using the library Practica2. Copy the cell TwoStage into four
different cells called TwoStageImpedance1, TwoStageImpedance2, TwoStageImpedance3. and
TwoStageImpedance4.
Open the cell called TwoStageImpedance1. Edit the schematic and delete the common-drain stage. Remove
also the 50 input impedance.
Open the ADE environment and set the variables their suitable values, making sure to set the suitable DC input
voltage, and have an AC excitation. Define an .AC analysis with a large enough frequency range (ex. 1 kHz to
100 GHz), and set as outputs to be plot the voltage and current of the small-signal source. Run the simulation and
represent graphically the input impedance of the common-source stage.
Q1.1. Capture the schematic and the graphical representation of the input impedance of the common-source
amplifier, with both axis in logarithmic scale and two markers in the resistive and capacitive regime. Which are
the input resistance and capacitance? Compare them to the values obtained in P1.2 and P1.3. Are we observing
CGD_M0 with its Miller effect?
Open the cell called TwoStageImpedance2. Edit the schematic and delete the common-drain stage. Connect
a DC current source at the output of the common-source, with zero DC current and AC current Iin_AC. Make
sure that this is the only AC excitation in your schematic.
Open the ADE environment and set the variables their suitable values. Define an .AC analysis with a large
enough frequency range (ex. 1 kHz to 100 GHz), and set as outputs to be plot the voltage and current of the
small-signal current source. Run the simulation and represent graphically the output impedance of the commonsource stage.
Q1.2. Capture the schematic and the graphical representation of the output impedance of the common-source
amplifier, with both axis in logarithmic scale and two markers in the resistive and capacitive regime. Which are
the output resistance and capacitance? Compare them to the values obtained in P1.2 and P1.3.

## Frequency Response of Basic Amplifying Stages

Open the cell called TwoStageImpedance3. Edit the schematic and delete the common-source stage and the
load capacitance. Connect a DC voltage source at the input of the common-drain, with DC voltage Vin_DC2 and
AC voltage Vin_AC. Make sure that this is the only AC excitation in your schematic.
Open the ADE environment and set the variables their suitable values. Define an .AC analysis with a large
enough frequency range (ex. 1 kHz to 100 GHz), and set as outputs to be plot the voltage and current of the
small-signal voltage source. Run the simulation and represent graphically the input impedance of the commondrain stage.
Q1.3. Capture the schematic and the graphical representation of the input impedance of the common-drain
amplifier, with both axis in logarithmic scale and markers. Which are the input resistance and capacitance?
Compare them to the values obtained in P1.2 and P1.3. Are we observing the Miller effect on M1?
Open the cell called TwoStageImpedance4. Edit the schematic and make sure to have a DC voltage at the
input of the common-drain stage. Delete the common-source stage and the load capacitance, and connect a DC
current source at the output of the common-drain, with zero DC current and AC current Iin_AC. Make sure that
this is the only AC excitation in your schematic.
Open the ADE environment and set the variables their suitable values. Define an .AC analysis with a large
enough frequency range (ex. 1 kHz to 100 GHz), and set as outputs to be plot the voltage and current of the
small-signal current source. Run the simulation and represent graphically the output impedance of the commondrain stage.
Q1.4. Capture the schematic and the graphical representation of the output impedance of the common-drain
amplifier, with both axis in logarithmic scale and markers. Which are the output resistance and capacitance?
Compare them to the values obtained in P1.2 and P1.3.

## Lab Part 2: Analysis of the frequency response

Once you have obtained the input and output resistances and capacitances of each stage, you can calculate the
frequencies of the circuit poles, after making the single-pole assumption for each node.
Q2.1. (to be completed after the lab session, as a discussion for your report). Repeat the calculations you did in
P1.4, now using the resistance and capacitance values obtained from simulation. Compare the frequencies of the
poles against those obtained in the Pre-Lab.

## Lab Part 3: Bandwidth extension.

Open the cell called TwoStage and copy it into a new cell called TwoStageShuntPeaked. Edit the
schematic and make sure to have a DC voltage source at the input, with DC voltage Vin_DC and AC voltage
Vin_AC. Insert an ideal inductor ind from the library analogLib, with inductance value Lshunt, in series with
the common-source resistance Res.
Open the ADE environment and set the variables their suitable values. Since the values in Q2.1 are similar to
those assumed in the pre-lab, you can use the inductor default value calculated in P1.6. Define an .AC analysis
from 100 kHz to 100 MHz. Define expressions for the voltage gain at the first and second stage, and total voltage
gains, and add them to the outputs to be plot.

Open the parametric analysis form, and select Parametric Set as Run Mode
. Insert
Lshunt as the Variable Name. Fill the Value List field with the inductor values you calculated in P1.6 and P1.7
(use space as separation) and the 0 value to compare with the case without inductor. Click on the green button
to start the analysis. You should get plots of the three voltage gains for each of the inductor values defined.

Q3.1. Capture the schematic and the representation of the gains for both inductor values. Did you get bandwidth
extension? Measure the bandwidth of the amplifier, for the different Lshunt values. Do you fulfill the specs? Did
you get maximally flat response?
Q3.2. (Optional) Use the parametric analysis tool to select the Lshunt value that provides a bandwidth equal or
higher than 10 MHz with the flattest response.