THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2009
1.

GENERAL INFORMATION
Practical 1
Introduction to VHDL Specification and Modeling of Digital Systems
and Tool Flow
0%
3
Estimated total
1
study hours :

Lecture

Online
 Lab

Other

Lab #:
Name of the Lab:
Lab Weighting:
Delivery mode:

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link:
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use Xilinx ISE in the implementation of digital systems
2. Describe Digital Systems using VHDL, in particular: write VHDL
code to a specified algorithm; create variables, signals and
components; and structurally map together an entity out of multiple
instantiated components

Recommended
prior knowledge
and skills3:

Course Staff

Position/Role

Cathy Radix

Lecturer

E-mail

Cathy.Radix@sta.uwi.tt

Azim Abdool

Instructor

azim.abdool@sta.uwi.tt

Phone
Office
Office

Hours
x3157 Rm 321, Mon/Tue
11am Blk 1
2pm
x2636 Rm 341/ Mon/
RTSG,
Thu
Blk 1
11am12pm

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Synthesize an HDL design using the Xilinx ISE tool flow
2. Use a Spartan series development board to implement a digital design and
on-board testing
3. Describe a digital design using VHDL when given an algorithm, and/or
given a structural model.

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:

Cognitive
Level
Synthesis
Application
Application

Not Applicable
-

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

4.

IN-LAB

Allotted Completion 3 hours

Time:
1 Computer
Required lab
1 Spartan 3 Toolkit
Equipment:

4.1. In-Lab Procedure

This practical session comprises four primary steps: you will create a new project, add design
files to the project, synthesize and implement the design.

Launch the ISE Project Navigator and Create a New Design Project

Create a folder on your shared drive (Z:) and name it your UWI Student ID number.
Select Start Programs Xilinx ISE Design Suite 11 ISE Project Navigator
Some pop-ups may appear with messages regarding reading a network directory or running
WebUpdate. Dismiss the popups to continue.
We will now create a new project using the new project wizard. From the project navigator select
File New Project
The New Project Wizard opens (Figure 1).

Figure 1: New Project Wizard Dialog

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Change the location of the project to the folder that you have created on your shared network
drive. Type in Practical1 into the project name text field and verify that HDL is selected as the
Top-level source type and click Next.
The New Project Wizard Device Properties window appears (Figure 2).

Figure 2: New Project Wizard - Device Properties Dialog

Select the following values in the New Project Wizard Device Properties window:

Product Category: All

Family: Spartan3
Device: XC3S1000 (or XC3S400 depending on the board you have been given)
Package: FT256
Speed: -5
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISim (VHDL/Verilog)
Preferred Language: VHDL. This will determine the default language for all processes
that generate HDL files.
Other properties can be left at their default values.

Click Next.
The Create New Source dialog will appear (Figure 3). You can use this dialog to create a new
HDL source file by defining the module name and ports. For now, we will continue on. Click
Next.
4

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Figure 3: New Project Wizard - Create New Source Dialog

The Add Existing Sources dialog appears (Figure 4). This dialog is useful if we have existing
sources which we can add to the project. However, again we will continue on. Click Next.

Figure 4: New Project Wizard - Add Existing Sources Dialog

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

The final window which appears in the process is the summary window (Figure 5). This gives a
brief summary of the options which you have selected until this point. Click on Finish.

Figure 5: New Project Wizard - Project Summary

After clicking on Finish, the Project Navigator main interface should be brought up.

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Around the Project Navigator Interface

The project navigator interface by default is subdivided into four panel sub-windows, as seen in
Figure 6.

Figure 6: Project Navigator

On the top left is the Design, Files and Libraries panels which include display and access to the
source files in the project, as well as access to running processes for the currently selected
source. At the bottom of the Project Navigator is the Console, Errors and Warnings panels which
display status messages, errors, and warnings. To the right is a multi-document interface (MDI)
window referred to as the Workspace. It enables you to view design reports, text files,
schematics, and simulation waveforms. Each window may be resized, undocked from Project
Navigator, moved to a new location within the main Project Navigator window, tiled, layered, or
closed. Panels may be opened or closed by using the View -> Panels -> * menu selections. The
default layout can always be restored by selecting View > Restore Default Layout.

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Adding Design Files

Select Project  New Source. The New Source Wizard Select Source Type dialog appears
(Figure 7).

Figure 7: New Source Wizard Select Source Type

Ensure that VHDL Module is selected from the list and type in up_down_counter_4bits into the
File name textbox. Click on Next.

Figure 8: New Source Wizard - Define Module Dialog

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

The New Source Wizard Define Module Dialog now comes up (Figure 8). Ensure that the
ports as show in the figure above are entered.
clock : in
count_direction : in
count_o : out. Ensure that the bus checkbox is ticked. The MSB should be 7 and LSB 0. This
means that the count_o port is defined as 8 bits wide, i.e. bits 7, 63, 2, 1 and 0.
After ensuring these settings have been entered, click Next.

Figure 9: New Source Wizard Summary

The final window in the New Source Wizard is the Summary dialog (Figure 9). Click on Finish.
A source file (up_down_counter_8bits.vhd) is produced with the information provided during
the New Source Wizard. In the ISE Text Editor, the ports are already declared in the HDL file,
and some of the basic file structure is already in place. Keywords are displayed in blue,
comments in green, and values are black. The file is color-coded to enhance readability and help
you recognize typographical errors.
Note that for this section, we have added a new source file that we are creating. Alternatively, we
could also add an existing source file by using the Project  Add Existing Source option.

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Coding the Architecture

At this point, we already have a large part of the basic structure of the file in place. Now edit the
entity declaration to include two more ports: reset and clock_enable, both being single bit wide
inputs.
You are required to code the architecture to the following algorithm.
up_down_counter (clock)
create internal counter cnt (of same width as output)
begin
if there is a rising edge of the clock signal
if reset is high then
clear all bits of cnt
elsif clock_enable is high then
if count_direction is high then
increment cnt
else
decrement cnt
end if
end if
count_o cnt
end if
end up_down_counter

Recall that since we are using if statements, you are required to create a process, as shown in
class to code the above solution.

10

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Synthesizing the Design Using XST

Now that we have created our design file, we can move on to synthesizing this design. In the
processes tab, double click on Synthesize (Figure 10).

Figure 10: Synthesizing

If you have coded correctly, then it should synthesize without errors or warnings. Please ask your
demonstrator for any assistance as required.
XST can generate a schematic representation of the HDL code that you have entered. A
schematic view of the code helps you analyze your design by displaying a graphical connection
between the various components that XST has inferred. There are two forms of the schematic
representation:

RTL View - Pre-optimization of the HDL code.

Technology View - Post-synthesis view of the HDL design mapped to the target
technology.

To view a schematic representation of your HDL code:

1. In the Processes tab, click the + next to Synthesize to expand the process hierarchy.
2. Double-click View RTL Schematic or View Technology Schematic.
3. If the Set RTL/Tech Viewer Startup Mode dialog appears, select Start with the Explorer
Wizard.
4. In the Create RTL Schematic start page, select all components from the Available Elements
list, then click the Add -> button to move the selected items to the Selected Elements list.
5. Click Create Schematic.
The RTL Viewer allows you to select the portions of the design to display as schematic. When
the schematic is displayed, double-click on the symbol to push into the schematic and view the
various design elements and connectivity. Right-click the schematic to view the various
operations that can be performed in the schematic viewer.
You have completed XST synthesis. An NGC file now exists for the design.
Now, in the HDL flow, we can perform a pre-synthesis simulation of this design (known as a
behavioural simulation). However, for the purposes of this practical, we shall only be
concentrating on on-board testing.
11

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Creating Cascaded Counters

Within this section, we will concern ourselves with cascading four (4) of the previously made 8
bit up/down counters. This is to say that we will create a 32-bit counter using a structural
approach, rather than the behavioural approach used in the creation of the 8 bit counter.
However, for testing on the board, we will concern ourselves with only the most significant 8
bits.
Now create a new source file for an entity with the following interface description:
clock, reset, clock_enable, count_direction input, 1 bit wide each
count_o output, 8 bits wide
Once this file has been created, right click on the file name in the design hierarchy and select
Set as top module (Figure 11).

Figure 11: Set As Top Module

Create a component declaration for the up_down_counter_8bits within the new file.
Within the architecture of this new cascaded counter, implement four component counters such
that the signals clock, reset and count direction are all tied to the port of the encapsulating entity.
The output of the most significant counter should map to the output of the encapsulating entity.
The clock_enable of the least significant counter should map to the input clock_enable of the
encapsulating entity.
The clock_enable of each downstream counter should map to the bitwise ANDing of the output
bits of the preceding counter entity.

12

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Before starting this structural approach, draw a diagram showing all of the connections described
above. In this diagram you should include, especially, the names of EACH signal that you intend
to use for the connections.

13

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Design Implementation

ISE manages the files created during implementation. The ISE tools use the settings that you
specified in the Process Properties dialog box. This gives you complete control over how a
design is processed. Typically, you set your options first. You then run through the entire flow
by running Implement Design. The Implement Design process includes the three sub-processes
Translate, Map and Place&Route. You can simply run the Implement Design process to
automate the running of all three sub-processes, or you may run the subprocesses individually.
However, before implementing the design, a user constraints file must be created. The User
Constraints File (UCF) is a text file and may be edited directly with a text editor.To facilitate
editing of this file, graphical tools are provided to create and edit constraints. The Constraints
Editor and PlanAhead are graphical tools that enable you to enter timing and I/O and placement
constraints.
Use PlanAhead to add and edit the pin locations and area group constraints defined in the
NGD file. PlanAhead writes the constraints to the project UCF file.
This section describes the creation of IOB assignments for several signals.
1. Select the top level module in the Sources window of the Design tab.
2. Click the + next to User Constraints to expand the process hierarchy in the Processes
window.
3. Double-click I/O Pin Planning (PlanAhead) - Post-Synthesis, located under User
Constraints.

Figure 12: Floorplan Area/IO/Logic - Post Synthesis

The software should prompt you to add a ucf file (Figure 13). Select Yes.

14

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Figure 13: UCF Creation Prompt

Select close on the Welcome screen and proceed into PlanAhead.

In the I/O Ports tab, expand the Scalar Ports tree under All ports. You will now create pin
assignments.
Locate the clock output signal, then click and drag it into the Package view and drop
it on the T9 pin location.
Alternatively, you can type the location in the Site field in the I/O Port Properties tab when the
I/O signal is selected.

Figure 14: Assigning IO pins from IO Port Properties

15

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Repeat the previous step to place the output pins as shown in Table 1.
Table 1: Pin Constraints

Design Port

FPGA Pin to be mapped to

clock
reset
clock_enable
count_direction
count_o(0)
count_o(1)
count_o(2)
count_o(3)
count_o(4)
count_o 5)
count_o(6)
count_o(7)

T9
any available pushbutton
any available switch
any available switch
K12 LED
P14 LED
L12 LED
N14 LED
P13 LED
N12 LED
P12 LED
P11 LED

Close PlanAhead by File  Exit.

Finally, run the Map and Place & Route Options to complete the design implementation.
Usually in the HDL design flow we may do timing simulations at this juncture, however, we will
bypass this simulation step and move on to programming our target device.

16

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Generating Programming File and Configuring Target

Double click on Generate Programming File in the process tab.

After this process completes, double click Configure Target Device. The ISE iMPACT window
should launch (Figure 15).

Figure 15: ISE iMPACT

Double click on Boundary Scan.

Right click and select Initialize Chain (Figure 16).

17

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Figure 16: Initialize Chain

Two devices should be detected. The window should then prompt you to assign the generated
bitstream. Assign it to the first device in the chain and bypass the second.
Program the first device by right clicking and selecting Program.
Ask your TA/Demonstrator for any assistance as required.
Does the system work as expected?

18

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

Proceed to post-lab exercise.

19

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:
Deliverables:

Not Applicable
-

End of Practical 1

20

Practical 1: Introduction to VHDL Specification and Modeling and Tool Flow

6.

APPENDIX INTRODUCTION TO THE SPARTAN-3 DEVELOPMENT BOARD

Detailed information can be found in the Spartan-3 starter kit user Guide, which is available
with course material distribution, or you may download from http://www.digilentinc.com).
Figure 17, taken from the user guide, provides an illustration of the board.

Figure 17: Illustration of Digilent Spartan-3 Development Board

Summary of Key Features

200,000 gate Spartan-3 xc3s00-4ft256 FPGA
- 4,320 logic cells (480 CLBs)
- 30K bits of distributed RAM
- 216K of BlockRAM
- 12 dedicated 18x18 multipliers
- 4 Digital Clock Managers (DCM)
- 173 User I/O pins
- 76 maximum differential I/O pairs
Push button switch to force FPGA configuration
LED indicates when FPGA is successfully configured
Three fourty-pin expansion connectors to extend functionality
JTAG port for low-cost download cable
Digilent JTAG download/debugging cable connects to PC parallel port
JTAG download/debug port compatible with the Xilinx Parallel-IV and MultiPRO
desktop tool
Power-on indicator LED
On-board 3.3V, 2.5V, and 1.2V regulators
2Mbit Xilinx XCF02S Platform-Flash, in-system programmable configuration PROM
1M-byte of fast asynchronous SRAM
3-bit, 8-color VGA display port
9-pin RS232 serial port
PS/2-style mouse/keyboard port
Four-character, seven-segment LED display
Eight slide switches
Eight individual LED outputs
Four momentary-contact push button switches
50 MHz crystal oscillator clock source
FPGA configuration mode selected via jumper settings

21