Abstract
This paper is a summary of the design process of an 8-bit 10MSPS pipelined analog to digital
converter (ADC). The intended focus of the project was the design of the operational transconductance
amplifier (OTA) that is the heart of the switched capacitor circuits that perform functions such as sampleand-hold and amplification by 2. It is the performance of these functional blocks that determine the
performance of the whole ADC. The ADC simulated performance was 7.0b ENOB while consuming
56.9mA from a 1.8V supply.
I. Introduction
There is nothing technically novel in this work. Working pipelined ADCs were designed and aptly
explained 20 years ago in references [1] and [2]. The design of an OTA is not new either; two simple and
direct designs of fully differential OTAs are presented in [3] with explanations of the design choices and a
thorough list of measured circuit metrics, such as DC gain, power consumption, and unity gain frequency.
However, the tools of design have changed since those papers were published, and this work aims to
elucidate a design method using Matlab/Simulink in addition to a traditional SPICE simulator for the system
verification of the ADC. After the specifications for blocks have been set by system level simulation, circuit
level design was done with SPICE. In this project, no chip was manufactured, so there are no measured data
to explain. However, there is a plethora of data output from design simulations available for explanation.
VIII. Conclusions
An 8b pipelined 10MSPS ADC was designed from the system level down to some of its critical
circuits. The OTA used in the switched capacitor amplifier and the switches and capacitors were designed
with considerations for noise and amplifier settling time given the conversion rate of 10MSPS and chosen
full-scale voltage of 1V. The stringent requirements of the gain error necessitate an amplifier with accurate
gain, such as that of a switched capacitor amplifier where the gain can be set by the matching of capacitors.
Switched capacitor amplifiers necessitate a fully differential OTA structure to minimize the effect of charge
injection from switches. A fully differential OTA necessitate the design of an effective common mode
feedback circuit. A more focused effort on the design of the OTA and the CMFB circuitry would improve
the simulated performance of the overall ADC.
Figure 4. Effect of input noise voltage variance (Vn2) on DNL and ENOB
Figure 5. Effect of gain error on DNL and ENOB if all stages have equivalent gain error (ideal gain = 2V/V)
Figure 6. Switch resistance with Vds swept 0V .. 500mV for W/L = 10*1um/0.18um
Figure 8. Schematic of 1-bit verilog-A ADC and switched capacitor sample and amplify by 2
Figure 10. Single stage folded cascode OTA with simple current mirror load
Figure 11. Single stage folded cascode OTA with cascoded current mirror load
Figure 12. Two-stage OTA with 82dB of DC gain (2.12mA total quiescent current)
Figure 13. OTA design with common-mode feedback circuit chosen for ADC
Figure 21. CMFB loop gain vs. DC value of CMFB control voltage
Figure 22. Switched capacitor x2 amplifier transient result for b = 0 (left) and b = 1 (right)
Figure 23. Switched capacitor x2 amplifier transient simulation with full-scale input step
Figure 25. 8b ADC transient output with input sinusoid at 365kHz, amplitude = 490mV
Figure 26. SNR, SINAD, and ENOB for 8b ADC with 365kHz input sinusoid, amplitude = 490mV
Figure 27. DNL of 8b ADC calculated by histogram method with sinusoid input
Figure 28. Current consumption of 8b ADC, fclk=10MHz, 365kHz sinusoid input with amplitude = 490mV
References
[1] B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar. A 12-Bit 1-Msample/s Capacitor ErrorAveraging Pipelined A/D Converter. IEEE Journal of Solid-State Circuits, pgs. 1324-1333, December
1988.
[2] S. Lewis and P. Gray. A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter. IEEE Journal of
Solid-State Circuits, pgs. 954-961, December 1987.
[3] M. Banu, J. Khoury, and Y. Tsividis. Fully Differential Operational Amplifiers with Accurate
Output Balancing. IEEE Journal of Solid-State Circuits, pgs. 1410 1414, December 1988.