GBTChipsetStatusandProductionPlans

PauloMoreira
OnbehalfoftheGBTteam
CERN
01February2013

http://cern.ch/projgbt

GBTProjectStatus

Outline

RadiationHardOpticalLinkArchitecture
TheGBTSystem
GBLDStatus
GBTIAStatus
GBTX:

DataBandwidth
ASICStatus
PackageStatus
TestingStatus

GBTSCAStatus
GBTBuildingBlocksStatus
GBTFPGAStatus
ExperimentsRequirements
GBTProjectFuture
Activities/Manpower/Budget

http://cern.ch/projgbt

GBTProjectStatus

RadiationHardOpticalLinkArchitecture

GBT

GBT
Versatile Link

FPGA

Timing & Trigger

Timing & Trigger

GBTIA
DAQ

GBTX

PD
DAQ

GBLD

LD

Slow Control

Slow Control

Custom ASICs
On-Detector
Radiation Hard Electronics

http://cern.ch/projgbt

Off-Detector
Commercial Off-The-Shelf (COTS)

GBTProjectStatus

TheGBTSystem
Externalclockreference
Clock[7:0]
E Port

FE
Module

eLink

GBTX

Phase Shifter

CLKReference/xPLL

E Port

GBLD

SER

SCR/ENC

ePLLTx

E Port

E Port

FE
Module

CDR

80,160and320Mb/sports

DEC/DSCR

clock

GBTIA

CLKManager

dataup

Phase Aligners+Ser/DesforE Ports

E Port

datadown

ePLLRx

E Port

FE
Module

E Port

One80Mb/sport

E Port

GBT SCA

JTAG

ControlLogic

Configuration
(eFuses+regBank)

I2CSlave

I2CMaster
I2C(light)

data
control

JTAG
Port

I2C
Port

clocks

http://cern.ch/projgbt

GBTProjectStatus

GBLDStatus

GBLDV4.0

Availableinsmallquantities

Fullyfunctional
Excellentperformance
Radiationhardnessproved
(Almost)productionready(V4.0):

IntegratedintheVTRxandVTTx

Problem:logicsynthesispartiallyremoved
theTMRinV4.0!
ThiswasnotthecasewithV3!

VersionV4.1correctsthisproblem:

Submission:

Onlythedigitallogicwillbechanged:

19th February2014
TMRlogicwassuccessfullytestedinthe
pastwithV3
Minimumrisk

LowpowerGBLD(LpGBLD)

Lowermodulationcurrent(12mAmax)

Prototyping:

Finaldesignreview:

1st February

Submission:

4.8Gb/s,preemphasison

Reducethepowerconsumption by40%
VCSELdriveronly:

19th February2013

Noriskinvolved,versionV4.1isthe
baseline!
IfsuccessfultheLpGBTwill(likely)become
thebaseline!

http://cern.ch/projgbt

GBTProjectStatus

Totaljitter:25ps

GBTIAStatus

GBTIAV1.0

Fabricatedin2008:
Fullyfunctional
Excellentperformance
IntegratedintheVTRx

GBTIAV2.0

Fabricatedin2012:
Fullyfunctionalandproductionready

Availableinsmallquantities
IntegratedintheVTRx

Addfeatures:

Newpadlayout
ReceivedSignalStrengthIndication(RSSI)

HigherreversebiasvoltageforthePIN
diode
Internalvoltageregulator

Jitterperformanceslightly worsethanthe
firstversion:

Tofacilitateopticalfiber/PINdiode
alignment.

Tj =36psinsteadof30psinV1
ButBERperformancestillverygood!

GBTIAV2.1

Submittedforfabrication:November2013
Targetstheimprovementofthejitter
performance
Willbecomethebaselinesolutionif
successful:

http://cern.ch/projgbt

Noriskinvolved,versionV2.0isstillagood
baselinesolution
GBTProjectStatus

GBTXDataBandwidth

TheGBTXsupportsthreeframe
types:
GBTFrame
WideBusFrame
8B/10BFrame

Configuration
(eFuses+regBank)

I2CSlave

I2CMaster

CDR
SER

WideBusMode:
JTAG

Uplinkdatascrambled
NoFEC
Userbandwidth:4.48Gb/s
http://cern.ch/projgbt

SCR/ENC

ePLLTx

ControlLogic

E Port

Downlinkdata8B/10Bencoded
NoFEC
Userbandwidth:3.52Gb/s

E Port

8B/10BMode

DEC/DSCR

Thedownlinkalwaysusesthe
GBTframe.

CLKManager

WideBusand8B/10Bframes
areonlysupportedfortheuplink

Phase Aligners+Ser/DesforE Ports

E Port

Up/downlinks

CLKReference/xPLL

ePLLRx

GBTMode
Userbandwidth:3.28Gb/s

Phase Shifter
E Port

GBTX

GBTProjectStatus

GBTXStatus

GBTXsubmittedforfabricationonthe6th
ofAugust
Prototypes(baredie)available:
160ASICs(SinceDecember2012)
Possibletobuy240piecesin2013

TheGBTXinnumbers:
milliongates
Approximately:
3008bitprogramableregisters
(allTMR)
3008biteFusememory

Clocktree(chipwide):
9clocktrees(allTMR)
Frequencies:40/80/160/320MHz

7PLLs:

RX:CDRPLL+ReferencePLL(2.4GHz)
SerializerPLL(4.8GHz)
PhaseShifterPLL(1.28GHz)
xPLL(VCXObasedPLL,80MHz)
(2x)ePLL(320MHz)

17masterDLLs:
9forphasealignmentoftheelinks
8forclockdeskewing

40replicadelaylines:
Forphasealignmentoftheelinks

http://cern.ch/projgbt

GBTProjectStatus

GBTXPackageStatus

Package:

20 20ballarray
0.8mmpitch
Size:17mm 17mm
8layersubstrate
Heatslug
Onpackage:

ManufacturedanddesignedbyASE:

DesignverifiedansimulatedbyCERN:

Interconnectivity
ACperformance
Electromigration

Informationflow:

QuartzCrystal
Decouplingcapacitors

CERNIMECASE
Longfeedbackcycle:1to4weeks!
Fiveiterationswererequiredtoagreeon
thedesign!

Status:

Packagedesigncomplete.
Abouttostart:

Someexportlicenseproblemsstilltobe
sortedout:

Toolingdevelopment
Substratemanufacturing

Capacitors!!!

Forecast(conservative!?):

http://cern.ch/projgbt

Prototypesavailablefortesting:May2013
GBTProjectStatus

GBTXTestingStatus

TheCredenceSapphireASIC
tester:
Characterization
Production
Threeauxiliaryboardsare
needed:
Loadboard:
Ready

TheGBTXTestBoard(TB)
Schematicready:
PCBunderdevelopment:
15th March

TheGBTXLinkTesterBoard(LTB)
Ready

TheStandAloneTestboard(SAT):
Dedicatedto:
Fieldtests
SEUtests

Designunderdevelopment
Schematicunderdevelopment

http://cern.ch/projgbt

GBTProjectStatus

10

GBTSCAStatus

AnalogCircuitry
ADCblock
DesigndevelopmentoutsourcedtoanIPvendorbasedontheDCUADCarchitecture
PreliminarydesigndatabasedeliveredtoCERN,simulationresultsaccording
specifications.
FinaldesigndeliveryexpectedinearlyFebruary2013

Bandgap
Designready

DAC
BuildingblocksarereadyfromMEDIPIX3project.
Integrationworkisneeded

DigitalCircuitry
CoreLogic
RTLcodeextensivelyredesignedduringlastyear.Levelofcompleteness80%
NeedtotriplicateandsynthetizetheRTLcode.

DevelopmentofaTestbench basedonSystemVerilog

ePort(withHDLCtransmissionprotocol)
RTLcode80%ready(Minoreffortisneededtofinalizetriplication)
FunctionalitychecksareO.K.andcodeissynthesizable

ChipAssemblyandprototypesubmission
Place&Routeworkandphysicalverificationtobedone
Targettapeoutdate:MOSISMPWruninMay2013

http://cern.ch/projgbt

GBTProjectStatus

11

GBTBuildingBlocks(IP)Status
AvailableIPtofacilitatetheimplementationof
eLinktransceiversinthefrontendASICs:

SLVSReceiver

ePLLFM

Wirebond,DMmetalstack
C4,LMmetalstack

SLVSDriver

Wirebond,DMmetalstack
C4,LMmetalstack

SLVSBidirectional

C4,LMmetalstack

HDLCtransceiver

SynthesizableVerilog
7B/8BCODEC
SynthesizableVerilog

ePLL FM

ePLLCDR(underdevelopment)

http://cern.ch/projgbt

GBTProjectStatus

FrequencyMultiplier PLL
RadiationHard
130nmCMOStechnologywiththeDMmetalstack(3
23).
Inputfrequencies:40/80/160MHz
Outputfrequencies:160/320MHzregardlesstheinput
frequency
Programmablephaseoftheoutputclockswitha
resolutionof11.25 forthe160MHzclockand22.5
forthe320MHzclock
Programmablechargepumpcurrent,loopfilter
resistanceandcapacitancetooptimizetheloop
dynamics
Supplyvoltage:1.2V 1.5V
Nominalpowerconsumption:20mW@1.2V 30
mW@1.5V
Operatingtemperaturerange:30Cto100C
Datarate:40/80/160/320Mbit/s
Outputclocks:dataclock+40/80/160/320MHzwith
programmablephase
InternalorexternalcalibrationoftheVCOfrequency
PossibilitytouseitasafrequencymultiplierPLL
withoutapplyinginputdata
Programmablechargepumpcurrent,loopfilter
resistanceandcapacitancetooptimizetheloop
dynamics
Supplyvoltage:1.2V 1.5V
Operatingtemperaturerange:30Cto100C
Prototypefabrication:May2013
12

GBTFPGAStatus

GBTSERDESsuccessfullyimplementedinFPGAs:

Scrambler/Descrambler+Encoder/Decoder+
Serializer/CDR

Firmware:

KITsareavailablefordownloadfor:

Cyclone
Kintex7
ImplementationoftheGBTWideBusmode
ImplementationoftheICchannelprotocol

TheGBTisnowimplementedinitslatencyoptimized
versionontheGLIBSVN
Availablesoonfor:

StratixIVGx
Virtex6LXT

Optimizationstudies:

Optimizationofuseofresources
Lowanddeterministiclatency

StratixII,IV
Virtex4and5
Virtex6(withaprojectonML605evaluationcard)

Ongoingworkfor:

Xilinx 4.8Gb/s

Altera+optoTRx 4.8Gb/s

NotforALTERA

GBTFPGACommunity:

Usershaveaccesstothesharepointsite:

56registeredmembers(mostusersfromcollaborating
institutes)

https://espace.cern.ch/GBTProject/GBT
FPGA/default.aspx

LHCexperiments,butalsoCLIC,PANDA,GBT
Activeusersarenowpartofthedevelopment
team

ToregistertotheGBTFPGAcommunity:

emailtoSophie.Baron@cern.ch with

http://cern.ch/projgbt

Fullname
Project
Experiment

GBTProjectStatus

13

ExperimentsRequirements
LS1:20132014
LS2:2018
LS3:20222023
Experiment
ALICE

Upgrade
LS2

ATLAS

LS2
LS2
LS2
LS2
LS2
LS2

CMS

(prototyping)
2015(XMAS)
LS2

LHCb

LS2

ASICsneeded
2014

ASIC
GBTIA/GBTX/GBLD

Quantities
4,000

Systems
TPC/ITS/mTracker

Notes

GBTIA/GBTX/GBLD
GBTX/GBLD
GBTIA
GBTIA/GBTX/GBLD
GBTX/GBLD
GBTIA/GBTX/GBLD

288
1,280
640
150
6,000
100

TGCTrigger&Readout To beconfirmed
megas
megas
LArcalorimeter,Trigger
LArcalorimeter,Trigger Notconfirmed,backupsolutiononly!
Tracker

Yesterday!
2013
2014

GBTX/GBLD
GBTX/GBLD
GBTX/GBLD

120
1,500
4,200

ForwardHCAL
ForwardHCAL
HCALBarrelandEndcaps

2014

GBTIA
GBTX/GBLD
GBTSCA

3,000
14,000
3,000

AlmostAll

To beconfirmed

ThevertexdetectorwilllikelyuseaGBTtransmitterIP

GBTChipsetProduction:Q22014
Forecastincluding20%spares(basedontheabovenumbers):
10kGBTIA
28kGBLD(+10kdependingonATLASandALICE)
28kGBTX(+10kdependingonATLASandALICE)
5kGBTSCA
ProductioncostssupportedbyPHtoberecoveredlaterfromtheexperiments!
http://cern.ch/projgbt

GBTProjectStatus

14

GBTProjectFuture

LpGBT:LowpowerGBTchipset
ReducetheGBTchipsetpowerconsumptionto~
GBTX:~500mW

TwoASICs:
SimpleSERDESwithreducedfunctionality(LpGBT SerDes)
Lowpincountandfootprint(targetingtrackerdevelopments)
Simpleparallelport

FullGBTXfunctionality(LpGBTX)
Generalpurpose
ELinks

Highbandwidthcapability:
Downlink4.8Gb/s(asintheGBTX)
Uplinktwomodes:4.8and9.6Gb/s
ELinksdoublethebandwidthinthe10Gb/smode

Technology:65nmCMOS
LpGBT SerDes
LpGBTX
LpGBLD(2nd generation,10G)willbeverylikelykeptin130nmCMOS?

SeriousdevelopmentefforttostartQ12014
(TestingandproductionoftheGBTXisthepriorityfor2013)
Target:
LpGBT SerDesprototypesin2017
LpGBTXprototypesin2018

Developments:
LpGBLD(4.8Gb/s):MOSISMPW,19th February2013
http://cern.ch/projgbt

GBTProjectStatus

15