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elverton@dcc.ufmg.br
Omar P. Vilela Neto
Computer Science
Department (UFMG)
Belo Horizonte, Brazil
omar@dcc.ufmg.br
Osvaldo L. H. M.
Fonseca
Computer Science
Department (UFMG)
Belo Horizonte, Brazil
osvaldo.morais@dcc.ufmg.br
Antonio Otavio
Fernandes
Computer Science
Department (UFMG)
Belo Horizonte, Brazil
otavio@dcc.ufmg.br
jnacif@ufv.br
Douglas S. Silva
Computer Science
Department (UFMG)
Belo Horizonte, Brazil
douglas.sales@dcc.ufmg.br
ABSTRACT
Keywords
This paper describes the complete implementation of a robust SUBNEG (subtract and branch if negative) processor
using quantum-dot cellular automata (QCA) technology. A
processor is the basic unit in computer systems which is
responsable for performing the basic arithmetic, logic, and
input/output operations. QCA is a promising nanotechnology where components have nano size, ultra-low power
consumption and could have a clock rate on terahertz rate.
The architecture of our processor was inspired by the one
used on the first carbon nanotube computer. We used this
work as reference because both nanotechnology (the carbon
nanotube and QCA) are promising and able to overcome
the limits of current CMOS technology. Our work is the
first implementation of a SUBNEG processor in QCA technology and, moreover, satisfies all constraints in order to
make it robust. In a bottom-up approach, we first describe
the building blocks that compose the QCA SUBNEG processor such as the ALU and the data and instruction memories. Next, we present the processor architecture. Lastly,
we describe tests and performance evaluation of the QCA
SUBNEG processor.
General Terms
Design
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SBCCI 14 September 01 - 05 2014, Aracaju, Brazil
Copyright 2014 ACM 978-1-4503-3156-2/14/09$15.00
http://dx.doi.org/10.1145/2660540.2660997.
1.
INTRODUCTION
2.
BACKGROUND
P=-1
Binary 0
P=+1
Binary 1
2.1
QCA
(a)
Coulombic Interaction
(b)
Input
Output
3.
RELATED WORK
Few works presented the implementation of a QCA processor and almost all implemented an accumulator type architecture, as shown in [19] and [12]. The first one uses an
architecture that do not follow the constraints to make a
QCA circuit design robust, e.g., their circuit does not use
clock zones in the wires [7] and uses rotate cells for crossing [15]. The other, despite more robust, does not have an
instruction memory and a program counter, i.e., this processor does not implement the branching feature, which essentially differentiates a computer from a calculator.
Our QCA processor implements the SUBNEG architecture, which is similar to the first carbon nanotube processor [16, 10]. Once QCA technology is still new, a simple
architecture processor implementation using a robust design
is an important step in order to show the feasibility of the
technology. Our work can also be used as a model in the
next steps of QCA technology.
The SUBNEG architecture in spite of being simple, is a
Turing complete architecture. The SUBNEG works only
with one instruction which performs two operations: a subtraction of two operands and a branching step when the
result of the operation is negative. The instruction is also
simple, once we have the address of the two operands and
part of the next instructions address. Simplicity is the reason because this architecture is a good starting point for new
technologies.
4.
PROCESSOR ORGANIZATION
WireSync
WireSync
WireSync_IM
WireSync_ALU
WireSync_out
WireSync
WireSync_out_IM
WireSync_out_ALU
4.1
Instruction Memory
4.3
register. The correct value from the instruction is followed
by a parallel P=+1 in the WireSync out from IM. When
i[0] reaches the special register for next instruction address,
the P=+1 reaches it either and the write in the register is
performed.
The arithmetic logic unit (ALU) is the simplest component of the SUBNEG processor because it makes only two
operations. The first operation, a subtraction, consists in
a XOR and the negative test can be performed by the single logic equation A.B[16, 10]. The ALU unit works asynchronously which implies that the WireSync has no use here
unless to follow the right ALU result. The ALU logic design
is shown in figure 9.
A
4.2
Data Memory
AB
AB'
WireSync
WireSync_out_DM
WireSync_out_IM
4.4
Integrated Processor
Select Instruction
Save Addr Bit
Select Registers A and B
Save Register B
Write Value to Register
Process Registers A and B
11
7
8
4
12
3
5.
SIMULATION RESULTS
In this section, we present a test for the SUBNEG processor. It is important to note that several tests had been
executed. However, due to space limitation we present only
one example. We implemented the proposed processor in
QCADesigner simulator applying the coherence vector engine [18] at temperature of 1K.
The instructions are showed in table 2. First, we initialize
the DM addresses 01,10, and 11 with 1 and the 00
with 0. Then, we setup the first instruction address to 10.
The instruction in this address, according to table 2, sets
00
10001
01
01010
10
01111
11
11111
Instruction addr 00
Part of
instruction
addr 11
max: 9.88e-01
ALU B
min: -9.88e-01
Read in the
input of ALU
max: 9.88e-01
ALU A
min: -9.88e-01
max: 9.88e-01
Subtraction
min: -9.88e-01
Read in the
output of ALU
max: 9.88e-01
Branching
min: -9.88e-01
max: 9.88e-01
Writeback_addr[0]
min: -9.88e-01
Read right
after the
written
max: 9.88e-01
Writeback_addr[1]
min: -9.88e-01
max: 9.88e-01
Instruction_addr[0]
min: -9.88e-01
Read in
4th cycle
inside I.M.
max: 9.88e-01
Instruction_addr[1]
min: -9.88e-01
max: 9.88e-01
Wiresync
min: -9.88e-01
Read in the
output of ALU
max: 9.88e-01
Reg[0]
min: -9.88e-01
max: 9.88e-01
Reg[1]
min: -9.88e-01
Read right
after the
written
max: 9.88e-01
Reg[2]
min: -9.88e-01
max: 9.88e-01
Reg[3]
min: -9.88e-01
Setup time
6.
CONCLUSIONS
In this work we proposed and implemented a 1-bit SUBNEG processor using QCA technology. It is also important to note that the proposed processor is scalable and
Data Memory
Register
Writeback Address
ALU
Initializers
WireSync
Instruction Adress[1]
Instruction Memory
7.
ACKNOWLEDGMENTS
8.
ADDITIONAL AUTHORS
9.
REFERENCES