Chapter 8

8-bit Microcontroller: i51 System

i51 is a very popular Intel 8-bit microcontroller architecture. Based on this
architecture different manufacturers designed their single chip MCU with different
features. The AT89C51 is one of them by Atmel. Its main features are 4K Bytes of Flash Memory
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
128 Byte Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Full Duplex UART Serial Channel
Pin-Configuration:
VCC: Supply voltage.
GND: Ground.
RST: Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.
ALE/PROG: Address Latch Enable (ALE) is an output pulse for latching the low
byte of the address during accesses to external memory. This pin is also the
program pulse input (PROG) during Flash programming.
Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. It can also be
configured to be the multiplexed low-order address/data bus during accesses to
external program and data memory. In this mode, P0 has internal pull-ups.
Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups.
Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. It also gives
the high-order address bits for external memory addressing.

MMI (i51) - Ehsan ur Rahman

Page 1

Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. All the P3
pins have alternate functions as shown in the following table-

Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

PSEN: Program Store Enable (PSEN) is the read strobe to external program
memory. While executing code from external program memory, PSEN is
activated twice each machine cycle.

MMI (i51) - Ehsan ur Rahman

Page 2

EA/VPP: External Access Enable. EA must be strapped to GND in order to

enable the device to fetch code from external program memory locations starting
at 0000H up to FFFFH. EA should be strapped to VCC for internal program
executions.
XTAL1: Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.
XTAL2: Output from the inverting oscillator amplifier.

Minimum System Connection:

AT89C51 MPU needs the following minimum connections for operation.

Address Map:
For memory 89C51 can use both internal or/and external memory. Internally it
can address 4KB program memory (ROM) and 128B (in some variant 256B) data

MMI (i51) - Ehsan ur Rahman

Page 3

memory (RAM) space. However it can address 64KB of memory (ROM or/and
RAM) using the external address and data buses like the 8085 does.
Program Memory: The memory space, where the program (instructions with
required constants) are stored. It is in general the ROM. For 8051, internal 4KB
can be used with external 60KB memory or only 64KB external memory should
be used.

Data Memory: The memory space, where the variable data (required for the
program) are stored or to be stored. It is in general the RAM. 8051 data memory
consists of internal 128B RAM and external 64KB Memory. Internal 256B
address spaces are allocated to the registers, bit-addressable block and RAM.

MMI (i51) - Ehsan ur Rahman

Page 4

SFR:
Type
Reg
System

Data
Control
Power
Reg. Array

Parallel
Port

UART
Timer
Config.
T/C 0
T/C 1
Interrupt

Register
A (ACC)
B
PC
SP
PSW
DPL
DPH
PCON
R0-R7
R8-R15
R16-R23
R24-R31
P0
P1
P2
P3
SCON
SBUF
TMOD
TCON
TH0-TL0
TH1-TL1
IP
IE

Length
8
8
16
8
8
8
8
8
8x8
8x8
8x8
8x8
8
8
8
8
8
8
8
8
16
16
8
8

Address
E0
F0
81
D0
82
83
87
00-07
08-0F
10-17
18-1F
80
90
A0
B0
98
99
89
88
8C-8A
8D-8B
B8
A8

Ini-value
00
00
0000
07
00
00
00
00
00
00
00
00
FF
FF
FF
FF
00
00
00
00
00
00
00
00

Bit-addressable.

MMI (i51) - Ehsan ur Rahman

Page 5

8051 Programming
Data Type:
Decimal:
Hex:
Binary:
ASCII Number:
ASCII Character:

MMI (i51) - Ehsan ur Rahman

28
28H
00011100B
28
Twenty Eight

Page 6

Instruction Set:
8051 instructions are divided into 5 typesArithmetic
ADD
ADD
ADD
ADD

Logical

A,Rn
A,addr8
A,@Ri
A,#data8

ANL A,Rn
ANL A,addr8
ANL A,@Ri
ANL A,#data8
ANL addr8,A
ADDC A,Rn
ANL addr8,#data8
ADDC A,addr8 ORL A,Rn
ADDC A,@Ri
ORL A,addr8
ADDC A,#data8 ORL A,@Ri
ORL A,#data8
SUBB A,Rn
SUBB A,addr8 ORL addr8,A
ORL addr8,#data8
SUBB A,@Ri
SUBB A,#data8 XRL A,Rn
XRL A,addr8
INC A
XRL A,@Ri
INC Rn
XRL A,#data8
INC addr8
XRL addr8,A
INC @Ri
XRL addr8,#data8
INC DPTR
CLR A
DEC A
CPL A
DEC Rn
RL A
DEC addr8
RLC A
DEC @Ri
RR A
MUL AB
RRC A
DIV AB
SWAP A
DA A

Boolean
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
JC rel8
JNC rel8
JB bit,rel8
JNB bit,rel8
JBC bit,rel8

Data Transfer

Branching

MOV A,Rn
ACALL addr11
MOV A,addr8
LCALL addr16
MOV A,@Ri
RET
MOV A,#data8
RETI
MOV Rn,A
MOV Rn,addr8
AJMP addr11
MOV Rn,#data8
LJMP addr16
MOV addr8,A
SJMP rel8
MOV addr8,Rn
JMP @A+DPTR
MOV addr8,addr8
JZ rel8
MOV addr8,@Ri
JNZ rel8
MOV addr8,#data8
MOV @Ri,A
CJNE A,addr8,rel8
MOV @Ri,addr8
CJNE A,#data8,rel8
MOV @Ri,#data8
CJNE Rn,#data8,rel8
MOV DPTR,#data16
CJNE @Ri,#data8,rel8
MOVC A,@A+DPTR
MOVC A,@A+PC
DJNZ Rn,rel8
MOVX A,@Ri
DJNZ addr8,rel8
MOVX A,@DPTR
NOP
MOVX @Ri,A
MOVX @DPTR,A
PUSH addr8
POP addr8
XCH A,Rn
XCH A,addr8
XCH A,@Ri
XCHD A,@Ri

Rn = R0 - R7,
@Ri = @R0 or @R1,
rel8 = -128 - +127,
bit = 0 - 255

Addressing:
The 8051 offers the following addressing modes:

MMI (i51) - Ehsan ur Rahman

Page 7

Immediate Addressing:
MOV A,#data8
addr8,#data8

MOV Rn,#data8

MOV DPTR,#data16

MOV

MOV A,#5 ; load the ACC with the value 5, # stands for value
Register Addressing:
It specifies one of the 8 available registers R0 through R7 as the source. An
example of register addressing is:
MOV A, Rn

MOV Rn, A

MOV A, R3 ; load the ACC with the contents of R3

Direct Addressing:
In direct addressing, the operand is specified by an 8-bit address field (RAM
Address) in the instruction. An example of direct addressing is:
MOV A,addr8
MOV addr8,A
MOV addr8,addr8

MOV Rn,addr8
MOV addr8,Rn

MOV A,3 ; move contents of RAM[3] to the ACC

MOV 0,2 ; Same as MOV R0, R2, which is not possible as register addressing
mode.
Indirect Addressing:
In indirect addressing, the instruction specifies a register (R0 or R1) which
contains the address of the source or destination. An example of indirect
addressing is:
MOV A,@Ri
MOV @Ri,A

MOV A,@R0

MOV addr8,@Ri
MOV @Ri,addr8

MOV @Ri,#data8

; Content of A= Content of the memory addressed by R0

MMI (i51) - Ehsan ur Rahman

Page 8

R0 and R1 registers are used for internal 256B RAM.

DPTR (16bit data pointer register) can be used to point to any program memory
address.

Branching:
8051 has 3 different types of branching1. Relative or Short
2. Long
3. Absolute
1. Relative or Short branching: All conditional jumps are relative
branching to +127 or -127 from the next instruction address of the jump
instruction
2. Long branching: It can branch anywhere within the 16-bit address
space (64KB) by the LJMP and LCALL instruction
3. Absolute branching: It can branch anywhere within the 11-bit address
space (2KB) by the ACALL instruction

Interrupts
The 8051 can respond to three different interrupts which are:

an overflow in the internal timer #0 or timer #1

an electrical pulse applied to the 8051's "external interrupt #0" pin,
interrupt #1" pin
receipt or transmission of a byte via the serial port

Interrupt Vector:
Interrupt
Reset
interrupt #0
timer #0 overflow
interrupt #1
timer #1 overflow
serial port

MMI (i51) - Ehsan ur Rahman

Address
0000
0003
000B
0013
001B
0023

Priority
0
1
2
3
4
5

Page 9

Interrupt control register:

Interrupt
Enable
Register
(IE)

D7
EA
Global
IE

D6
-

Interrupt
Priority
Register
(IP)

D5
-

D4
D3
D2
D1
ES
ET1
EX1
ET0
Serial
Timer- Ext Int- TimerInt
1
1
0
1= Enable, 0=Disable
ES
ET1
EX1
ET0
Serial
Timer- Ext Int- TimerInt
1
1
0
1= Increase priority, 0= Default priority

D0
EX0
Ext
Int-0
PX0
Ext
Int-0

External Interrupt Signal:

Level (Default)
Edge (using TCON)

Steps to use interrupt:

1.
2.
3.
4.

Set he Global Interrupt Enable bit (EA=1) of IE register

Set the preferred interrupt enable bit of IE
Configure TCON for the external interrupt signal.
Write the ISR at the vector location or other redirected location.

MMI (i51) - Ehsan ur Rahman

Page 10