Digital Systems Design

TimeQuest Timing Analyzer

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-1

TimeQuest Timing Analyzer

ASIC-style timing analysis tool that validates the
timing performance of all logic in your design
Use the TimeQuest analyzer GUI or command-line
interface to constrain, analyze, and report results for
all timing paths in your design

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-2

Recommended Design Flow

Create Quartus II Project and Specify Design Files

Perform Analysis & Synthesis
Specify Timing Requirements
Compile Design and Verify Timing

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-3

Specifying Timing Requirements

Before running timing analysis with the TimeQuest
analyzer, you must specify
Timing constraints
Describe the clock frequency requirements and other
characteristics
Timing exceptions, and
I/O timing requirements of your design

You can use the TimeQuest Timing Analyzer

Wizard to enter initial constraints for your design,
and then refine timing constraints with the
TimeQuest analyzer GUI.
Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-4

Specifying Timing Requirements

Both the TimeQuest analyzer and the Fitter use constraints
contained in a Synopsis Design Constraints (.sdc) file
The constraints in the SDC file are read in sequence
You must first make a constraint before making any references to that
constraint
For example, if a generated clock references a base clock, the base
clock constraint must be made before the generated clock constraint

You can use template files included with the Quartus II

software and the interactive dialog boxes to create your
initial SDC file
If you are familiar with timing analysis, you can also create
an SDC file in you preferred text editor
Include the SDC file in the project when you are finished
Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-5

Timing Constraints
Timing analysis in the Quartus II software with the
TimeQuest Timing Analyzer relies on constraining
your design to make it meet your timing
requirements
When discussing these constraints, they can be referred
to as timing constraints, SDC constraints, or SDC
commands interchangeably

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-6

Recommended Starting SDC

Constraints
Almost every beginning SDC file should contain the following
four commands (at most):
create_clock
derive_pll_clocks
derive_clock_uncertainty

SDC Constraint Creation Summary

For a sample design with two clocks coming into it, your
SDC file might look like this example:
create_clock -period 20.00 -name adc_clk [get_ports adc_clk]
create_clock -period 8.00 -name sys_clk [get_ports sys_clk]
derive_pll_clocks
derive_clock_uncertainty

set_clock_groups

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-7

create_clock
The first statements in a SDC file should be
constraints for clocks, for example, constrain the
external clocks coming into the FPGA with
create_clock
An example of the basic syntax is:
create_clock -name sys_clk -period 8.0 [get_ports fpga_clk]

This command creates a clock called sys_clk with

an 8ns period and applies it to the port called
fpga_clk
By default, the clock has a rising edge at time 0ns, and a
50% duty cycle, hence a falling edge at time 4ns
Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-8

derive_pll_clocks
After the create_clock commands add the following
command into your SDC file:
derive_pll_clocks
This command automatically creates a generated
clock constraint on each output of the PLLs (Phase
Locked Loop) in your design.
When PLLs are created, you define how each PLL
output is configured
Because of this, the TimeQuest analyzer can
automatically constrain them, with the derive_pll_clocks
command
Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-9

derive_clock_uncertainty
Add the following command to your SDC file:
derive_clock_uncertainty
This command calculates clock-to-clock
uncertainties within the FPGA, due to
characteristics like PLL jitter, clock tree jitter, etc.
This should be in all SDC files
The TimeQuest analyzer generates a warning if this
command is not found in your SDC files

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-10

Creating I/O Requirements

The TimeQuest analyzer reviews setup and hold
relationships for designs in which an external
source interacts with a register internal to the
design
The TimeQuest analyzer supports input and output
external delay modeling with the set_input_delay
and set_output_delay commands
You can specify the clock and minimum and
maximum arrival times relative to the clock.

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-11

Input and Output Constraints

Input Constraints
Input constraints allow you to specify all the external
delays feeding into the device
Specify input requirements for all input ports in your
design

Output Constraints
Output constraints allow you to specify all external delays
from the device for all output ports in your design

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-12

Input Constraints

The calculation the TimeQuest analyzer performs to

determine the typical input delay
input delayMAX=(cd_extMAXcd_altrMIN)+tco_extMAX+ddMAX
input delayMIN=(cd_extMINcd_altrMAX)+tco_extMIN+ddMIN

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-13

Output Constraints

The calculation the TimeQuest analyzer performs to

determine the typical out delay
output delayMAX=ddMAX+tsu_ext+(cd_altrMAXcd_extMIN)
output delayMIN=(ddMINth_ext+(cd_altrMINcd_extMAX))

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-14

Using the TimeQuest Timing Analyzer

1.

Start the analyzer from

2.

Tools->TimeQuest Timing Analyzer

Create a timing netlist

Netlist->Create Timing Netlist

3.

Choose Post-fit, slow-corner model

Create clock(s) constraints

Constraints->Create Clock

Specify clock name, period, and associated port

Update Timing Netlist

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-15

Using the TimeQuest Timing Analyzer

4.

Create I/O constraints

Constraints->Set Input Delay

Constraints->Set Output Delay

5.

Specify max/min output constraints relative to clock for

all output ports

Write SDC file to save results

6.

Specify max/min input constraints relative to clock for all

input ports

Constraints->Write SDC File

Recompile design to verify TimeQuest Timing Analyzer results

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 5-16