A linear CMOS power amplier (PA) is developed for wideband codedivision multiple-access (W-CDMA) application using 0.

18 m
silicon-on-insulator (SOI) technology. By adopting a quadruplestacked FET structure, 1W of output power is achieved at 4V supply
voltage. A negative capacitance circuit is employed to maximise the
efciency of the PA by cancelling out the excessive capacitance at
the source terminal of the common-gate stage. Besides, a lineariser
based on the variable capacitor circuit is added to reduce the inherent
AM-PM distortion of the CMOS FET. Using W-CDMA modulation at
837MHz, the fabricated PA module delivers a PAE of 47.5% and an
adjacent channel leakage ratio of 36dBc at the output power of
27.1dBm.

Introduction: CMOS technology is promising for single-chip radio

integration for cellular mobile terminals. The power amplier is one
key building block that makes full transceiver system integration very
difcult. Besides the isolation issues, CMOS transistors suffer from
low breakdown voltage and poor linearity owing to relatively large
knee voltages [1].
Among various ways, a stacked FET conguration is an attractive
option for power combining of low-breakdown voltage devices, where
the voltage swing from each FET is added in phase to achieve high
output power [1]. By terminating the gates of common-gate (CG)
FETs with proper capacitance, the voltage swing can be maintained
below the breakdown voltage limits. Even if the breakdown issues are
successfully addressed, the poor device linearity remains as an obstacle
for 3G/4G linear power applications [2].
In this Letter, a highly efcient watt-level linear CMOS PA is developed using an integrated lineariser in a stacked-FET conguration. A
negative capacitance circuit is employed to cancel out the excessive
gate capacitance, and a lineariser based on a variable capacitor is
added to compensate for large AM-PM distortion of the CMOS FET.
The fabricated CMOS PA module shows a PAE of 47.5% with an adjacent channel leakage ratio (ACLR) of 36dBc using the W-CDMA
signal.

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10

16

Circuit design: The stacked FET PA is composed of one commonsource (CS) FET and multiple CG FETs connected in series, as
shown in Fig. 1. Small shunt capacitors (C2, C3, C4) are attached to
each gate terminal of the CG-FETs instead of large bypass capacitors
for RF-grounding. In this way, the voltage swing is divided between
the shunt capacitors and the gate-to-source capacitance (Cgs) of the
CG-FETs, which helps to overcome the low breakdown limits of
CMOS transistors [1, 3].

C4
C3
C2

IN

M4

CM4

M3

CM3

M2

CM2

M1

M4

Miller capacitor for

negative capacitance

equivalent circuit for

3 Miller capacitors

CTD_4=(1-1/Av_M4)CM4
CTS_4=(1-Av_M4)CM4

Cgs4
M3

CTD_3=(1-1/Av_M3)CM3
CTS_3=(1-Av_M3)CM3

Cgs3

M2

CTD_2=(1-1/Av_M2)CM2
CTS_2=(1-Av_M2)CM2

Cgs2

to lineariser

negative capacitor

to M1 drain

22
24
26
output power, dBm

28

30

32

Pout = 23 dBm

capacitance

voltage waveform
of diode

Pout = 30 dBm

40
30
20
10
0
16

20
24
28
output power, dBm

32

OUT

a
to load matching

C2

20

lineariser
(variable
capacitor
circuit)

C3

18

Vdd

C4

w/o lineariser (constant C)

w/ lineariser (variable C)

20

effective capacitance, pF

M.-S. Jeon, J. Woo, U. Kim and Y. Kwon

FET in a 0.18 m silicon-on-insulator (SOI) CMOS technology. To

prevent the device breakdown up to an output power of 1W with 4V
supply voltage, a quadruple stacked-FET is selected for the power
stage and a triple stacked cell for the driver stage. The FET size used
for the power and driver stage is 20 mm and 2 mm, respectively.
Fig. 1b shows the simplied equivalent circuit of the stacked CG-FET
cells used for the power stage. To maximise the output power and PAE,
the voltage swing from each FET must add in phase. However, large Cgs
of the 20mm FET ( 23 pF) virtually prevents in-phase voltage stacking. This problem has been avoided by cancelling out Cgs with negative
capacitance generated by the Miller capacitors (CM2, CM3, CM4 in
Fig. 1a) [4]. From Miller theorem, three Miller capacitors connected
between the source and drain of the CG-FETs can be transformed into
six shunt capacitors at the source and drain terminals. The transformed
capacitances at the source and drain can be expressed as a function of
voltage gain Av, and the Miller capacitor value CM, as shown in
Fig. 1b. Since the CG-FET has a positive voltage gain greater than 1,
the transformed capacitances (CTSs) at the source terminal have negative values. After optimisation using the circuit simulators, 3pF, 6pF,
and 10pF are determined for CM2, CM3, and CM4, respectively.
The poor linearity of the CMOS transistor has been addressed using
an on-chip phase lineariser based on the variable capacitor circuit. As
shown in [2], the linearity of the CMOS FET is degraded by AM-PM
distortion caused by the nonlinear Cgs, which tends to decrease as the
output power increases under class-AB bias conditions. As shown in
the phase distortion analysis of the cascode FETs [5], the phase of S21
increases as Cgs decreases. As a result, the AM-PM curve shows a
strong positive slope with respect to the output power. This has been
conrmed with the measured data as shown in Fig. 2a. The phase of
S21 increases from 5 to 27 when the output power is increased from
16 to 30dBm. In this work, a variable capacitor circuit with a positive
slope is employed at the gate terminal of M2 to compensate for the
phase distortion coming from the stacked FETs.

AM-PM, deg

High-efficiency CMOS stacked-FET power

amplifier for W-CDMA applications using
SOI technology

Fig. 1 Overall circuit schematic of two-stage stacked CMOS PA (Fig. 1a)

and simplied equivalent circuit of CG-FETs used in power stage (Fig. 1b)

Fig. 1a shows the overall circuit schematic of the two-stage CMOS

PA. The CMOS FET used in the PA design is a 0.32 m standard I/O

Fig. 2 Measured AM-PM characteristics (Fig. 2a), voltage waveform across

the diode and instantaneous capacitance (Fig. 2b) and calculated effective
capacitance of lineariser (Fig. 2c)

The lineariser circuit consists of a xed capacitor (74 pF) terminated

with a parallel combination of a diode and a resistor (680 ) as shown in
Fig. 1a. Under small-signal conditions, the diode is turned-off and the
capacitance of the lineariser is negligible. As the voltage swing at the
M2 gate goes over the turn-on voltage of the diode, the diode turns
on and the capacitance of the lineariser jumps up to 74 pF (see
Fig. 2b). As the power grows further, the on time of the diode
expands, which gradually increases the effective capacitance of the lineariser circuit. As shown in Fig. 2c, simulated effective capacitance
increases from 10 to 31pF when the output power increases from 16
to 30dBm. This capacitance expansion compensates for the phase distortion caused by the Cgs decrease in the FETs of the power stage. To show
the effectiveness of the lineariser, PA chips with and without the lineariser have been fabricated. Measured AM-PM characteristics are compared in Fig. 2a. Phase distortion is reduced from 27 to 7 with the
employment of the lineariser.

ELECTRONICS LETTERS 11th April 2013 Vol. 49 No. 8

Experimental results: The effect of the lineariser is veried by comparing the ACLR of the PA modules with and without the lineariser.
W-CDMA modulated signals are used for this test. Fig. 3a compares
the measured PAE and ACLR under high-current bias (Icq = 76mA).
In the case of a reference PA (without a lineariser), ACLR degrades
to 36dBc at a power level of 25.4dBm. It reaches the 3GPP system
specication limit of 33dBc at 26.2dBm. By applying the lineariser,
the ACLR is improved across the entire power range, showing ACLRs
better than 36dBc up to 26.8dBm. The lineariser effectively increases
the linear output power by 1.4dB and PAE by 6.5%.

10

w/o lineariser
w/ lineariser

15

35

20
25

30
33dBc
20 36dBc

40

30
35

ACLR, dBc

30

33dBc
20 36dBc

PAE, %

25
30

M.-S. Jeon, J. Woo, U. Kim and Y. Kwon (Institute of New Media and
Communications, School of Electrical Engineering and Computer
Science, Seoul National University, Seoul 151-742, Republic of Korea)

40
10

10
0
15

The Institution of Engineering and Technology 2013

15 October 2012
doi: 10.1049/el.2012.3627
One or more of the Figures in this Letter are available in colour online.

15
40

20

45
20
25
output power, dBm

50
30

45
0
15

20
25
output power, dBm

Acknowledgments: This work was supported by the Acceleration

Research Program of the Ministry of Education, Science and
Technology of the Republic of Korea and the National Research
Foundation of Korea.

5
10

50

40
PAE, %

60

w/o lineariser
w/ lineariser

50

ACLR, dBc

60

circuit is also employed to cancel out the excessive gate capacitance.

The fabricated PA module shows a PAE of 47.5% and an ACLR of
36dBc at the output power of 27.1dBm using the W-CDMA signal.
To our knowledge, this is among the best performances ever reported
using the CMOS technology. It clearly shows the potential of the
CMOS PA for 3G and 4G mobile terminal applications.

50
30

E-mail: ykwon@snu.ac.kr

Fig. 3 Measured PAE and ACLR against output power at 837 MHz using
WCDMA modulated signal. VDD is set at 4V
a High-current bias (Icq = 76mA)
b Low-current bias (Icq = 65mA)

Fig. 3b shows the measured results under low-current bias. By reducing the quiescent current to 65mA, PAE improves while the ACLR
degrades. For example, the PA without the lineariser starts to show
poor ACLR ( > 36dBc) from 16dBm. However, the PA with a lineariser shows ACLR better than 36dBc up to 27.1dBm, where PAE
reaches 47.5%. When the PA is driven to a higher power level of
27.6dBm, where the ACLR reaches 33dBc, PAE further improves
to 49.5%.
Conclusion: A linear CMOS PA has been demonstrated using a capacitive lineariser in a stacked FET conguration. The negative capacitance

References
1 Pornpromlikit, S., Jeong, J., Presti, C., Scuderi, A., and Asbeck, P.: A
watt-level stacked-FET linear power amplier in silicon-on-insulator
CMOS, IEEE Trans. Microw. Theory Tech., 2010, 58, pp. 5764
2 Wang, C., Vaidyanathan, M., and Larson, L.: A capacitancecompensation technique for improved linearity in CMOS class-AB
power ampliers, IEEE J. Solid-State Circuits, 2004, 39, pp. 19271937
3 Kim, Y., Koh, Y., Kim, J., Lee, S., Jeong, J., Seo, K., and Kwon, Y.: A
60GHz broadband stacked FET power amplier using 130-nm metamorphic HEMTs, IEEE Microw. Wirel. Compon. Lett., 2011, 21,
pp. 323325
4 Song, Y., Lee, S., Cho, E., Lee, J., and Nam, S.: A CMOS class-E power
amplier with voltage stress relief and enhanced efciency, IEEE Trans.
Microw. Theory Tech., 2010, 58, pp. 310317
5 Hayashi, H., Nakatsugawa, M., and Muraguchi, M.: Quasi-linear amplication using self phase distortion compensation technique, IEEE
Trans. Microw. Theory Tech., 1995, 43, pp. 25572563

ELECTRONICS LETTERS 11th April 2013 Vol. 49 No. 8

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