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Colour Television

Chassis

Q552.1A
LA

18990_000_100330.eps
100330

Contents

Page

Revision List
2
Technical Specifications, Diversity, and Connections2
Precautions, Notes, and Abbreviation List
5
Mechanical Instructions
9
Service Modes, Error Codes, and Fault Finding 12
Alignments
30
Circuit Descriptions
36
IC Data Sheets
48
Block Diagrams
Wiring diagram Matisse 42" - 46"
59
Block Diagram Video
60
Block Diagram Audio
61
Block Diagram Control & Clock Signals
62
Block Diagram I2C
63
Supply Lines Overview
64
10. Circuit Diagrams and PWB Layouts
Drawing
AL1 820400089786 AmbiLight Common
65
AL1 820400089691 9 LED LiteOn
67
AL1 820400089703 15 LED LiteOn
69
AL1 820400090592 AmbiLight Common
72
AL1 820400090601 9 LED Everlight
74
AL1 820400090621 15 LED Everlight
76
B01 820400089943 Tuner, HDMI & CI
79
B02 820400089506 PNX85500
90
B03 820400089514 CLASS D
99
B04 820400089524 Analog I/O
107
B05 820400089535 DDR
112
B06 820400089572 LVDS Non DVBS
113
B09 820400089812 Non DVBS Con.
117
11. Styling Sheets
Matisse 32" - 46"
120

Contents

Page

1.
2.
3.
4.
5.
6.
7.
8.
9.

PWB
71
71
71
78
78
78
118
118
118
118
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118

Copyright 2010 Koninklijke Philips Electronics N.V.


All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.

Published by ER/TY 1063 BU TV Consumer Care, the Netherlands

Subject to modification

EN 3122 785 18990


2010-Apr-02

EN 2

1.

Revision List

Q552.1A LA

1. Revision List
Manual xxxx xxx xxxx.0
First release.

2. Technical Specifications, Diversity, and Connections


2.1

Index of this chapter:


2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections
2.4 Chassis Overview

Technical Specifications
For on-line product support please use the CTN links in Table
2-1. Here is product information available, as well as getting
started, user manuals, frequently asked questions and
software & drivers.

Notes:
Figures can deviate due to the different set executions.
Specifications are indicative (subject to change).
Table 2-1 Described Model Numbers and Diversity

2.2

B14 (TCON-SHP)

B13 (Ambilight)

B11 (TCON-LGD)

B09 (non-DVBS-conn.)

B08 (DVBS-Supp.)

B07 (DVBS-FE)

B06 (non-DVBS-LVDS)

B05 (DDR)

B04 (I/O)

B03 (DC/DC / Class D)

B02 (PNX85500)

B01 (Tuner)

Additional Everlight

Common Everlight

Additional LiteOn

10

Common LiteOn

Wng Schematics

Diagram

Descriptions

TCON

Assembly
Removal
LCD
Removal

Wire

Styling
styling sh.

3104 313

CTN

AmbiLight

Tuner

Conn Mechanics

PSU

SSB

42PFL8605D/93 Matisse
11-1

63643 2.3
10-16

4-1 4.3

t.b.d. 7.2 7.4.1 -

9-1

10-1 10-2 10-5 10-6 10-9 10- 10- 10- 10- 10-14 10 11 12 13

10-15 -

42PFL8605/98

Matisse
11-1

63643 2.3
10-16

4-1 4.3

t.b.d. 7.2 7.4.1 -

9-1

10-1 10-2 10-5 10-6 10-9 10- 10- 10- 10- 10-14 10 11 12 13

10-15 -

46PFL8605D/93 Matisse
11-1

63643 2.3
10-16

4-2 4.3

t.b.d. 7.2 7.4.1 -

9-1

10-1 10-3 10-5 10-7 10-9 10- 10- 10- 10- 10-14 10 11 12 13

10-15 -

Directions for Use


You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

2010-Apr-02

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Technical Specifications, Diversity, and Connections


2.3

Q552.1A LA

2.

EN 3

Connections

6
2

10

11

12

12

13

14

15

16
3

18990_001_100401.eps
100401

Figure 2-1 Connection overview


4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Note: The following connector colour abbreviations are used


(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow.
2.3.1

Side Connections
1 - Common Interface
68p - See diagram B01F HDMI & CI

jk

2 - USB2.0

10000_022_090121.eps
090121

Figure 2-2 USB (type A)


1
2
3
4

- +5V
- Data (-)
- Data (+)
- Ground

k
jk
jk
H

Gnd

2.3.2

- D1+
- Shield
- D1- D0+
- Shield
- D0- CLK+
- Shield
- CLK- Easylink/CEC
- n.c.
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground

Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Control channel

j
H
j
j
H
j
j
H
j
jk

DDC clock
DDC data
Gnd

j
jk
H
j
j
H

Hot Plug Detect


Gnd

Rear Connections
4 - RJ45: Ethernet (optional)
12345678

3 - HDMI: Digital Video, Digital Audio - In


19
18

1
2

10000_025_090121.eps
090121

10000_017_090121.eps
090428

Figure 2-4 Ethernet connector


Figure 2-3 HDMI (type A) connector
1
2
3

- D2+
- Shield
- D2-

Data channel
Gnd
Data channel

1
2
3
4

j
H
j
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- TD+
- TD- RD+
- CT

Transmit signal
Transmit signal
Receive signal
Centre Tap: DC level fixation

k
k
j

2010-Apr-02

EN 4
5
6
7
8

2.

Q552.1A LA

- CT
- RD- GND
- GND

Technical Specifications, Diversity, and Connections

Centre Tap: DC level fixation


Receive signal
Gnd
Gnd

5 - CVI 2: Cinch: Video YPbPr - In, Audio - In


Gn - Video Y
1 VPP / 75 ohm
Bu - Video Pb
0.7 VPP / 75 ohm
Rd - Video Pr
0.7 VPP / 75 ohm
Rd - Audio - R
0.5 VRMS / 10 kohm
Wh - Audio - L
0.5 VRMS / 10 kohm

jq
jq
jq
jq
jq

6 - Service Connector (UART)


1 - Ground
Gnd
2 - UART_TX
Transmit
3 - UART_RX
Receive
7 - Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS
1 VPP / 75 ohm
Wh - Audio L
0.5 VRMS / 10 kohm
Rd - Audio R
0.5 VRMS / 10 kohm

2.3.3

jq
jq
jq

H
H
j
j

10
15

Figure 2-6 VGA Connector


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

ot

kq

1
2

Figure 2-5 HDMI (type A) connector


Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel
Gnd
Data channel
Data channel

j
H
j
j
H
j
j
H
j
j

Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.

2010-Apr-02

10000_002_090121.eps
090127

10000_017_090121.eps
090428

2.4

jq
jq

13 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/


Out

- D2+
- Shield
- D2- D1+
- Shield
- D1- D0+
- Shield
- D0- CLK+

Coax, 75 ohm

11

12 - HDMI 2 (& 3 optional): Digital Video, Digital Audio - In


See 3 - HDMI: Digital Video, Digital Audio - In

1
2
3
4
5
6
7
8
9
10

Hot Plug Detect


Gnd

H
j
jk
k
j
jk
H
j
j
H

16 - VGA: Video RGB - In

10 - CVI 1: Video RGB - In, CVBS - In/Out, Audio - In/Out


See 5 - CVI 2: Cinch: Video YPbPr - In, Audio - In

19
18

Gnd
Data channel
Control channel
Audio Return Channel
DDC clock
DDC data
Gnd

15 - Aerial - In
- - IEC-type (EU)

Rear Connections - Bottom

11 - Cinch: S/PDIF - Out


Bk - Coaxial
0.4 - 0.6VPP / 75 ohm

- Shield
- CLK- Easylink/CEC
- ARC
- DDC_SCL
- DDC_SDA
- Ground
- +5V
- HPD
- Ground

14 - Cinch: Audio - In (VGA/DVI)


Rd - Audio R
0.5 VRMS / 10 kohm
Wh - Audio L
0.5 VRMS / 10 kohm

H
k
j

8 - S-Video (Hosiden): Video Y/C - In


1 - Ground Y
Gnd
2 - Ground C
Gnd
3 - Video Y
1 VPP / 75 ohm
4 - Video C
0.3 VPPP / 75 ohm
9 - Head phone (Output)
Bk - Head phone
32 - 600 ohm / 10 mW

11
12
13
14
15
16
17
18
19
20

j
H
H

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- Video Red
- Video Green
- Video Blue
- n.c.
- Ground
- Ground Red
- Ground Green
- Ground Blue
- +5VDC
- Ground Sync
- n.c.
- DDC_SDA
- H-sync
- V-sync
- DDC_SCL

0.7 VPP / 75 ohm


0.7 VPP / 75 ohm
0.7 VPP / 75 ohm

j
j
j

Gnd
Gnd
Gnd
Gnd
+5 V
Gnd

H
H
H
H
j
H

DDC data
0-5V
0-5V
DDC clock

j
j
j
j

Precautions, Notes, and Abbreviation List

Q552.1A LA

3.

EN 5

3. Precautions, Notes, and Abbreviation List


Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List

3.1

Safety Instructions
3.3.2

Safety regulations require the following during a repair:


Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard. Of de set
ontploft!

3.2

3.3.3

3.3.4

Notes

3.3.1

General

Spare Parts

BGA (Ball Grid Array) ICs


Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
Magazine, then go to Repair downloads. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.

3.3.5

Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
To reach a solder-tip temperature of at least 400C.
To stabilize the adjusted temperature at the solder-tip.
To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature of around
360C - 380C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch off unused equipment or
reduce heat.
Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.

All ICs and many other semiconductors are susceptible to


electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched on.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.

3.3

All resistor values are in ohms, and the value multiplier is


often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an E or an R (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads ( = 10-6),
nano-farads (n = 10-9), or pico-farads (p = 10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An asterisk (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.

For the latest spare part overview, consult your Philips Spare
Part web portal.

Warnings

Schematic Notes

Safety regulations require that after a repair, the set must be


returned in its original condition. Pay in particular attention to
the following points:
Route the wire trees correctly and fix them with the
mounted cable clamps.
Check the insulation of the Mains/AC Power lead for
external damage.
Check the strain relief of the Mains/AC Power cord for
proper function.
Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the on position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch off the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any
inner parts by the customer.

picture carrier at 475.25 MHz for PAL, or 61.25 MHz for


NTSC (channel 3).
Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.

Measure the voltages and waveforms with regard to the


chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and

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2010-Apr-02

EN 6
3.3.6

3.

Q552.1A LA

Precautions, Notes, and Abbreviation List


3.4

Alternative BOM identification


It should be noted that on the European Service website,
Alternative BOM is referred to as Design variant.

0/6/12

The third digit in the serial number (example:


AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
result in sets which have the same CTN (Commercial Type
Number; e.g. 28PW9515/12) but which have a different B.O.M.
number.
By looking at the third digit of the serial number, one can
identify which B.O.M. is used for the TV set he is working with.
If the third digit of the serial number contains the number 1
(example: AG1B033500001), then the TV set has been
manufactured according to B.O.M. number 1. If the third digit is
a 2 (example: AG2B0335000001), then the set has been
produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
indicated by the third digit of the serial number.

AARA

ACI

ADC
AFC

AGC

AM
AP
AR
ASF

Identification: The bottom line of a type plate gives a 14-digit


serial number. Digits 1 and 2 refer to the production centre (e.g.
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers
to the Service version change code, digits 5 and 6 refer to the
production year, and digits 7 and 8 refer to production week (in
example below it is 2006 week 17). The 6 last digits contain the
serial number.
MODEL

: 32PF9968/10

PROD.NO: AG 1A0617 000001

ATSC

ATV
Auto TV

MADE IN BELGIUM
220-240V ~ 50/60Hz
128W
VHF+S+H+UHF

AV
AVC
AVIP
B/G

BJ3.0E LA

10000_024_090121.eps
100105

BDS
BLR
BTSC

Figure 3-1 Serial number (example)


3.3.7

Board Level Repair (BLR) or Component Level Repair


(CLR)
B-TXT
C
CEC

If a board is defective, consult your repair procedure to decide


if the board has to be exchanged or if it should be repaired on
component level.
If your repair procedure says the board should be exchanged
completely, do not solder on the defective board. Otherwise, it
cannot be returned to the O.E.M. supplier for back charging!
3.3.8

Abbreviation List

CL
CLR
ComPair
CP
CSM
CTI

Practical Service Precautions

It makes sense to avoid exposure to electrical shock.


While some sources are expected to have a possible
dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
reactions that are best avoided. Before reaching into a
powered TV set, it is best to test the high voltage insulation.
It is easy to do, and is a good service precaution.

CVBS
DAC
DBE
DCM

DDC
D/K
DFI
2010-Apr-02

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SCART switch control signal on A/V


board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
format
Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio
Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page
Analogue to Digital Converter
Automatic Frequency Control: control
signal used to tune to the correct
frequency
Automatic Gain Control: algorithm that
controls the video input of the feature
box
Amplitude Modulation
Asia Pacific
Aspect Ratio: 4 by 3 or 16 by 9
Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information
Advanced Television Systems
Committee, the digital TV standard in
the USA
See Auto TV
A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
External Audio Video
Audio Video Controller
Audio Video Input Processor
Monochrome TV system. Sound
carrier distance is 5.5 MHz
Business Display Solutions (iTV)
Board-Level Repair
Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
Blue TeleteXT
Centre channel (audio)
Consumer Electronics Control bus:
remote control bus on HDMI
connections
Constant Level: audio output to
connect with an external amplifier
Component Level Repair
Computer aided rePair
Connected Planet / Copy Protection
Customer Service Mode
Color Transient Improvement:
manipulates steepness of chroma
transients
Composite Video Blanking and
Synchronization
Digital to Analogue Converter
Dynamic Bass Enhancement: extra
low frequency amplification
Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
See E-DDC
Monochrome TV system. Sound
carrier distance is 6.5 MHz
Dynamic Frame Insertion

Precautions, Notes, and Abbreviation List


DFU
DMR
DMSD
DNM
DNR
DRAM
DRM
DSP
DST

DTCP

DVB-C
DVB-T
DVD
DVI(-d)
E-DDC

EDID
EEPROM
EMI
EPG
EPLD
EU
EXT
FDS
FDW
FLASH
FM
FPGA
FTV
Gb/s
G-TXT
H
HD
HDD
HDCP

HDMI
HP
I
I2 C
I2 D
I2 S
IF
IR
IRQ
ITU-656

Directions For Use: owner's manual


Digital Media Reader: card reader
Digital Multi Standard Decoding
Digital Natural Motion
Digital Noise Reduction: noise
reduction feature of the set
Dynamic RAM
Digital Rights Management
Digital Signal Processing
Dealer Service Tool: special remote
control designed for service
technicians
Digital Transmission Content
Protection; A protocol for protecting
digital audio/video content that is
traversing a high speed serial bus,
such as IEEE-1394
Digital Video Broadcast - Cable
Digital Video Broadcast - Terrestrial
Digital Versatile Disc
Digital Visual Interface (d= digital only)
Enhanced Display Data Channel
(VESA standard for communication
channel and display). Using E-DDC,
the video source can read the EDID
information form the display.
Extended Display Identification Data
(VESA standard)
Electrically Erasable and
Programmable Read Only Memory
Electro Magnetic Interference
Electronic Program Guide
Erasable Programmable Logic Device
Europe
EXTernal (source), entering the set by
SCART or by cinches (jacks)
Full Dual Screen (same as FDW)
Full Dual Window (same as FDS)
FLASH memory
Field Memory or Frequency
Modulation
Field-Programmable Gate Array
Flat TeleVision
Giga bits per second
Green TeleteXT
H_sync to the module
High Definition
Hard Disk Drive
High-bandwidth Digital Content
Protection: A key encoded into the
HDMI/DVI signal that prevents video
data piracy. If a source is HDCP coded
and connected via HDMI/DVI without
the proper HDCP decoding, the
picture is put into a snow vision mode
or changed to a low resolution. For
normal content distribution the source
and the display device must be
enabled for HDCP software key
decoding.
High Definition Multimedia Interface
HeadPhone
Monochrome TV system. Sound
carrier distance is 6.0 MHz
Inter IC bus
Inter IC Data bus
Inter IC Sound bus
Intermediate Frequency
Infra Red
Interrupt Request
The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.

ITV
LS

LATAM
LCD
LED
L/L'

LPL
LS
LVDS
Mbps
M/N
MHEG

MIPS

MOP
MOSFET
MPEG
MPIF
MUTE
MTV
NC
NICAM

NTC
NTSC

NVM
O/C
OSD
OAD

OTC
P50
PAL

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Q552.1A LA

3.

EN 7

SDI), is a digitized video format used


for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz.
Institutional TeleVision; TV sets for
hotels, hospitals etc.
Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences
Latin America
Liquid Crystal Display
Light Emitting Diode
Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I
LG.Philips LCD (supplier)
Loudspeaker
Low Voltage Differential Signalling
Mega bits per second
Monochrome TV system. Sound
carrier distance is 4.5 MHz
Part of a set of international standards
related to the presentation of
multimedia information, standardised
by the Multimedia and Hypermedia
Experts Group. It is commonly used as
a language to describe interactive
television services
Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor
Matrix Output Processor
Metal Oxide Silicon Field Effect
Transistor, switching device
Motion Pictures Experts Group
Multi Platform InterFace
MUTE Line
Mainstream TV: TV-mode with
Consumer TV features enabled (iTV)
Not Connected
Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe.
Negative Temperature Coefficient,
non-linear resistor
National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air)
Non-Volatile Memory: IC containing
TV related data such as alignments
Open Circuit
On Screen Display
Over the Air Download. Method of
software upgrade via RF transmission.
Upgrade software is broadcasted in
TS with TV channels.
On screen display Teletext and
Control; also called Artistic (SAA5800)
Project 50: communication protocol
between TV and peripherals
Phase Alternating Line. Color system
mainly used in West Europe (color
carrier= 4.433619 MHz) and South
America (color carrier PAL M=
2010-Apr-02

EN 8

3.

PCB
PCM
PDP
PFC
PIP
PLL

POD

POR
PSDL
PSL
PSLS

PTC
PWB
PWM
QRC
QTNR
QVCP
RAM
RGB

RC
RC5 / RC6
RESET
ROM
RSDS
R-TXT
SAM
S/C
SCART

SCL
SCL-F
SD
SDA
SDA-F
SDI
SDRAM
SECAM

SIF
SMPS
SoC
SOG
SOPS
SPI

S/PDIF
SRAM
SRP
SSB
SSC
STB
STBY
SVGA
2010-Apr-02

Q552.1A LA

Precautions, Notes, and Abbreviation List


SVHS
SW
SWAN

3.575612 MHz and PAL N= 3.582056


MHz)
Printed Circuit Board (same as PWB)
Pulse Code Modulation
Plasma Display Panel
Power Factor Corrector (or Preconditioner)
Picture In Picture
Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency
Point Of Deployment: a removable
CAM module, implementing the CA
system for a host (e.g. a TV-set)
Power On Reset, signal to reset the uP
Power Supply for Direct view LED
backlight with 2D-dimming
Power Supply with integrated LED
drivers
Power Supply with integrated LED
drivers with added Scanning
functionality
Positive Temperature Coefficient,
non-linear resistor
Printed Wiring Board (same as PCB)
Pulse Width Modulation
Quasi Resonant Converter
Quality Temporal Noise Reduction
Quality Video Composition Processor
Random Access Memory
Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced.
Remote Control
Signal protocol from the remote
control receiver
RESET signal
Read Only Memory
Reduced Swing Differential Signalling
data interface
Red TeleteXT
Service Alignment Mode
Short Circuit
Syndicat des Constructeurs
d'Appareils Radiorcepteurs et
Tlviseurs
Serial Clock I2C
CLock Signal on Fast I2C bus
Standard Definition
Serial Data I2C
DAta Signal on Fast I2C bus
Serial Digital Interface, see ITU-656
Synchronous DRAM
SEequence Couleur Avec Mmoire.
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
Sound Intermediate Frequency
Switched Mode Power Supply
System on Chip
Sync On Green
Self Oscillating Power Supply
Serial Peripheral Interface bus; a 4wire synchronous serial data link
standard
Sony Philips Digital InterFace
Static RAM
Service Reference Protocol
Small Signal Board
Spread Spectrum Clocking, used to
reduce the effects of EMI
Set Top Box
STand-BY
800 600 (4:3)

SXGA
TFT
THD
TMDS
TS
TXT
TXT-DW
UI
uP
UXGA
V
VESA
VGA
VL
VSB
WYSIWYR

WXGA
XTAL
XGA
Y
Y/C
YPbPr

YUV

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Super Video Home System


Software
Spatial temporal Weighted Averaging
Noise reduction
1280 1024
Thin Film Transistor
Total Harmonic Distortion
Transmission Minimized Differential
Signalling
Transport Stream
TeleteXT
Dual Window with TeleteXT
User Interface
Microprocessor
1600 1200 (4:3)
V-sync to the module
Video Electronics Standards
Association
640 480 (4:3)
Variable Level out: processed audio
output toward external amplifier
Vestigial Side Band; modulation
method
What You See Is What You Record:
record selection that follows main
picture and sound
1280 768 (15:9)
Quartz crystal
1024 768 (4:3)
Luminance signal
Luminance (Y) and Chrominance (C)
signal
Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
Component video

Mechanical Instructions

Q552.1A LA

4.

EN 9

4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing Matisse styling
4.2 Service Positions
4.3 Assy/Panel Removal Matisse Styling
4.4 Set Re-assembly

4.1
Notes:
Figures below can deviate slightly from the actual situation,
due to the different set executions.

Cable Dressing Matisse styling


Note: pictures are taken from the European equivalent (with
SCART connector).

18990_100_100401.eps
100401

Figure 4-1 Cable dressing 42" 8000-series

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div. table

2010-Apr-02

EN 10

4.

Q552.1A LA

Mechanical Instructions

18990_101_100401.eps
100401

Figure 4-2 Cable dressing 46" 8000-series

2010-Apr-02

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div. table

Mechanical Instructions
4.2

Q552.1A LA

4.

EN 11

Service Positions
For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can
seriously damage the display!
Ensure that ESD safe measures are taken.

4.3

Assy/Panel Removal Matisse Styling


No detailed information is available at time of publishing.

4.4

Set Re-assembly
To re-assemble the whole set, execute all processes in reverse
order.
Notes:
While re-assembling, make sure that all cables are placed
and connected in their original position.
Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

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div. table

2010-Apr-02

EN 12

5.

Q552.1A LA

Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter:


5.1 Test Points
5.2 Service Modes
5.3 Stepwise Start-up
5.4 Service Tools
5.5 Error Codes
5.6 The Blinking LED Procedure
5.7 Protections
5.8 Fault Finding and Repair Tips
5.9 Software Upgrading

5.1

How to Activate SDM


For this chassis there are two kinds of SDM: an analogue SDM
and a digital SDM. Tuning will happen according Table 5-1.
Analogue SDM: use the standard RC-transmitter and key
in the code 062596, directly followed by the MENU (or
HOME) button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it off, push the MENU(or
HOME) button again.
Digital SDM: use the standard RC-transmitter and key in
the code 062593, directly followed by the MENU (or
HOME) button.
Note: It is possible that, together with the SDM, the main
menu will appear. To switch it off, push the MENU (or
HOME) button again.
Analogue SDM can also be activated by grounding for a
moment the solder path on the SSB, with the indication
SDM (see figure Service mode pad).

Test Points
As most signals are digital, it will be difficult to measure
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.
Perform measurements under the following conditions:
Service Default Mode.
Video: Colour bar signal.
Audio: 3 kHz left, 1 kHz right.

5.2

All service-unfriendly modes (if present) are disabled, like:


(Sleep) timer.
Child/parental lock.
Picture mute (blue mute or black mute).
Automatic volume levelling (AVL).
Skip/blank of non-favourite pre-sets.

Service Modes
Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the Service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.
This chassis also offers the option of using ComPair, a
hardware interface between a computer and the TV chassis. It
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis.
(see also section 5.4.1 ComPair).
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old MENU
button is now called HOME (or is indicated by a house icon).

5.2.1

SDM

Service Default Mode (SDM)


Purpose
To create a pre-defined setting, to get the same
measurement results as given in this manual.
To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
section 5.3 Stepwise Start-up.
To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section 5.5 Error Codes).

18770_249_100215.eps
100215

Figure 5-1 Service mode pad

Specifications

After activating this mode, SDM will appear in the upper right
corner of the screen (when a picture is available).

Table 5-1 SDM default settings

Freq. (MHz)

Default
system

Europe, AP(PAL/Multi)

475.25

PAL B/G

Europe, AP DVB-T

DVB-T
546.00 PID
Video: 0B 06 PID
PCR: 0B 06 PID
Audio: 0B 07

Region

2010-Apr-02

How to Navigate
When the MENU (or HOME) button is pressed on the RC
transmitter, the TV set will toggle between the SDM and the
normal user menu.
How to Exit SDM
Use one of the following methods:
Switch the set to STAND-BY via the RC-transmitter.
Via a standard customer RC-transmitter: key in 00sequence.

All picture settings at 50% (brightness, colour, contrast).


Sound volume at 25%.
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Service Modes, Error Codes, and Fault Finding

5.

EN 13

button and XXX (where XXX is the 3 digit decimal display


code as mentioned in Table 6-7). Make sure to key in all three
digits, also the leading zeros. If the above action is successful,
the front LED will go out as an indication that the RC sequence
was correct. After the display option is changed in the NVM, the
TV will go to the Stand-by mode. If the NVM was corrupted or
empty before this action, it will be initialized first (loaded with
default values). This initializing can take up to 20 seconds.

Service Alignment Mode (SAM)


Purpose
To perform (software) alignments.
To change option settings.
To easily identify the used software version.
To view operation hours.
To display (or clear) the error code buffer.
How to Activate SAM
Via a standard RC transmitter: Key in the code 062596
directly followed by the INFO/HOME button. After activating
SAM with this method a service warning will appear on the
screen, continue by pressing the OK button on the RC.

Display Option
Code

39mm

Contents of SAM (see also Table 6-8)


Hardware Info.
A. SW Version. Displays the software version of the
main software (example: Q555X-1.2.3.4 =
AAAAB_X.Y.W.Z).
AAAA= the chassis name.
B= the SW branch version. This is a sequential
number (this is no longer the region indication, as
the software is now multi-region).
X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
B. STBY PROC Version. Displays the software
version of the stand-by processor.
C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. ComPair will foresee in a
possibility to do this.
Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched on/off, 0.5 hours is added to this number.
Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section 5.5 Error Codes).
Reset Error Buffer. When cursor right (or the OK
button) is pressed and then the OK button is pressed, the
error buffer is reset.
Alignments. This will activate the ALIGNMENTS submenu. See Chapter 6. Alignments.
Dealer Options. Extra features for the dealers.
Options. Extra features for Service. For more info
regarding option codes, 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the OK button before
the options are stored. Otherwise changes will be lost.
Initialize NVM. The moment the processor recognizes a
corrupted NVM, the initialize NVM line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
Initialize the NVM.

PHILIPS
27mm

5.2.2

Q552.1A LA

040

MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001

(CTN Sticker)

E_06532_038.eps
240108

Figure 5-2 Location of Display Option Code sticker

Store - go right. All options and alignments are stored


when pressing cursor right (or the OK button) and then
the OK-button.
SW Maintenance.
SW Events. Not useful for Service purposes. In case
of specific software problems, the development
department can ask for this info.
HW Events. Not useful for Service purposes. In case
of specific software problems, the development
department can ask for this info.
Test settings. For development purposes only.
Development file versions. Not useful for Service
purposes, this information is only used by the development
department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
Channel list, Personal settings, Option codes,
Display-related alignments, Identification data and
History list. First a directory repair\ has to be created
in the root of the USB stick. To upload the settings select
each item separately, press cursor right (or the OK
button), confirm with OK and wait until Done appears. In
case the download to the USB stick was not successful
Failure will appear. In this case, check if the USB stick is
connected properly and if the directory repair is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download onto another
TV or other SSB. Uploading is of course only possible if the
software is running and if a picture is available. This
method is created to be able to save the customers TV
settings and to store them into another SSB.
Download to USB. To download several settings from the
USB stick to the TV, same way of working needs to be
followed as with uploading. To make sure that the
download of the channel list from USB to the TV is
executed properly, it is necessary to restart the TV and
tune to a valid preset if necessary.
NVM editor. For NET TV the set type must be installed.
Also the production code can be entered via the RCtransmitter.

Note: When the NVM is corrupted, or replaced, there is a high


possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, its advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments)
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code 062598 directly followed by the MENU (or HOME)

How to Navigate
In SAM, the menu items can be selected with the
CURSOR UP/DOWN key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the CURSOR UP/DOWN key to
display the next/previous menu items.
With the CURSOR LEFT/RIGHT keys, it is possible to:
(De) activate the selected menu item.
(De) activate the selected sub menu.
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2010-Apr-02

EN 14

5.

Q552.1A LA

Service Modes, Error Codes, and Fault Finding

With the OK key, it is possible to activate the selected


action.

How to Exit SAM


Use one of the following methods:
Switch the TV set to STAND-BY via the RC-transmitter.
Via a standard RC-transmitter, key in 00 sequence, or
select the BACK key.
5.2.3

Customer Service Mode (CSM)

Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The Service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the Service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.

Software versions
Current main SW. Displays the build-in main software
version. In case of field problems related to software,
software can be upgraded. As this software is consumer
upgradeable, it will also be published on the Internet.
Example: Q555X_1.2.3.4
Standby SW. Displays the build-in stand-by processor
software version. Upgrading this software will be possible
via ComPair or via USB (see section 5.9 Software
Upgrading).
Example: STDBY_88.68.1.2.
e-UM version. Displays the electronic user manual SWversion.

When in this chassis CSM is activated, a testpattern will be


displayed during 5 seconds (1 second Blue, 1 second Green
and 1 second Red, then again 1 second Blue and 1 second
Green). This test pattern is generated by the PNX51X0. So if
this test pattern is shown, it could be determined that the back
end video chain (PNX51X0, LVDS, and display) of the SSB is
working. For TV sets without the PNX51X0 inside, every menu
from CSM will be used as check for the back end video chain.

Quality items
Signal quality. bad / average /good
Ethernet MAC address. Dispays the MAC address
present in the SSB.
Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.
BDS key. Indicates if the set is in the BDS status.
CI slot present. If the common interface module is
detected.
Event counter.

When CSM is activated and there is a USB stick connected to


the TV set, the software will dump the complete CSM content
to the USB stick. The file (Csm.txt) will be saved in the root of
the USB stick. This info can be handy if no information is
displayed. To have fast feedback from the field, a flashdump
can be requested. While in CSM, push the red button + dial
serial digits 2679 (same keys to form the word COPY with a
cellphone). A file Dump_settype_serienumber.bin will be
written on the connected USB device. This can take 1/2 minute,
depending on the quantity of data that needs to be dumped.

How to Exit CSM


Press MENU (or HOME) / Back key on the RC-transmitter.

Also when CSM is activated, the LAYER 1 error is displayed via


blinking LED. Only the latest error is displayed. (see also
section 5.5 Error Codes).
How to Activate CSM
Key in the code 123654 via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
How to Navigate
By means of the CURSOR-DOWN/UP knob on the RCtransmitter, can be navigated through the menus.
Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.
General
Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM. This
can be done in SAM via the NVM editor, or via ComPair.
Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. This can be done in SAM via the NVM
editor, or via ComPair.
2010-Apr-02

Installed date. Indicates the date of the first installation of


the TV. This date is acquired via time extraction.
Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. ComPair will foresee in a possibility to do this. This
identification number is the 12nc number of the SSB.
12NC display. Shows the 12NC of the display.
12NC supply. Shows the 12NC of the supply.
12NC 200Hz board. Shows the 12NC of the 200Hz Panel.

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Service Modes, Error Codes, and Fault Finding


5.3

Stepwise Start-up

Q552.1A LA

5.

EN 15

7U0X or others FETs on shortcircuit before activating SDM via


the service pads.

When the TV is in a protection state due to an error detected by


stand-by software (error blinking is displayed) and SDM is
activated via shortcutting the SDM solder path on the SSB, the
TV starts up until it reaches the situation just before protection.
So, this is a kind of automatic stepwise start-up. In combination
with the start-up diagrams below, you can see which supplies
are present at a certain moment. Caution: in case the start-up
in this mode with a faulty FET 7U0X is done, you can destroy
all ICs supplied by the +1V8 and +1v1, due to overvoltage (12V
on XVX-line). It is recommended to measure first the FET

The abbreviations SP and MP in the figures stand for:


SP: protection or error detected by the Stand-by
Processor.
MP: protection or error detected by the MIPS Main
Processor.

Mains
off

Mains
on

- WakeUp requested
- Acquisition needed
- Tact switch pushed

St by

WakeUp
requested

Semi
St by

- stby requested and


no data Acquisition
required

Active
- St by requested
- tact SW pushed

Tact switch
pushed

Hibernate

WakeUp
requested
(SDM)

- Tact switch pushed


- last status is hibernate
after mains ON

GoToProtection
GoToProtection

Protection

18770_250_100216.eps
100402

Figure 5-3 Transition diagram

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div. table

2010-Apr-02

EN 16

5.

Service Modes, Error Codes, and Fault Finding

Q552.1A LA

Off
Stand by or
Protection

Mains is applied

Standby Supply starts running.


All standby supply voltages become available.

st-by P resets

If the protection state was left by short circuiting the


SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
not be entered.

Initialise I/O pins of the st-by P:


- Switch reset-AVC LOW (reset state)
- Switch reset-system LOW (reset state)
- Switch reset-Ethernet LOW (reset state)
- Switch reset-USB LOW (reset state)
- Switch reset-DVBs LOW (reset state)
- keep Audio-reset and Audio-Mute-Up HIGH

- Switch Audio-Reset high.


It is low in the standby mode if the standby
mode lasted longer than 10s.

start keyboard scanning, RC detection. Wake up reasons are


off.

Switch ON Platform and display supply by switching


LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power


is switched on, followed by the +1V2 DCDC converter
Detect2 is moved to an interrupt. To be checked if
the detection on interrupt base is feasible or not or if
we should stick to the standard 40ms interval.

Detect2 high received


within 2 seconds?

Yes

12V error:
Layer1: 3
Layer2: 16

No

Enter protection

Enable the DCDC converters


(ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set IC slave address


of Standby P to (A0h)

Detect EJTAG debug probe


(pulling pin of the probe interface to
ground by inserting EJTAG probe)

An EJTAG probe (e.g. WindPower ICE probe) can be


connected for Linux Kernel debugging purposes.

EJTAG probe
connected ?

Yes

No
No

No

Cold boot?

Yes
Release AVC system reset
Feed warm boot script

Release AVC system reset


Feed cold boot script

Release AVC system reset


Feed initializing boot script
disable alive mechanism

18770_251_100216.eps
100216

Figure 5-4 Off to Semi Stand-by flowchart (part 1)

2010-Apr-02

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Service Modes, Error Codes, and Fault Finding

Q552.1A LA

5.

Reset-system is switched HIGH by the


AVC at the end of the bootscript

Reset-system is switched HIGH by the


AVC at the end of the bootscript

AVC releases Reset-Ethernet, Reset-USB and


Reset-DVBs when the end of the AVC bootscript is detected

AVC releases Reset-Ethernet, Reset-USB and


Reset-DVBs when the end of the AVC bootscript is detected

Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the
startup process

Reset-Audio and Audio-Mute-Up are


switched by MIPS code later on in the
startup process

EN 17

No

This cannot be done through the bootscript,


the I/O is on the standby P

Timing need to be updated if


more mature info is available.

Bootscript ready
in 1250 ms?

No

Yes
Set IC slave address
of Standby P to (60h)

RPC start (comm. protocol)


Timing needs to
be updated if more
mature info is
available.

Flash to Ram
image transfer succeeded
within 30s?

No
Code =
Layer1: 2
Layer2: 15

Yes

Switch AVC PNX85500 in


reset (active low)

Code =
Layer1: 2
Layer2: 53

No

SW initialization
succeeded
within 20s?

Wait 10ms

Timing needs to be
updated if more
mature info is
available.

Yes

Enable Alive check mechanism


Disable all supply related protections and
switch off the +3V3 +5V DC/DC converter.
MIPS reads the wake up reason
from standby P.

Wait until AVC starts to


communicate

Wait 5ms

switch off the remaining DC/DC


converters

3-th try?

Startup screen shall only be visible when there is a coldboot to


an active state end situation. The startup screen shall not be
visible when waking up for reboot reasons or waking up to semistandby conditions or waking up to enter Hibernate mode..

Wake up reason
coldboot & not semistandby?
yes

Switch Standby I/O line high


and wait 4 seconds

The first time after the option turn on of the startup screen or
when the set is virgin, the cfg file is not present and hence
the startup screen will not be shown.

Startup screen cfg file


present?

Yes

yes

Blink Code as
error code

200Hz set?

yes

No

Enter protection

85500 sends out startup screen

85500 sends out startup screen

85500 starts up the display.

200Hz Tcon has started up the


display.

Startup screen visible

85500 requests Lamp on

No

No
To keep this flowchart readable, the exact
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid.

Startup screen visible

Initialize audio
initialize tuner and channel decoders
Initialize source selection
Initialize video processing ICs

initialize AutoTV by triggering CHS AutoTV Init interface


Initialize Ambilight with Lights off.

Semi-Standby
18770_252_100216.eps
100216

Figure 5-5 Off to Semi Stand-by flowchart (part 2)

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2010-Apr-02

EN 18

5.

Q552.1A LA

Service Modes, Error Codes, and Fault Finding

Constraints taken into account:


- Display may only be started when valid LVDS output clock can be delivered by the AVC.
- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty
cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output
level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts,
the picture should only be unblanked after these first seconds.

Semi Standby

The assumption here is that a fast toggle (<2s) can


only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STBY->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s.

Wait until previous on-state is left more than 2


seconds ago. (to prevent LCD display problems)

Assert RGB video blanking


and audio mute

CPipe already generates a valid output


clock in the semi-standby state: display
startup can start immediately when leaving
the semi-standby state.

Display already on?


(splash screen)
No

Switch on the display power by


switching LCD-PWR-ON low

The exact timings to


switch on the
display (LVDS
delay, lamp delay)
are defined in the
display file.

Yes
Wait x ms
Initialize audio and video
processing IC's and functions
according needed use case.

Switch on LVDS output in the 85500


Delay Lamp-on with the sum of the LVDS delay and
the Lamp delay indicated in the display file

Switch off the dimming backlight feature, set


the BOOST control to nominal and make sure
PWM output is set to maximum allowed PWM

Switch on LCD backlight (Lamp-ON)

Start POK line


detection algorithm

Wait until valid and stable audio and video, corresponding to the
requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.

return

Switch Audio-Reset low and wait 5ms


A LED set does not normally need a
preheat time. The preheat remains present
but is set to zero in the display file.

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)

Restore dimming backlight feature, PWM and BOOST output


and unblank the video.

The higher level requirement is that audio and video


should be demuted without transient effects and that
the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_253_100216.eps
100216

Figure 5-6 Semi Stand-by to Active flowchart (EEFL or LED backlight 50/100 Hz only)

2010-Apr-02

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Service Modes, Error Codes, and Fault Finding

The assumption here is that a fast toggle (<2s)


can only happen during ON->SEMI ->ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI>STBY->SEMI->ON can be made in less than 2s,
we have to delay the semi -> stby transition until
the requirement is met.

Q552.1A LA

5.

EN 19

Semi Standby
Wait until previous on-state is left more than 2
seconds ago. (to prevent LCD display problems)

Assert RGB video blanking


and audio mute

There is no need to define the


display timings since the timing
implementation is part of the Tcon.

Backlight already on?


(splash screen)
Yes
Initialize audio and video
processing IC's and functions
according needed use case.

No
Request Tcon to Switch on the backlight in a
direct LED or
set Lamp-on I/O line in case of a side LED

Start POK line


detection algorithm
Wait until valid and stable audio and video, corresponding to
the requested output is delivered by the AVC.
return
Switch Audio-Reset low and wait 5ms

The higher level requirement is that audio and


video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblanking of the video.

Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)

unblank the video.

Switch on the Ambilight functionality according the last status


settings.

Startup screen Option


and Installation setting
Photoscreen ON?
Yes
Display cfg file present
and up to date, according
correct display option?
No
No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
18770_254_100216.eps
100216

Figure 5-7 Semi Stand-by to Active flowchart (LED backlight 200 Hz)

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div. table

2010-Apr-02

EN 20

5.

Q552.1A LA

Service Modes, Error Codes, and Fault Finding

Active
Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground


(I/O: audio reset)
And wait 5ms

switch off Ambilight

Wait until Ambilight has faded out: Output power


Observer should be zero

Switch off POK line


detection algorithm

switch off LCD backlight


(I/O or IC)

Mute all video outputs

Yes

200Hz set?

No

Wait x ms (display file)


Instruct 200Hz
Tcon to turn off
the display

Switch off LVDS output in 85500

Wait x ms

The exact timings to


switch off the
display (LVDS
delay, lamp delay)
are defined in the
display file.

Switch off the display power by


switching LCD-PWR-ON high

Semi Standby
18770_255_100216.eps
100216

Figure 5-8 Active to Semi Stand-by flowchart

2010-Apr-02

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div. table

Service Modes, Error Codes, and Fault Finding

Q552.1A LA

5.

EN 21

Semi Stand by

If ambientlight functionality was used in semi-standby


(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is


finished. *)

*) If this is not performed and the set is


switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

Switch Memories to self-refresh (this creates a more


stable condition when switching off the power).

Switch AVC system in reset state (reset-system and


reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Wait 10ms

Disable all supply related protections and switch off


the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the


Standby I/O line

Important remarks:
release reset audio 10 sec after entering
standby to save power
Also here, the standby state has to be
maintained for at least 4s before starting
another state transition.

Stand by
18770_256_100216.eps
100216

Figure 5-9 Semi Stand-by to Stand-by flowchart

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2010-Apr-02

EN 22

5.

Service Modes, Error Codes, and Fault Finding

Q552.1A LA

5.4

Service Tools

5.5

Error Codes

5.4.1

ComPair

5.5.1

Introduction

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips
Consumer Electronics products. and offers the following:
1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this.
3. ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the P
is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.

The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.

Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an
USB cable. For the TV chassis, the ComPair interface box and
the TV communicate via a bi-directional cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television, by a combination of
automatic diagnostics and an interactive question/answer
procedure.

New in this chassis is the way errors can be displayed:

How to Connect
This is described in the chassis fault finding database in
ComPair.

TO TV
TO
UART SERVICE
CONNECTOR

ComPair II
RC in

RC out

TO
I2C SERVICE
CONNECTOR

TO
UART SERVICE
CONNECTOR

Multi
function

Optional Power Link/ Mode


Switch
Activity

I2C

RS232 /UART

If no errors are there, the LED should not blink at all in


CSM or SDM. No spacer must be displayed as well.
There is a simple blinking LED procedure for board
level repair (home repair) so called LAYER 1 errors
next to the existing errors which are LAYER 2 errors (see
Table 5-2).
LAYER 1 errors are one digit errors.
LAYER 2 errors are 2 digit errors.
In protection mode.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
In CSM mode.
When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
In SDM mode.
When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Error display on screen.
In CSM no error codes are displayed on screen.
In SAM the complete error list is shown.

PC

Basically there are three kinds of errors:


Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section 5.6 The Blinking LED Procedure).
Errors detected by the Stand-by software which not
lead to protection. In this case the front LED should blink
the involved error. See also section 5.5 Error Codes, 5.5.4
Error Buffer, Extra Info. Note that it can take up several
minutes before the TV starts blinking the error (e.g. LAYER
1 error = 2, LAYER 2 error = 15 or 53).
Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.

ComPair II Developed by Philips Brugge

HDMI
I2C only

Optional power
5V DC

10000_036_090121.eps
091118

Figure 5-10 ComPair II interface connection


Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be
blown!

5.5.2

Use one of the following methods:


On screen via the SAM (only when a picture is visible).
E.g.:
00 00 00 00 00: No errors detected
23 00 00 00 00: Error code 23 is the last and only
detected error.
37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note that no protection errors can be logged in the
error buffer.

How to Order
ComPair II order codes:
ComPair II interface: 3122 785 91020.
Software is available via the Philips Service web portal.
ComPair UART interface cable for Q55x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
Note: While encounting problems, contact the local support
desk.
2010-Apr-02

How to Read the Error Buffer

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div. table

Service Modes, Error Codes, and Fault Finding

5.5.3

5.

EN 23

content, as this history can give significant information). This to


ensure that old error codes are no longer present.
If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Via error bits in the status registers of ICs.
Via polling on I/O pins going to the stand-by processor.
Via sensing of analogue values on the stand-by processor
or the PNX85500.
Via a not acknowledge of an I2C communication.

Via the blinking LED procedure. See section 5.5.3 How to


Clear the Error Buffer.
Via ComPair.

How to Clear the Error Buffer


Use one of the following methods:
By activation of the RESET ERROR BUFFER command
in the SAM menu.
If the content of the error buffer has not changed for 50+
hours, it resets automatically.

5.5.4

Q552.1A LA

Error Buffer

Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
check if the front LED is blinking or if an error is logged.

In case of non-intermittent faults, clear the error buffer before


starting to repair (before clearing the buffer, write down the
Table 5-2 Error code overview

Description

Monitored Error/ Error Buffer/


Layer 1 Layer 2 by
Prot Blinking LED Device

Defective Board

I2C3

13

MIPS

BL / EB

SSB

SSB

I2C2

14

MIPS

BL / EB

SSB

SSB

I2C4

18

MIPS

BL / EB

SSB

SSB

PNX doesnt boot (HW cause) 2

15

Stby P

BL

PNX8550

SSB

12V

16

Stby P

BL

Supply

Inverter or display supply

17

MIPS

EB

Supply

HDMI mux

23

MIPS

EB

Sil9x87A

SSB

I2C switch

24

MIPS

EB

PCA9540

SSB

Channel dec DVB-S

28

MIPS

EB

STV0903

SSB

Lnb controller

31

MIPS

EB

LNBH23

SSB

Tuner

34

MIPS

EB

DTT 71300

SSB

Main nvm

35

MIPS

EB

STM24C64

SSB

Tuner DVB-S

36

MIPS

EB

STV6110

SSB

T sensor SSB/set

42

MIPS

EB

LM 75

T sensor

T sensor LED driver/Tcon

42

MIPS

EB

LM 75

T sensor

PNX doesnt boot (SW cause) 2

53

Stby P

BL

PNX8550

SSB

Display

64

MIPS

BL / EB

Altera

Display

Extra Info
Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section 5.8 Fault Finding and Repair Tips, 5.8.6
Logging). Its shown that the loggings which are generated
by the main software keep continuing. In this case
diagnose has to be done via ComPair.
Error 13 (I2C bus 3, SSB bus blocked). At the time of
release of this manual, this error was not working as
expected. Current situation: when this error occurs, the TV
will constantly reboot due to the blocked bus. The best way
for further diagnosis here, is to use ComPair.
Error 14 (I2C bus 2, TV set bus blocked). At the time of
release of this manual, this error was not working as
expected. Current situation: when this error occurs, the TV
will constantly reboot due to the blocked bus. The best way
for further diagnosis here, is to use ComPair.
Error 18 (I2C bus 4, Tuner bus blocked). At the time of
release of this manual, this error was not working as
expected. Current situation: when this error occurs, the TV
will constantly reboot due to the blocked bus. The best way
for further diagnosis here, is to use ComPair.
Error 15 (PNX8550 doesnt boot). Indicates that the main
processor was not able to read his bootscript. This error will
point to a hardware problem around the PNX8550
(supplies not OK, PNX 8550 completely dead, I2C link
between PNX and Stand-by Processor broken, etc...).
When error 15 occurs it is also possible that I2C1 bus is

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div. table

blocked (NVM). I2C1 can be indicated in the schematics as


follows: SCL-UP-MIPS, SDA-UP-MIPS.
Other root causes for this error can be due to hardware
problems regarding the DDRs and the bootscript reading
from the PNX8550.
Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM is activated we see blinking LED
LAYER 2 error = 16.
Error 17 (Invertor or Display Supply). Here the status of
the Power OK is checked by software, no protection will
occur during failure of the invertor or display supply (no
picture), only error logging. LED blinking of LAYER 1
error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
Error 23 (HDMI). When there is no I2C communication
towards the HDMI mux after start-up, LAYER 2 error = 23
will be logged and displayed via the blinking LED
procedure if SDM is switched on.
Error 24 (I2C switch). When there is no I2C
communication towards the I2C switch, LAYER 2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on. Remark : this only
works for TV sets with an I2C controlled screen included.
Error 28 (Channel dec DVB-S). When there is no I2C
communication towards the DVB-S channel decoder,
LAYER 2 error = 28 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 31 (Lnb controller). When there is no I2C
communication towards this device, LAYER 2 error = 31

2010-Apr-02

EN 24

5.

Q552.1A LA

Service Modes, Error Codes, and Fault Finding


6. The sequence starts again.

will be logged and displayed via the blinking LED


procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
Error 35 (main NVM). When there is no I2C
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
procedure when SDM is switched on. All service modes
(CSM, SAM and SDM) are accessible during this failure,
observed in the Uart logging as follows : "<< ERRO >>>
PFPOW_.C : First Error (id19, Layer_1= 2 Layer_= 35)".
Error 36 (Tuner DVB-S). When there is no I2C
communication towards the DVB-S tuner during start-up,
LAYER 2 error = 36 will be logged and displayed via the
blinking LED procedure when SDM is switched on.
Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
Error 53. This error will indicate that the PNX8550 has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM,
LAYER 2 error = 53.
Error 64. Only applicable for TV sets with an I2C controlled
screen .

5.6

The Blinking LED Procedure

5.6.1

Introduction

5.6.2

Use one of the following methods:


Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in normal operation
mode or automatically when the error/protection is
monitored by the standby processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether error devices are
mentioned. (see section 5.8 Fault Finding and Repair
Tips, 5.8.6 Logging).
Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
normal operation mode or when SDM (via hardware pins)
is activated when the tv set is in protection.

5.7

Protections

5.7.1

Software Protections
Most of the protections and errors use either the stand-by
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
Related to supplies: presence of the +5V, +3V3 and 1V2
needs to be measured, no protection triggered here.
Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.

The blinking LED procedure can be split up into two situations:


Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table 5-2 Error code
overview) which causes the failure of the TV. This
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a
distance.
Blinking LED procedure LAYER 2 error. Via this
procedure, the contents of the error buffer can be made
visible via the front LED. In this case the error contains
2 digits (see table 5-2 Error code overview) and will be
displayed when SDM (hardware pins) is activated. This is
especially useful for fault finding and gives more details
regarding the failure of the defective board.
Important remark:
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed.

Remark on the Supply Errors


The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimise the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see section 5.3 Stepwise Start-up).
5.7.2

When one of the blinking LED procedures is activated, the front


LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
1. n long blinks (where n = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. n short blinks (where n= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s (spacer).
6. The sequence starts again.

Hardware Protections
The only real hardware protection in this chassis appears in
case of an audio problem e.g. DC voltage on the speakers. This
protection will only affect the Class D audio amplifier (item
7D10; see diagram B03A) and puts the amplifier in a
continuous burst mode (cyclus approximately 2 seconds).
Repair Tip
There still will be a picture available but no sound. While
the Class D amplifier tries to start-up again, the cone of the
loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
starts over and over again. The headphone amplifier will
also behaves similar.

Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence (spacer).
2010-Apr-02

How to Activate

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Service Modes, Error Codes, and Fault Finding


5.8

Fault Finding and Repair Tips

Ambilight

Audio Amplifier
The Class D-IC 7D10 has a powerpad for cooling. When the IC
is replaced it must be ensured that the powerpad is very well
pushed to the PWB while the solder is still liquid. This is needed
to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.

5.8.3

At start-up, +24V becomes available when STANDBY signal is


low (together with +12V for the basic board), when +3V3 from
the basic board is present the two DC-DC converters channels
inside 7T03 are activated. Initially only the 24V to 5V converter
(channel 1 of 7T03 generating +5V-DVBS) will effectively work,
while +V-LNB is held at a level around 11V7 via diode 6T55.
After 7T05 is initialized, the second channel of 7T03 will start
and generates a voltage higher then LNB-RF1 with 0V8. +5VDVBS start-up will imply +3V3-DVBS start-up, with a small
delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will
be enabled.

CSM
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)

5.8.4

EN 25

Description DVB-S2:
LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel
of 7T03 followed by 7T50 LNB supply control IC.It provides
supply voltage that feeds the outdoor satellite reception
equipment.
+3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
via a 5V to 1V DC-DC converter and is stabilised at the
point of load (channel decoder) by means of feedback
signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
are generated via linear stabilisers from +5V-DVBS that by
itself is generated via the first conversion channel of 7T03.

Due to degeneration process of the LEDs fitted on the ambi


module, there can be a difference in the colour and/or light
output of the spare ambilight modules in comparison with the
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be adjusted.
5.8.2

5.

+12V is considered OK (=> DETECT2 signal becomes high,


+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
can be started up) if it rises above 10V and doesnt drop below
9V5. A small delay of a few milliseconds is introduced between
the start-up of 12V to +1V8 DC-DC converter and the two other
DC-DC converters via 7U48 and associated components.

Read also section 5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info.
5.8.1

Q552.1A LA

DC/DC Converter
Description basic board

If +24V drops below +15V level then the DVB-S2 supply will
stop, even if +3V3 is still present..

The basic board power supply consists of 4 DC/DC converters


and 5 linear stabilisers. All DC/DC converters have +12V input
voltage and deliver :
+1V1 supply voltage (1.15V nominal), for the core voltage
of PNX85500, stabilised close to the point of load;
SENSE+1V1 signal provides the DC-DC converter the
needed feedback to achieve this.
+1V8 supply voltage, for the DDR2 memories and DDR2
interface of PNX85500.
+3V3 supply voltage (3.30V nominal), overall 3.3 V for
onboard ICs, for non-5000 series SSB diversities only.
+5V (5.15V nominal) for USB, WIFI and Conditional
Access Module and +5V5-TUN for +5V-TUN tuner
stabiliser.

Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power-on via the mains cord,
presuming that the standby microprocessor and the external
supply are operational. Take STANDBY signal high-to-low
transition as time reference.
When +12V becomes available (maximum 1 second after
STANDBY signal goes low) then +1V1 is started immediately.
After ENABLE-3V3 goes low, all the other supply voltages
should rise within a few milliseconds.
Tips
Behaviour comparison with a reference TV550 platform
can be a fast way to locate failures.
If +12V stays low, check the integrity of fuse 1U40.
Check the integrity (at least no short circuit between drain
and source) of the power MOS-FETs before starting up the
platform in SDM, otherwise many components might be
damaged. Using a ohmmeter can detect short circuits
between any power rail and ground or between +12V and
any other power rail.
Short circuit at the output of an integrated linear stabiliser
(7UC0, 7UD2 or 7UD3) will heat up this device strongly.
Switching frequencies should be 500 kHz ...600 kHz for
12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC
converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V
LNB DC-DC converters operates at 300 kHz while for 5 V
to 1.1 V DC-DC converter 900 kHz is used.

The linear stabilisers are providing:


+1V2 supply voltage (1.2V nominal), stabilised close to
PNX85500 device, for various other internal blocks of
PNX85500; SENSE+1V2 signal provides the needed
feedback to achieve this.
+2V5 supply voltage (2.5V nominal) for LVDS interface and
various other internal blocks of PNX85500; for 5000 series
SSB diversities the stabiliser is 7UD2 while for the other
diversities 7UC0 is used.
+3V3 supply voltage (3V3 nominal) for 5000 series SSB
diversities, provided by 7UD3; in this case the 12V to 3V3
DC-DC converter is not present.
+5V-TUN supply voltage (5V nominal) for tuner and IF
amplifier.
+3V3-STANDY (3V3 nominal) is the permanent voltage,
supplying the standby microprocessor inside PNX85500.
5.8.5

Supply voltage +1V1 is started immediately when +12V voltage


becomes available (+12V is enabled by STANDBY signal when
low). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN
are switched on by signal ENABLE-3V3 when low, provided
that +12V (detected via 7U40 and 7U41) is present.

Exit Factory Mode


When an F is displayed in the screens right corner, this
means the set is in Factory mode, and it normally
happens after a new SSB is mounted. To exit this mode, push
the VOLUME minus button on the TVs local keyboard for 10
seconds (this disables the continuous mode).

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2010-Apr-02

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5.

Q552.1A LA

Service Modes, Error Codes, and Fault Finding

Then push the SOURCE button for 10 seconds until the F


disappears from the screen.
5.8.6

Logging
When something is wrong with the TV set (f.i. the set is
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a ComPair UARTcable (3138 188 75051) from the service connector in the TV to
the multi function jack at the front of ComPair II box.
Required settings in ComPair before starting to log :
- Start up the ComPair application.
- Select the correct database (open file Q55X.X, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. logging)
in the Connection Description box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the Display Option Code (useful when there is no picture),
look for item DisplayRawNumber in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for error devices in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.

5.8.7

Loudspeakers
Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!

5.8.8

PSL
In case of no picture when CSM (test pattern) is activated and
backlight doesnt light up, its recommended first to check the
inverter on the PSL + wiring (LAYER 2 error = 17 is displayed
in SDM).

5.8.9

Tuner
Attention: In case the tuner is replaced, always check the tuner
options!

5.8.10 Display option code


Attention: In case the SSB is replaced, always check the
display option code in SAM, even when picture is available.
Performance with the incorrect display option code can lead to
unwanted side-effects for certain conditions.
New in this chassis:
While in the download application (start up in TV mode + OK
button pressed), the display option code can be changed via
062598 HOME XXX special SAM command (XXX=display
option in 3 digits).

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Service Modes, Error Codes, and Fault Finding

Q552.1A LA

5.

EN 27

5.8.11 SSB Replacement


Follow the instructions in the flowchart in case a SSB has to be
exchanged. See figure SSB replacement flowchart.
In st ru ct io n n o t e SSB rep lacem en t Q543.x, Q548.x, Q549.x, and Q55x.x

ST AR T

Before starting:
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder upgrades in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in
case there are more than one "autorun.upg" files on the USB stick.

Set is still oper ating?


No
Yes

C onnect the U SB stick to the set,


go to SAM and save the current TV settings via Upload to USB
1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.

Start-up the set


Due to a possible wrong display option code in the received Service
SSB (NVM), its possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback).
No pictur e displayed

1) Start up the TV set, equiped with the Service SSB,


and enable the UART logging on the PC.

Set behaviour?

Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen

2) The TV set will start-up automatically in the


download application if main TV software is not loaded.

3) Plug the prepared USB stick into the TV set. Follow the
instructions in the UART log file, press Right cursor key to enter
the list. Navigate to the autorun.upg file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press Ok.

1) Plug the USB stick into the TV set and select


the autorun .upg file in the displayed browser.

2) Now the main software will be loaded automatically,


supported by a progress bar.
4) Press "Down" cursor and Ok to start flashing the main
TV software. Printouts like: L: 1-100%, V: 1-100% and
P: 1-100% should be visible now in the UART logging.

5) Wait until the message Operation successful ! is logged in


the UART log and remove all inserted media. Restart the TV set.

3) Wait until the message Operation successful ! is displayed


and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where
xxx is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the Display Option code, the set is going to


Standby
(= validation of code)

No

Connect PC via the ComPair interface to Service connector.

Restart the set

Saved settings
on USB stick?

Yes

Start TV in Jett mode (DVD I + (OSD))


Open ComPair browser Q54x

Go to SAM and reload settings


via Download from USB function.

In case of settings reloaded from USB, the set type,


serial number, display 12 NC, are automatically stored
when entering display options.

Program set type number, serial number, and display 12 NC


Program E - DFU if needed.
If not already done:
Check latest software on Service website.
Update main and Stand-by software via USB.

Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.

- Check if correct display option code is programmed.


- Verify option codes according to sticker inside the set.
- Default settings for white drive > see Service Manual.

Check and perform alignments in SAM according to the


Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.


Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End

Q54x.E SSB Board swap VDS


Updated 22-03-2010

H_16771_007a.eps
100402

Figure 5-11 SSB replacement flowchart

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2010-Apr-02

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5.

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Service Modes, Error Codes, and Fault Finding

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the


RED LED is continuous on.

An F is displayed (and the HDMI 1


input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10
seconds
- Press the SOURCE button for 10 seconds until the F disappears
from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced


with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct


disabling of the Factory mode.

Program display option code


via 062598 MENU, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).

After entering display option code, the set is


going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
100322

Figure 5-12 SSB replacement flowchart - Factory mode

2010-Apr-02

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Service Modes, Error Codes, and Fault Finding


5.9

Software Upgrading

5.9.1

Introduction

5.

EN 29

Back-up Software Upgrade Application


If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the back-up software upgrade
application.
How to start the back-up software upgrade application
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the CURSOR DOWN-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.
3. The back-up software upgrade application will start.

The set software and security keys are stored in a NANDFlash, which is connected to the PNX85500.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A
description on how to upgrade the main software can be found
in the electronic User Manual.
5.9.3
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if the CI + key, MAC address.. are valid.
For the correct order number of a new SSB, always refer to the
Spare Parts list!
5.9.2

Q552.1A LA

Stand-by Software Upgrade via USB


In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
software via USB.
Use the following steps:
1. Create a directory UPGRADES on the USB stick.
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbySW_CFT72_88.0.0.0.upg) into this directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section
Manual Software Upgrade.
5. Select the appropriate file and press the OK button to
upgrade.

Main Software Upgrade


5.9.4

Content and Usage of the One-Zip Software File

The UpgradeAll.upg file is only used in the factory.


Below the content of the One-Zip file is explained, and
instructions on how and when to use it.
FUS_Q5551_x.x.x.x_commercial.zip. Contains the
autorun.upg which is needed to upgrade the TV main
software and the software download application.
StandbySW_CFTxx_x.x.x.x_commercial.zip. Contains
the Stand-by software in upg and hex format.
The StandbySW_xxxxx_prod.upg file can be used to
upgrade the Stand-by software via USB.
The StandbySW_xxxxx.hex file can be used to
upgrade the Stand-by software via ComPair.
The files StandbySW_xxxxx_exhex.hex and
StandbySW_xxxxx_dev.upg may not be used by
Service technicians (only for development purposes).
UpgradeAll_Q555X_x.x.x.x_commercial.zip. Only for
production purposes, not to be used by Service
technicians.
ProcessNVM_Q55XX_x.x.x.x.zip. Default NVM content.
Must be programmed via ComPair or can be loaded via
USB, be aware that all alignments stored in NVM are
overwritten here.

Automatic Software Upgrade


In normal conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the AUTORUN.UPG
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
_Q555X_ x.x.x.x_commercial.zip). This can also be done by
the consumers themselves, but they will have to get their
software from the commercial Philips website or via the
Software Update Assistant in the user menu (see eUM). The
autorun.upg file must be placed in the root of the USB stick.
How to upgrade:
1. Copy AUTORUN.UPG to the root of the USB stick.
2. Insert USB stick in the set while the set is operational. The
set will restart and the upgrading will start automatically. As
soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.
Manual Software Upgrade
In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the OK button on a Philips TV remote control or a
Philips DVD RC-6 remote control (it is also possible to use
a TV remote in DVD mode). Keep the OK button
pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.

5.9.5

UART logging 2K10 (see section 5.8 Fault Finding and


Repair Tips, 5.8.6 Logging)

Attention!
In case the download application has been started manually,
the autorun.upg will maybe not be recognized.
What to do in this case:
1. Create a directory UPGRADES on the USB stick.
2. Rename the autorun.upg to something else, e.g. to
software.upg. Do not use long or complicated names,
keep it simple. Make sure that AUTORUN.UPG is no
longer present in the root of the USB stick.
3. Copy the renamed upg file into this directory.
4. Insert USB stick into the TV.
5. The renamed upg file will be visible and selectable in the
upgrade application.

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EN 30

6.

Q552.1A LA

Alignments

6. Alignments
For the next alignments, supply the following test signals via a
video generator to the RF input:
EU/AP-PAL models: a PAL B/G TV-signal with a signal
strength of at least 1 mV and a frequency of 475.25 MHz
US/AP-NTSC models: an NTSC M/N TV-signal with a
signal strength of at least 1 mV and a frequency of 61.25
MHz (channel 3).
LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).

Index of this chapter:


6.1 General Alignment Conditions
6.2 Hardware Alignments
6.3 Software Alignments
6.4 Option Settings
6.5 Reset of Repaired SSB
6.6 Service SSB delivered without main software loaded
6.7 Total Overview SAM modes

6.1

General Alignment Conditions


6.3.1

Perform all electrical adjustments under the following


conditions:
Power supply voltage (depends on region):
AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
EU: 230 VAC / 50 Hz ( 10%).
LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
US: 120 VAC / 60 Hz ( 10%).
Connect the set to the mains via an isolation transformer
with low internal resistance.
Allow the set to warm up for approximately 15 minutes.
Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to
AUDIO_GND).
Caution: It is not allowed to use heat sinks as ground.
Test probe: Ri > 10 M, Ci < 20 pF.
Use an isolated trimmer/screwdriver to perform
alignments.
6.1.1

Picture Setting
Contrast

100

Brightness

50

Colour

Light Sensor

Off

Picture format

Unscaled

In menu Picture, choose Pixel Plus HD and set picture


settings as follows:

Picture Setting
Dynamic Contrast

Off

Dynamic Backlight

Off

Colour Enhancement

Off

Gamma

White point alignment LCD screens:


Use a 90% white screen to the HDMI input and set the
following values:
Colour temperature: Normal.
All White point values to: 127.

First, set the correct options:


In SAM, select Option numbers.
Fill in the option settings for Group 1 and Group 2
according to the set sticker (see also paragraph 6.4
Option Settings).
Press OK on the remote control before the cursor is
moved to the left.
In submenu Option numbers select Store and press
OK on the RC.
OR:
In main menu, select Store again and press OK on
the RC.
Switch the set to Stand-by.
Warming up (>15 minutes).

Hardware Alignments

Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error
Codes, and Fault Finding). The SAM menu will now appear on
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
The following items can be aligned:
White point
Ambilight
TCON Alignment
Reset TCON Alignment.

Table 6-1 White D alignment values CCFL backlight panels


Value

To store the data:


Press OK on the RC before the cursor is moved to the
left
In main menu select Store and press OK on the RC
Switch the set to stand-by mode.

2010-Apr-02

Go to the SAM and select Alignments-> White point.

In case you have a colour analyser:


Measure with a calibrated contactless colour analyser
(Minolta CA-210 or Minolta CS-200) in the centre of the
screen. Consequently, the measurement needs to be done
in a dark environment.
Adjust the correct x, y coordinates (while holding one of the
White point registers R, G or B on 127) by means of
decreasing the value of one or two other white points to the
correct x, y coordinates (see Table 6-1 White D alignment
values CCFL backlight panels, 6-2 White D alignment
values LED backlight panels - colour analyser Minolta CA210 or 6-3 White D alignment values LED backlight panels
- colour analyser Minolta CS-200). Tolerance: dx: 0.002,
dy: 0.002.
Repeat this step for the other colour temperatures that
need to be aligned.
When finished press OK on the RC and then press STORE
(in the SAM root menu) to store the aligned values to the
NVM.
Restore the initial picture settings after the alignments.

Not applicable.

6.3

Choose TV menu, Setup, More TV Settings and then


Picture and set picture settings as follows:

Alignment Sequence

6.2

White Point

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Cool (11000K)

Normal (9000K)

Warm (6500K)

0.276

0.287

0.313

0.282

0.296

0.329

Alignments
6.3.3

Table 6-2 White D alignment values LED backlight panels -

Q552.1A LA

6.

EN 31

TCON Alignment

colour analyser Minolta CA-210


Value

Cool (9420K)

Normal (8120K)

Warm (6080K)

0.282

0.292

0.320

0.298

0.311

0.345

In TV sets with forward integration where the TCON device is


located on the small signal board or 200 Hz board, all TCON
values needs realignment for every SSB/display swap due to
repair or upgrade. The TCON alignment during assembly is
normally supported by a special testpattern and the use of a
camera, hence very difficult to simulate for home repair. A more
practical way with predefined settings is described below:

Table 6-3 White D alignment values LED backlight panels colour analyser Minolta CS-200
Value

Cool (11000K)

Normal (9000K)

Warm (6500K)

0.276

0.287

0.313

0.282

0.296

0.329

If you do not have a colour analyser, you can use the default
values. This is the next best solution. The default values are
average values coming from production.
Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
Set the RED, GREEN and BLUE default values according
to the values in Table 6-4 and Table 6-5.
When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.
Restore the initial picture settings after the alignments.

6.4

Option Settings

6.4.1

Introduction
The microprocessor communicates with a large number of I2C
ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these
PNX51XX ICs (back-end advanced video picture improvement
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control)
is made known by the option codes.

Table 6-4 White tone default setting 42" 1


White Tone
Colour Temp
Normal

Black level
offset
R

127

100

66

t.b.d.

t.b.d.

Cool

127

113

118

t.b.d.

t.b.d.

Warm

109

102

127

t.b.d.

t.b.d.

Notes:
After changing the option(s), save them by pressing the OK
button on the RC before the cursor is moved to the left,
select STORE in the SAM root menu and press OK on the
RC.
The new option setting is only active after the TV is
switched off / stand-by and on again with the mains
switch (the NVM is then read again).

Notes
1): data is preliminary and will be updated in next release.
Table 6-5 White tone default setting 46"
White Tone
Colour Temp
Normal

Black level
offset
R

t.b.d.

t.b.d.

t.b.d.

t.b.d.

t.b.d.

Cool

t.b.d.

t.b.d.

t.b.d.

t.b.d.

t.b.d.

Warm

t.b.d.

t.b.d.

t.b.d.

t.b.d.

t.b.d.

6.4.2

6.3.2

6.4.3

TCON Alignment

42"

443

46"

143

Dealer Options
For dealer options, in SAM select Dealer options.
See Table 6-8 SAM mode overview.

Table 6-6 TCON default settings


Screen size

Go to SAM (dial 062596 + OK button pressed).


Select Alignments.
TCON alignment: value with 4 digits, this can be changed
by RC-transmitter entry according the values listed in Table
6-6. The value shall be stored in:
- STVM100DC for Sharp
- MAX9668 for LGD
Reset TCON alignment: here, a default value (according
the display option code) will be copied from the display file
to the TCON and changes the current value to the default
value.

(Service) Options
Select the sub menu's to set the initialisation codes (options) of
the model number via text menus.
See Table 6-8 SAM mode overview.

Alignment of the Ambilight modules


6.4.4
Method:
Go to SAM (press 062596 + OK button).
Select Alignments.
Select Ambilight: a white testpattern shall be displayed.
Select the number of module (pixel) that have to be
aligned. Module (pixel) 1 is the first one which will come
across according the wire connection track as follows: start
by the small signal panel and proceed towards the
ambilient modules. This module (pixel) 1 will be connected
to the next module (pixel) 2 and etc.
Align the brightness compared with the neighbour
modules. The brightness will be automatically stored.
Select one of the 10 matrixes which most color respond
towards the neighbour modules. The alignment is stored
automatically.

Opt. No. (Option numbers)


Select this sub menu to set all options at once (expressed in
two long strings of numbers).
An option number (or option byte) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
When the NVM is replaced, all options will require resetting. To
be certain that the factory settings are reproduced exactly, you
must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set and in Table 6-7
Option and display code overview.
Example: The options sticker gives the following option
numbers:
08192 00133 01387 45160
12232 04256 00164 00000

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EN 32

6.

Q552.1A LA

Alignments

The first line (group 1) indicates hardware options 1 to 4, the


second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
See Table 6-7 Option and display code overview for the
options.
Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
Refer to Chapter 2. Technical Specifications, Diversity, and
Connections.
6.4.5

18310_221_090318.eps
090319

Option Code Overview


Figure 6-1 SSB identification

Table 6-7 Option and display code overview


CTN
(Alt. BOM#)

Options Group 1

Options Group 2

Disp.
code

6.6

42PFL8605D/93 02060 12803 23359 40647 33552 34310 00000 00000 272
02060 12803 23359 39363 00016 34304 00000 00000 272
42PFL8605/98
46PFL8605D/93 02060 13059 23359 40647 33551 34310 00000 00000 271

Due to a changed manufacturing process, new Service SSBs


can be delivered to the warehouse without main TV
software loaded. Below you find the steps to follow when such
an SSB is received.

Important: after having edited the option numbers as


described above, you must press OK on the remote control
before the cursor is moved to the left!
6.6.1

6.5

Reset of Repaired SSB

After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code of
the TV has to be set according to the type plate of the set. For
this (new in this platform), you can use the NVM editor in
SAM. This action also ensures the correct functioning of the
Net TV feature and access to the Net TV portals. The loading
of the CTN and production code can also be done via ComPair
(Model number programming).
6.6.2
In case of a display replacement, reset the Operation hours
display to 0, or to the operation hours of the replacement
display.

When no picture is available


Due to a possible wrong display option code in the received
Service SSB (NVM), no picture can be available at start-up and
thus no download application will be visible. Here you can
proceed and finalize step by step to load the main TV software
via the UART logging on the PC (for visual feedback).
1. Start-up the TV set, equipped with the Service SSB, and
enable the UART logging on the PC (see for settings 5.8
Fault Finding and Repair Tips 5.8.6 Logging).
2. The TV set will start-up automatically in the download
application if main TV software is not loaded.
3. Plug the prepared USB stick into the TV set, press cursor
Right to enter the list, and navigate to the autorun file in
the UART logging printout via the cursor keys on the
remote control. When the correct file is selected, press
OK.
4. Press cursor Down and OK to start the flashing of the
main TV software. Printouts like: L: 1-100%, V: 1-100%
and P: 1-100% should be visible now in the UART logging.
5. Wait until the message Operation successful! is displayed
and remove all inserted media. Restart the TV set

SSB identification
Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of a Service SSB is the same as the ordering
number of an initial factory SSB.

2010-Apr-02

When a picture is available


1. Mount the Service SSB into the TV set. After start-up,
normally the download application will appear on the
screen.
2. Download the latest main software (FUS) from the
www.p4c.philips.com website.
3. Create a folder upgrades in the root of a USB stick (size
> 50 MB) and save the autorun.upg file in this upgrades
folder. Note: it is possible to rename this file, e.g.
Q555_SW_version.upg, this in case there are more than
one autorun.upg files on your USB stick.
4. Plug the prepared USB stick into the TV set, and select the
autorun file in the displayed browser on the screen
5. Now the main TV software will be loaded automatically,
supported by a progress bar.
6. Set the correct display code via 062598-HOME-xxx,
where xxx is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).

A very important issue towards a repaired SSB from a Service


repair shop (SSB repair on component level) implies the reset
of the NVM on the SSB.
A repaired SSB in Service should get the Service Set type
00PF0000000000 and Production code 00000000000000.
Also the virgin bit is to be set. To set all this, you can use the
ComPair tool.

6.5.1

Service SSB delivered without main software


loaded

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Alignments
6.6.3

6. Set the correct display code via 062598-HOME-xxx,


where xxx is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).

6.7

Q552.1A LA

6.

EN 33

Use of repaired SSBs instead of new


Repaired SSBs on stock will obviously already contain main TV
software. This implies that only a main software upgrade is
required if you use a repaired SSB for board swap instead of
a new SSB.

Total Overview SAM modes


Table 6-8 SAM mode overview
Main Menu

Sub-menu 1

Sub-menu 2

Hardware Info

A. SW version

e.g. Q5521_0.33.0.0

Sub-menu 3

Display TV & Standby SW version and CTN serial


number

B. Standby processor version e.g. STDBY_42.42.0.0


C. Production code

Description

e.g. see type plate

Operation hours

Displays the accumulated total of operation hours.TV


switched on/off & every 0.5 hours is increase one

Errors

Displayed the most recent errors

Reset error buffer


Alignment

Clears all content in the error buffer


White point

Colour temperature

Normal
Warn

3 different modes of colour temperature can be selected

Cool
White point red

LCD White Point Alignment. For values,


see Table 6-4 White tone default setting 42" 1 until 65 White tone default setting 46"

White point green


White point blue
Ambilight

Select module
Brightness
Select matrix

Dealer options

TCON alignment

used when a new display code (after a SSB


exchange) is keyed-in and if you have alignment
values from production; see Table 6-6 TCON default
settings

Reset TCON alignment

used when a new display code (after a SSB


exchange) is keyed-in and if you do not have
alignment values from production

Virgin mode

Off/On

E-sticker

Off/On

Auto store mode

None

Select Virgin mode On/Off. TV starts up / does not


start up (once) with a language selection menu after
the mains switch is turned on for the first time (virgin
mode)
Select E-sticker On/Off (USPs on-screen)

PDC/VPS
TXT page
PDC/VPS/TXT

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2010-Apr-02

EN 34

6.

Q552.1A LA

Alignments

Main Menu

Sub-menu 1

Sub-menu 2

Sub-menu 3

Options

Digital broadcast

DVB

Off/On

Select DVB On/Off

DVB - T installation

Off/On or Country dependent

Select DVB T installation On/Off or by country

Digital features

Display

Video reproduction

Description

DVB - T light

Off/On

Select DVB T light On/Off

DVB - C

Off/On

Select DVB C On/Off

DVB - C installation

Off/On or Country dependent

Select DVB C installation On/Off or by country

DVB - C light

Off/On

Select DVB C light On/Off

DVB - S
Over the air download

Off/On
Off/On or Country dependent

Select DVB S On/Off


Select Over the air download On/Off or by country

8 days EPG

Off/On

Select 8 day EPG On/Off

Ethernet

Off/On

Select Ethernet On/Off

Wi-Fi

Off/On

Select Wi-Fi On/Off

DLNA

Off/On

Select DLNA On/Off

On-line service

On

On-line service is On

Videostore SD card slot

Off/On

Select Videostore SD card slot On/Off

Multiview

Off/On

Select Multiview On/Off

Internet software update

Off

Internet software update is Off

Screen

237 / LCD Sharp D3GA23 46"

Displayed the panel code & type model

LightGuide

Off/On

Select LightGuide On/Off

Display fans

Not present/Present

Select Display fans Present/Not present

Temperature sensor

No sensor/On backside/In display/ Sensor present Yes/No and in case Yes, where
On SSB

Temperature LUT

E-box & monitor

Off/On

Select E-box & monitor On/Off

Light sensor

Off/On

Select Light sensor On/Off

Light sensor type

0/1/2/3

Select Light sensor type form 0 to 3 (for difference


styling)

Super resolution

Off/On

Super resolution Off/On

Smart bit enhancement


Pixel Plus type

Off/On
Pixel Plus HD

Smart bit enhancement Off/On


Select type of picture improvement

N.A.

Perfect Pixel HD
Pixel Precise HD
Natural motion type

Perfect Natural Motion

Natural motion type selection

Ambilight

HD Natural Motion
None

Select type of Ambilight modules use

2 sided 3/3
2 sided 4/4
2 sided 5/5
2 sided 6/6
2 sided 7/7
3 sided 5/5/5
3 sided 6/6/6
3 sided 7/7/7
3 sided 6/9/6
Off/On

Ambilight sunset
Audio reproduction

Acoustic system

Source selection

EXT1/AV1 type

Ambilight sunset On/Off


Cabinet design used for setting dynamic audio parameters

SCART CVBS RGB LR


CVBS Y/C YPbPr LR

Select input source when connected with external


equipment

CVBS Y/C YPbPr HV LR


EXT2/AV2 type

SCART CVBS RGB LR


CVBS LR

Select input source when connected with external


equipment

YPbPr LR
None
EXT3/AV3 type

None
CVBS

Select input source when connected with external


equipment

CVBS LR
CVBS Y/C LR
YPbPr
YPbPr LR

Miscellaneous

SIDE I/O

YPbPr HV LR
Off/On

Select SIDE I/O On/Off

S-VIDEO (Y/C)

Off/On

Select S-VIDEO (Y/C) On/Off

HDMI 2

Off/On

Select HDMI 2 On/Off

HDMI 3

Off/On

Select HDMI 3 On/Off

HDMI side

Off/On

Select HDMI side On/Off

HDMI CEC Viewport 21:9

Off/On

Select HDMI CEC Viewport 21:9 On/Off

HDMI CEC OneUX seamless

Off/On

Select HDMI CEC OneUX seamless On/Off

Europe

Select Region/country

Region

AP-PAL-Multi
China
Australia
Latam
Russia
Tuner type

Select type of Tuner used

Hotel mode

2010-Apr-02

Off
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Hotel mode is Off

Alignments
Sub-menu 3

Q552.1A LA

6.

EN 35

Main Menu

Sub-menu 1

Sub-menu 2

Option numbers

Group 1

e.g. 00008.01793.15421.08192

The first line (group 1) indicates hardware options 1


to 4

Group 2

e.g. 44013.34315.00000.00000

The second line (group 2) indicates software options


5 to 8

Store

Description

Store after changing

Initialise NVM

N.A.

Store

Select Store in the SAM root menu after making any


changes
In case the display must be swapped for repair, you
can reset the Display operation hours to 0. So,
this one does keeps up the lifetime of the display itself (mainly to compensate the degeneration behaviour)

Operation hours display

Software maintenance

0003

Software events

Display

Display information is for development purposes

Clear
Test reboot
Test cold reboot
Hardware events

Test application crash


Display

Display information is for development purposes

Clear
Test setting

Digital info

Centre frequency: 774605208


QAM modulation: None

Display information is for development purposes

Symbol rate:
Original network ID: 0
Network ID: 0
Transport stream ID: 0
Service ID: 0
Hierarchical modulation: 0
Selected video PID: 0
Selected main audio PID: 0
Selected 2nd audio PID: 0
Install start frequency

000

Install start frequency from 0 MHz

Install end frequency

999

Install end frequency as 999 MHz

Digital only

Select Digital only or Digital + Analogue before installation

Default install frequency


Installation

Digital + Analogue
Development file ver- Development 1 file version
sions

Display parameters DISPT6.0.9.8


Acoustics
0.39.6.16

parameters

Display information is for development purposes

ACSTS

PQ - TV550 1.0.22.1
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM 5.0.2.4
Development 2 file version

12NC one zip software

Display information is for development purposes

Initial main software


NVM version Q55x1_0.3.1.0
Flash units software
Temp com file version none
Upload to USB

All
Channel list

To upload several settings from the TV to an USB


stick

Personal settings
Option codes
Alignments
Identification data
History list
Download from USB

All
Channel list

To download several settings from the USB stick to


the TV

Personal settings
Option codes
Alignments
Identification data
NVM editor

Type number

see type plate

AG code

see type plate

NVM editor; re key-in type number and production


code after SSB replacement

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2010-Apr-02

EN 36

7.

Q552.1A LA

Circuit Descriptions

7. Circuit Descriptions
7.1

Index of this chapter:


7.1 Introduction
7.2 Power Architecture
7.3 DC/DC Converters
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception
7.5 HDMI
7.6 Video and Audio Processing - PNX85500
7.7 Back-End
7.8 Ambilight
7.9 TCON

Introduction
The Q552.1A LA chassis is part of the TV550 platform and
comes with the following stylings: Da Vinci (series
xxPFL6xxx) and Matisse (series xxPFL8xx). The TV550
platform is the successor of the TV543 platform.

7.1.1

Implementation
Key components of this chassis are:
PNX85500 System-On-Chip (SOC) TV Processor
TX31XX Hybrid Tuner (DVB-T/C, analogue)
SII9x87 HDMI Switch
TPA312xD2PWP Class D Power Amplifier
LAN8710 Dual Port Gigabit Ethernet media access
controller.

Notes:
Only new circuits (circuits that are not published recently)
are described.
Figures can deviate slightly from the actual situation, due
to different set executions.
For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts). Where
necessary, you will find a separate drawing for clarification.

7.1.2

TV550 Architecture Overview


For details about the chassis block diagrams refer to chapter 9.
Block Diagrams. An overview of the TV550 architecture can be
found in Figure 7-1.

18770_244_100203.eps
100219

Figure 7-1 Architecture of TV550 platform - TCON integrated in display (xxPFL8xxx)

2010-Apr-02

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Circuit Descriptions

Q552.1A LA

7.

EN 37

18770_245_100203.eps
100219

Figure 7-2 Architecture of TV550 platform - TCON integrated on SSB (xxPFL6xxx)

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2010-Apr-02

EN 38

Q552.1A LA

Circuit Descriptions

SSB Cell Layout

1M95

DDR

1M99

FLASH

CA
LOW PROFILE

7.1.3

7.

ClassD

RJ45
Tuner
L

9187

OUT

Pr

Pb

HDMI 1.3

HDMI 1.3

HDMI 1.3

18990_200_100401.eps
100401

Figure 7-3 SSB layout cells (top view) TCON integrated in display (xxPFL8xxx)

DVB-S
TCON

Tuner
HDMI 1.3

HDMI 1.3

HDMI 1.3

VGA

18990_201_100401.eps
100401

Figure 7-4 SSB layout cells (top view) TCON integrated on SSB (xxPFL6xxx)

2010-Apr-02

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Circuit Descriptions
7.2

Q552.1A LA

7.

EN 39

Power Architecture
Refer to figure Figure 7-5 for the power architecture of this
platform.

18770_234_100127.eps
100127

Figure 7-5 Power Architecture TV550 platform


7.2.1

Power Supply Unit


All power supplies are a black box for Service. When defective,
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always
replace a defective fuse with one with the correct
specifications! This part is available in the regular market.
Consult the Philips Service web portal for the order codes of the
boards.

7.2.2

Output to the display; in case of


- IPB: High voltage to the LCD panel
- PSL and PSLS (LED-driver outputs)
- PSDL (high frequent) AC-current.

Diversity
The diversity in power supply units is mainly determined by the
diversity in displays. Table 7-1 Supply diversity lists the
different types of displays with its associated PSUs:

Important deltas with the TV543 platform are:


New power architecture for LED backlight (PSL, PSLS,
PSDL)
Boost-signal is now a PWM-signal + continuous variable.

Table 7-1 Supply diversity

The control signals are:


Standby
Lamp on/off
DIM (PWM) (not for PSDL)
Boost (PWM except for IPB)
Power-OK: indicates that the main converter is functioning
(feedback signal to the SSB).

CTN

Supplier

PSU

42PFL8605D/93

LGIT

PLDF-P975A

42PFL8605/98

LGIT

PLDJ-P977A

46PFL8605D/93

LGIT

PLDF-P975A

The following displays can be distinguished:


CCFL/EEFL backlight: power board is conventional IPB
LED backlight:
- side-view LED without scanning: PSL power board
- side-view LED with scanning: PSLS power board
- direct-view LED without 2D-dimming: PSL power board
- direct-view LED with 2D-dimming: PSDL power board.

In this manual, no detailed information is available because of


design protection issues.
The output voltages to the chassis are:
+3V3-STANDBY (standby-mode only)
+12V (on-mode)
+Vsnd (+24V) (audio power) (on-mode)
+24V (bolt-on power) (on-mode)

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PSL stands for Power Supply with integrated LED-drivers.


PSLS stands for a Power Supply with integrated LEDdrivers with added Scanning functionality (added
microcontroller).
2010-Apr-02

EN 40

7.2.3

7.

Circuit Descriptions

Q552.1A LA

PSDL stands for a Power Supply for Direct-view LED


backlight with 2D-dimming.

Connector overview

Table 7-2 Connector overview

Connector
no.

7.3

1311

1319

1316

1M95

1M09

1MP1

Descr. mains

1308

mains

disp.

disp.

to SSB to SSB Amb.

1M99

T-con

Pin

CN1

CN2

CN3

CN4

CN5

t.b.d.

t.b.d.

3V3std +12V

t.b.d.

t.b.d.

Stndby +12V

24Vb

+12V

GND1

GND1

GND1

n.c.

GND1

GND1

GND1

GND1

BL_ON _OFF

+12V

DIM

+12V

Boost

+12V

n.c.

+Vsnd

POK

10

GND_
SND

11

n.c.

12

CN6

CN7

CN8

24Vb

+12V

GND1

7.4

Front-End Analogue and DVB-T, DVB-C;


ISDB-T reception

7.4.1

European/China region

GND1

The Front-End for the European/China region consist of the


following key components:

DC/DC Converters
The on-board DC/DC converters deliver the following voltages
(depending on set execution):
+3V3-STANDBY, permanent voltage for the standby
controller, LED/IR receiver and controls; connector 1M95
pin 1
+12V, input from the power supply for TV550 common
(active mode); connector 1M95 pins 6, 7 and 8
+24V, input from the power supply for DVB-S2 (in active
mode); connector 1M09 pins 1 and 2
+1V1, core voltage supply for PNX85500; has to be started
up first and switched off last (diagram B03B)
+1V2, supply voltage for analogue blocks inside
PNX85500
+1V8, supply voltage for DDR2 (diagram B03B)
+2V5, supply voltage for analogue blocks inside
PNX85500 (see diagram B03E)
+3V3, general supply voltage (diagram B03E)
+5V, supply voltage for USB and CAM (diagram B03E)
+5V-TUN, supply voltage for tuner (diagram B03E)
+V-LNB, input voltage for LNB supply IC (item no. 7T50)
+5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)
+3V3-DVBS, clean voltage for silicon tuner and DVB-S2
channel decoder
+2V5-DVBS, clean voltage for DVB-S2 channel decoder
+1V-DVBS, core voltage for DVB-S2 channel decoder.

Hybrid Tuner
Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
(8 MHz) (China)
Bandpass filter
Amplifier
PNX85500 SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for this


region.

18770_235_100127.eps
100219

Figure 7-6 Front-End block diagram European/China region


7.4.2

Brazil region
The Front-End for the Brazil region consist of the following key
components:

A +12 V under-voltage detector (see diagram B03C) enables


the 12V to 3.3V and 12V to 5V DC/DC converters via the
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter
via the ENABLE-1V8 line. DETECT2 is the signal going to the
standby microcontroller and ENABLE-3V3n is the signal
coming from the standby microcontroller.

Diagram B03D contains the following linear stabilisers:


+2V5 stabiliser, built around item no. 7UCO
+5V-TUN stabiliser, built around items no. 7UA6 and 7UA7
+1V2 stabiliser, built around items no. 7UA3 and 7UA4.

Hybrid Tuner with integrated SAW filter and amplifier


External ISDB-T channel decoder covering the Brazilian
digital terrestrial TV standard
Bandpass filter
Amplifier
PNX85500 SoC TV with integrated analogue demodulator.

Below find a block diagram of the front-end application for this


region.

Diagram B08A contains the DVB-S2-related DC/DC


converters and -stabilisers:
a +24V under-voltage detection circuitry is built around
item no. 7T04

2010-Apr-02

the switching frequency of the 24 to 14...20V switched


mode converter is 350 kHz (item no. 7T03 and +V-LNB
lines)
the output signal on the +V-LNB line goes to the LNBH23Q
(item no. 7T50)
the LNBH23Q (item no. 7T50) sends a feedback signal via
the V0-CNTRL line
the switching frequency of the +5V-DVBS to +1-DVBS
switched mode converter is 900 kHz (item no. 7T00)
a delay line for the +2V5-DVBS and +1V-DVBS lines is
created with item no. 3T03 (R=10k) and 2T06 (C=100n)
a 3.3V to 2.5V linear stabiliser is built around item no. 7T01
a 5V to 3.3V linear stabiliser is built around item no. 7T02.

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Circuit Descriptions

7.6

Q552.1A LA

7.

EN 41

EDID stored in Sil9x87, therefore there are no EDID pins


on the SSB.

Video and Audio Processing - PNX85500


The PNX85500 is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:

18770_236_100127.eps
100219

Figure 7-7 Front-End block diagram Brazil region

7.5

HDMI
In this platform, the Silicon Image Sil9x87 HDMI multiplexer is
implemented. Refer to figure 7-8 HDMI input configuration for
the application.

New in this platform is the implementation of the Audio Return


Channel (ARC) (pin 14 on HDMI 1). The ARC in HDMI1.4
enables a TV, via a single HDMI cable, to send audio data
upstream to an A/V receiver or surround audio controller,
increasing user flexibility and eliminating the need for any
separate SPDIF audio connection.

Multi-standard digital video decoder (MPEG-2, H.264,


MPEG-4)
Integrated DVB-T/DVB-C channel decoder
Integrated CI+
Integrated motion accurate picture processing (MAPP2)
High definition ME/MC
2D LED backlight dimming option
Embedded HDMI HDCP keys
Extended colour gamut and colour booster
Integrated USB2.0 host controller
Improved MPEG artefact reduction compared with
PNX8543
Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions,


such as DVB-T channel decoding, MPEG-2/H.264 decode,
analogue video decode and HDMI reception, with advanced
back-end video picture improvements. It also includes next
generation Motion Accurate Picture Processing (MAPP2). The
MAPP2 technology provides state-of-the-art motion artifact
reduction with movie judder cancellation, motion sharpness
and vivid colour management. High flat panel screen
resolutions and refresh rates are supported with formats
including 1366 768 @ 100Hz/120Hz and 1920 1080 @
100Hz/120Hz. The combination of Ethernet, CI+ and H.264
supports new TV experiences with IPTV and VOD. On top of
that, optional support is available for 2D dimming in
combination with LED backlights for optimum contrast and
power savings up to 50%.
For a functional diagram of the PNX85500, refer
to Figure 7-9.

18770_243_100203.eps
100203

Figure 7-8 HDMI input configuration


The following multiplexers can be used:
Sil9187A (does not support Instaport technology for fast
switching between input signals)
Sil9287B (supports Instaport technology for fast
switching between input signals).
The hardware default I2C addresses are:
Sil9187A: 0xB0/0xB2 (random: software workaround)
Sil9287B: 0xB2 (fixed).
The Sil9x87 has the following specifications:
+5V detection mechanism
Stable clock detection mechanism
Integrated EDID
RT control
HPD control
Sync detection
TMDS output control
CEC control

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2010-Apr-02

EN 42

7.

Circuit Descriptions

Q552.1A LA

PNX85500x

MEMORY
CONTROLLER

TS input

DVB

MPEG
SYSTEM
PROCESSOR

CI/CA

TS out/in for
PCMCIA

PRIMARY
VIDEO
OUTPUT

LVDS

LVDS for
flat panel display
(single, dual or
quad channel)

DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
DECODER

CVBS, Y/C,
RGB

3D COMB
SECONDARY
VIDEO
OUTPUT

Low-IF

SSIF, LR

DIGITAL IF

MPEG/H.264
VIDEO
DECODER

VIDEO
ENCODER

analog CVBS

AUDIO DACS

analog audio

Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION

AUDIO DEMOD
AND DECODE

AUDIO IN

SPDIF

AUDIO DSP
AUDIO OUT
HDMI
RECEIVER

HDMI

450 MHz
AV-DSP
560 MHz
MIPS32
24KEf CPU

SYSTEM
CONTROLLER
(8051)

I 2S
SPDIF

DRAWING
ENGINE

DMA BLOCK

I2C

PWM GPIO

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet


Memory MAC
x8
Card

18770_241_100201.eps
100219

Figure 7-9 PNX85500 functional diagram

2010-Apr-02

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Circuit Descriptions
7.7

Q552.1A LA

7.

EN 43

Back-End
The following backlight types can be distinguished:
CCFL/EEFL backlight; applicable to the xxPFL54xx sets
LED backlight:
- side-view (edge) LED without scanning: PSL power
board; applicable to xxPFL76xx sets
- side-view (edge) LED with scanning: PSLS power board;
not applicable to this chassis
- direct-view LED with 0D-dimming: PSL power board;
applicable to xxPFL56xx sets
- direct-view LED with 2D-dimming: PSDL power board;
not applicable to this chassis.
Refer to section 7.2.2 Diversity for an in-depth explanation of
the different power boards that are used.

18770_242_100203.eps
100203

Figure 7-10 Backlight (xxPFL54xx, xxPFL56xx, xxPFL76xx sets)


application

7.8

Ambilight
In this chassis, only 2-sided Ambilight is implemented. Refer to
figure 7-11 Ambilight architecture.

MTK
or
PNX85500

1
M
5
9

Glue
logic

1
M
8
3

AmbiLight

1
M
8
4

1
M
8
3

AmbiLight

1
M
8
4

SSB
1M09
1M09

PSU

18770_209a_100202.eps
100202

Figure 7-11 Ambilight architecture


For an overview of the LED grouping per board, refer to figure
7-12 LED grouping per board.

back to
div. table

2010-Apr-02

EN 44

7.

Circuit Descriptions

Q552.1A LA

2 3B01-2 7

1 3B30-1 8

36

30

24

12

2B02

33p

2B00

15

18

7B20-2
74LVC2G17
+3V3
5

4
+
5
L
E
D

3B01-1

3B30-4

100R

SPI-CLOCK-BUF

220R
2B10

100p

SPI-CLOCK

6
L
E
D

6
L
E
D

33p

6
L
E
D

5
L
E
D

2B01

6
L
E
D

PWM-CLOCK-BUF

220R

100R

100p

PWM-CLOCK

7B20-1
74LVC2G17

6
L
E
D

100n

2B17

+3V3

18770_214_100126.eps
100126

Figure 7-15 Ambilight buffer


18770_210_100126.eps
100126

The temperature sensor is built around item no. 7B30 (diagram


AL1A) and indicates overtemperature of the board. Refer to
figure 7-16 Temperature sensor.

Figure 7-12 LED grouping per board


The communication between PNX85500, Complex
Programmable Logic Device (CPLD) and the Ambilight module
uses the SPI protocol; refer to figure 7-13 Communication
protocol outside LED board. Between the CPLD and the LED
driver, as extra line is mentioned:
Non-SPI signals that are required for the LED driver
Temperature sensor line.

3B34
+3V3

+3V3

100K RES

1K5 1%

6
3B39-3

7B30
5

3B39-2
2

FB40

1K5 1%

+3V3

4
2

RES

TEMP-SENSOR

LMV331IDCK

10K

10n
3004

10K

2B08

-T

3B11

10n
3B39-1

2B09

C P LD

PNX

1M 59

S P I + e x tra

1K5 1%

FB41

SPI

18770_211_100126.eps
100126

18770_215_100126.eps
100126

Figure 7-13 Communication protocol outside LED board

Figure 7-16 Temperature sensor

Refer to figure for an overview of the communication inside the


LED board.

The EEPROM (item no. 7B07; diagram AL1A) contains


alignment information about the mounted LEDs and is
programmed during the alignment process in production. Refer
to figure 7-17 EEPROM.

E x tra

SPI-DATA-IN-BUF

1M 83

SPI-CLOCK-BUF
7B07
M95010-WDW6

+3V3

EEPRO M

Tem p
sensor

2B20

SPI

1M 84

LE D
D river

5
7B06
74LVC1G32GW
1
SPI-CS

6
4

Te m p

SPI

+3V3
3

DATA-SWITCH

10K

VCC

(64K)
C
3B02-2

S
HOLD
W

7
7

10K

+3V3

GND
4

SPI

1
1 3B02-1 8

SPI

B uffer

SPI

100n

+3V3

18770_213_100126.eps
100219

SPI-DATA-RETURN

18770_216_100126.eps
100126

Figure 7-14 Communication protocol inside LED board


Figure 7-17 EEPROM

The buffer is built around item no. 7B20 (diagram AL1A) and
regenerates the clock signals. Refer to figure 7-15 Ambilight
buffer.

2010-Apr-02

The LED driver is built around item no. 7B26 (diagram AL1A)
and controls the LEDs. Refer to figure 7-18 LED driver.

back to
div. table

Circuit Descriptions

Q552.1A LA

7.

EN 45

+3V3
2B11
100n

VCC

3B00-1

8
150R
1K8

4 3B00-4 5
150R

PROG
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-IN
SPI-DATA-OUT

3
3B00-3

6
150R

LATCH

3B18
FB35

150R

3B21

22
25
32

3B22
10K

+3V3

FB20

2 3B00-2 7

31
24
26
3
1
2
23

12
13
28
29

100p

2B04-3

XERR
XHALF
XLAT

NC

GND
30

100p

2B04-4
4

100p

100p
2B04-1

2B04-2

150R

BLANK
GSCLK
IREF
MODE
SCLK
SIN
SOUT

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

0
1
2
3
4
5
6
7
OUT
8
9
10
11
12
13
14
15

PWM-R1
PWM-G1
PWM-B1
PWM-G3
PWM-R3
PWM-R2
PWM-G2
PWM-B2
PWM-B3
PWM-G4
PWM-R4
PWM-B4
PWM-B5
PWM-G5
PWM-R5
DATA-SWITCH
3B31

GND_HS
33

BLANK
PWM-CLOCK-BUF

27

7B26-1
TLC5946RHB

+3V3

2K0
7B26-2
TLC5946RHB
34
VIA
35
VIA VIA
36
VIA
37
38
39

42
41
40

18770_217_100126.eps
100126

Figure 7-18 LED driver


The Overvoltage Protection Circuit is built around item no.
7B50, 7B51, 7C20 and 7C22 (diagram AL1B). Refer to figure
7-19 Overvoltage Protection Circuit.

7B23-1
BC847BS(COL)
6

10K

8 3B07-1 1

+24V

1
10K

2 3B07-2 7

FB30

PWM-B1

3B35
7000
99-235/RSBB7C-A24/2D

10K

7004
99-235/RSBB7C-A24/2D

7003
99-235/RSBB7C-A24/2D

7002
99-235/RSBB7C-A24/2D

7001
99-235/RSBB7C-A24/2D

+24V

7005
99-235/RSBB7C-A24/2D

270R
3B36

7B23-2
BC847BS(COL)
3

BLUE

BLUE

BLUE

BLUE

6 5

BLUE

BLUE

270R

GREEN

GREEN

GREEN

GREEN

2 1

GREEN

GREEN

3B37

RED

RED

RED

RED

4 3

RED

RED

68R

4
10K

3 3B07-3 6

5 3B07-4 4

+24V

1 3B03-1 8
FB31

PWM-R1

2
+24V

1K5
3B03-2

1K5

7B25
BC847BW 3

2B03

2
10K

5 3B13-4 4

1K5

PWM-G1

1K5
3B03-4

100n

10K

3 3B13-3 6

3 3B03-3 6

FB32

18770_218_100126.eps
100126

Figure 7-19 Overvoltage Protection Circuit

7.9

TCON
This section describes the application with the TCON
integrated on the SSB.
For the basic application, refer to figure 7-20 TCON
architecture.

back to
div. table

2010-Apr-02

EN 46

7.

Circuit Descriptions

Q552.1A LA

EEPROM

LVDS

(10 bit)
Timing

Mini - LVDS

Controller
(TCON)

Gamma
Reference
Voltage

+3.3 V
+1.8 V

Source Drive IC

+16 V
+12 V

Power
Block

M ain P latform

VGH (+28 V)
VGL (-6 V)

Gate Drive IC

PNX8550

Control
Signals

TFT LCD Panel

TCO N
LC D P anel

SSB
18770_238_100127.eps
100402

Figure 7-20 TCON architecture


For the TCON block diagram, refer to figure 7-21 TCON block
diagram.

LVDS
Input

S p re a d
S p e c tru m

M in iLVDS
Output

T im in g C o n tro lle r IC

SDRAM

R 1 A ~E

LV D S
R e c e iv er

R 2C LK

ODC

DCA

(Over
Drive
Circuit)

(Dynamic
Contrast
Control)

R 2 A ~E

OPC
(Optimum
Power
Control)

R 1C LK

LV D S
R e c e iv er

D a ta
P a th
B lo c k
(L in e
B u ffer)

Form atter/S erializer

1 6 bit
M ini-LVDS
Transmitter

RLV P /N

M ini-LVDS
Transmitter

Right h alf
data

Gate D river
C trl S ign als

Ve rtic a l & H o rizo n ta l


Tim in g g e n e ra tio n
I2 C
S lav e

ROM

I2 C
M aster

Source D river
C trl S ign als

H s y n c/
Vsync
S S C L K (S p re a d Spectrum C lo c k)
DE

Control
Signal
Output

EEPROM
18770_239_100127.eps
100127

Figure 7-21 TCON block diagram


2010-Apr-02

back to
div. table

Circuit Descriptions

D C /D C
C o n tro lle r

7.

EN 47

Timing Control Function: generates control signals to


column drivers and row drivers (Source Enable - SOE,
Gate Enable - GOE, Gate Start Pulse - GSP).
For an overview of the TCON DC/DC converters, refer to figure
7-22 TCON DC/DC converters.

Notes to figure 7-21 TCON block diagram:


LVDS receiver: converts the data stream back into RGB
data and SYNC signals (Vsync, Hsync, Data Enable - DE)
ODC: Over Drive Circuit - to improve LC response
Data Path Block: the video RGB data input to data path
block is delayed to align the column driver start pulse with
the column driver data

+ 12V

Q552.1A LA

LGD

SHP

W h ere U sed

VGH

+2 8 V

+3 5 V

To G a te D riv e rs (G a te
H ig h Vo lta g e )

VGL

-6 V

-6 V

To G a te D riv e rs (G a te
L o w Vo lta g e )

Vcc

+3 V 3

+3 V 3

Tim in g C o n tro lle r IC


S u p p ly Vo lta g e

Vcc

+1 V 8

+1 V 2

Tim in g C o n tro lle r IC


S u p p ly Vo lta g e

Vre f

+1 6 V

+1 5 V 2

G a m m a R e fe renc e
Vo lta g e

Vdd

+1 6 V

+1 5 V 6

S o u rc e D riv e r S u p p ly
Vo lta g e
18770_240_100128.eps
100128

Figure 7-22 TCON DC/DC converters


7.9.1

TCON Programming
For LGD - TCONs, the EEPROM can be programmed via
ComPair (via I2C communication).
For Sharp - TCONs, the data can be flashed with a SPI
Programmer (via SPI communication). This device has to be
ordered separately via Philips.

7.9.2

TCON Alignment
The purpose of TCON alignment is to obtain equal voltages for
both positive and negative LC polarity. This is to avoid flicker
and image sticking. For alignment, see 6.3.3 TCON
Alignment.

back to
div. table

2010-Apr-02

EN 48

8.

IC Data Sheets

Q552.1A LA

8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as black boxes in the

8.1

electrical diagrams (with the exception of memory and logic


ICs).

Diagram USB Hub B01C, USB2513B (IC 7F25)

Block diagram
To Upstream
VBUS

Upstream
USB Data

To EEPROM or
SMBus Master

24 MHz
Crystal

SDA SCL

3.3 V

BusPower
Detect/
Vbus Pulse

Upstream
PHY

Regulator

Serial
Interface

PLL

Serial
Interface
Engine

Repeater

3.3 V

...

TT
#1

Regulator

Controller

TT
#x

Port
Controller

CRFILT

Routing & Port Re-Ordering Logic

Port #1
PHY#1

OC Sense
Switch Driver/
LED Drivers

...

Port #x
OC Sense
Switch Driver/
LED Drivers

PHY#x

USB Data OC
Port
Downstream Sense Power
Switch/
LED
Drivers

OC
USB Data
Port
Downstream Sense Power
Switch/
LED
Drivers

The x indicates the number of available downstream ports: 2, 3, 4, or 7.

NC

NC

NC

21

19

SCL / SMBCLK / CFG_SEL[0]

24

20

HS_IND / CFG_SEL[1]

25

VDD33

RESET_N

26

SDA / SMBDATA / NON_REM[1]

VBUS_DET

27

Pinning information

22

The LED port indicators only apply to USB2513i.

23

SUSP_IND / LOCAL_PWR / NON_REM[0]

28

18

NC

VDD33

29

17

OCS_N[2]

USBDM_UP

30

16

PRTPWR[2] / BC_EN[2]*

USBDP_UP

31

15

VDD33

XTALOUT

32

14

CRFILT

XTALIN / CLKIN

33

13

OCS_N[1]

PLLFILT

34

12

PRTPWR[1] / BC_EN[1]*

RBIAS

35

11

TEST

VDD33

36

10

VDD33

SMSC
USB2512/12A/12B
USB2512i/12Ai/12Bi
(Top View QFN-36)

6
NC

5
VDD33

NC

4
USBDP_DN[2]

3
USBDM_DN[2]

2
USBDP_DN[1]

NC

1
USBDM_DN[1]

Ground Pad
(must be connected to VSS)

NC

Note :

Indicates pins on the bottom of the device.

18770_301_100217.eps
100217

Figure 8-1 Internal block diagram and pin configuration


2010-Apr-02

back to
div. table

IC Data Sheets
8.2

Q552.1A LA

8.

EN 49

Diagram Temp Sensor + Headphone B01J, LM75BDP (IC 7FD1)

Block diagram
VCC

LM75B
BIAS
REFERENCE

POINTER
REGISTER

CONFIGURATION
REGISTER

BAND GAP
TEMP SENSOR

COUNTER

TEMPERATURE
REGISTER

TIMER

TOS
REGISTER

COMPARATOR/
INTERRUPT

THYST
REGISTER

11-BIT
SIGMA-DELTA
A-to-D
CONVERTER

OSCILLATOR

POWER-ON
RESET

OS

LOGIC CONTROL AND INTERFACE

A2

A1

A0

SCL SDA

GND

Pinning information

SDA

VCC

SCL

A0

A1

A2

OS

GND

LM75BDP

18770_300_100217.eps
100217

Figure 8-2 Pin configuration

back to
div. table

2010-Apr-02

EN 50
8.3

8.

IC Data Sheets

Q552.1A LA

Diagram PNX NandFlash - Conditional Access B02A, PNX85500 (IC7S00)

Block diagram
PNX8550x

MEMORY
CONTROLLER

TS input

MPEG
SYSTEM
PROCESSOR

CI/CA

TS out/in for
PCMCIA

PRIMARY
VIDEO
OUTPUT

LVDS

LVDS for
flat panel display
(single, dual or
quad channel)

DVB-T/C
channel decoder

DVB

AV-PIP
SUB-PICTURE
VIDEO
DECODER

CVBS, Y/C,
RGB

3D COMB
SECONDARY
VIDEO
OUTPUT

Low-IF

MULTISTANDARD
VIDEO
DECODER

DIGITAL IF

Direct-IF

SPDIF

AUDIO IN

HDMI

HDMI
RECEIVER

analog CVBS

AUDIO DACS

analog audio

analog Y/C

Motion-accurate
pixel processing
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION

AUDIO DEMOD
AND DECODE

SSIF, LR

VIDEO
ENCODER

AUDIO DSP
AUDIO OUT
450 MHz
AV-DSP
500 MHz
MIPS32
24KEf CPU

SYSTEM
CONTROLLER
(8051)

I2S
SPDIF

DRAWING
ENGINE
Scatter/Gather
TS Demux

I2C

PWM Px_x

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet


Memory MAC
x 10
Card

Pinning information
ball A1
index area

PNX8550xE
2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Transparent top view
18770_308_100217.eps
100217

Figure 8-3 Internal block diagram and pin configuration

2010-Apr-02

back to
div. table

IC Data Sheets
8.4

Q552.1A LA

8.

EN 51

Diagram Audio B03A, TPA3120D2PWP (IC7D10)

Block diagram
TPA3120D2
1 F

0.22 F
LIN

BSR

RIN

ROUT

1 F

22 H

0.68 F

PGNDR

0.68 F

PGNDL

1 F
BYPASS
AGND

470 F

LOUT
22 H

BSL

470 F

0.22 F

PVCCL
AVCC
PVCCR

VCLAMP
Shutdown
Control

SD

1 F

MUTE

GAIN0
GAIN1

Pinning information

PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR

Control

PWP (TSSOP) PACKAGE


(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
I_18020_142.eps
100402

Figure 8-4 Internal block diagram and pin configuration

back to
div. table

2010-Apr-02

EN 52
8.5

8.

Q552.1A LA

IC Data Sheets

Diagram DC/DC B03B, TPS53126PW (IC7U03)

Block diagram

Pinning information
VBST1

28

NC

27

LL1

EN1

26

DRVL1
PGND1

DRVH1

25

24

TRIP1

NC

23

VIN

22

VREG5

GND

TEST1

NC

TPS53124

VO1
VFB1

21

V5FILT

20

TEST2
TRIP2

VFB2

10

19

VO2

11

18

PGND2

EN2

12

17

DRVL2

NC

13

16

LL2

VBST2

14

15

DRVH2

18250_300_090319.eps
100402

Figure 8-5 Internal block diagram and pin configuration

2010-Apr-02

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div. table

IC Data Sheets
8.6

Q552.1A LA

8.

EN 53

Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

Block diagram

Pinning information

DFN8 (4 4)

PowerSO-8
I_18010_083.eps
100402

Figure 8-6 Internal block diagram and pin configuration

back to
div. table

2010-Apr-02

EN 54
8.7

8.

Q552.1A LA

IC Data Sheets

Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

Block diagram

LD1117DT

Pinning information

DPAK

F_15710_166.eps
100402

Figure 8-7 Internal block diagram and pin configuration

2010-Apr-02

back to
div. table

IC Data Sheets

8.

EN 55

Diagram Ethernet + Service B04C, LAN8710A-EZKH (IC 7E10)

Block diagram
MODE0
MODE1
MODE2
nRST

MODE Control

AutoNegotiation

10M Tx
Logic

Reset
Control

SMI

RMIISEL

HP Auto-MDIX

10M
Transmitter

TXP / TXN

Transmit Section
100M Tx
Logic

Management
Control

RXP / RXN

100M
Transmitter
MDIX
Control

TXD[0:3]
TXEN
TXER
TXCLK

CRS
COL/CRS_DV

RMII / MII Logic

RXD[0:3]
RXDV
RXER
RXCLK

100M Rx
Logic

DSP System:
Clock
Data Recovery
Equalizer

PLL

Analog-toDigital

Interrupt
Generator

nINT

100M PLL

Receive Section

LED Circuitry
10M Rx
Logic

Squelch &
Filters
10M PLL

MDC
MDIO

XTAL1/CLKIN
XTAL2

LED1
LED2

Central
Bias

RBIAS

PHY
Address
Latches

PHYAD[0:2]

TXP

TXN

VDD1A

RXDV

TXD3

27

26

25

RXN
30

29

RXP

28

RBIAS
32

31

Pinning information

VDD2A

24

TXD2

LED2/nINTSEL

23

TXD1

LED1/REGOFF

22

TXD0

21

TXEN

20

TXCLK

19

nRST

18

nINT/TXER/TXD4

17

MDC

13

14

15

16

CRS

COL/CRS_DV/MODE2

MDIO

VSS
12

VDDIO

RXD3/PHYAD2

RXER/RXD4/PHYAD0

11

RXD0/MDE0

VDDCR
RXCLK/PHYAD1

10

RXD1/MODE1

XTAL2
XTAL1/CLKIN

SMSC
LAN8710/LAN8710i
32 PIN QFN
(Top View)

RXD2/RMIISEL

8.8

Q552.1A LA

18770_302_100217.eps
100217

Figure 8-8 Internal block diagram and pin configuration

back to
div. table

2010-Apr-02

EN 56
8.9

8.

Q552.1A LA

IC Data Sheets

Diagram HDMI B04D, SII9287B (IC 7EC1)

Block diagram

Pinning information

18770_303_100217.eps
100217

Figure 8-9 Internal block diagram and pin configuration

2010-Apr-02

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div. table

IC Data Sheets

Q552.1A LA

8.

EN 57

8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

Block diagram
VDD 8

VDD/2
2

IN 1

BYPASS

IN 2

SHUTDOWN

VO1 1

VO2 7

Bias
Control

Pinning information
D OR DGN PACKAGE
(TOP VIEW)

VO1
IN1
BYPASS
GND

VDD
VO2
IN2
SHUTDOWN
18770_309_100217.eps
100217

Figure 8-10 Internal block diagram and pin configuration

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div. table

2010-Apr-02

EN 58

8.

Q552.1A LA

IC Data Sheets

Personal Notes:

10000_012_090121.eps
090121

2010-Apr-02

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div. table

Block Diagrams

Q552.1A LA

9.

EN 59

9. Block Diagrams
9-1 Wiring diagram Matisse 42" - 46"
WIRING DIAGRAM 42"- 46" MATISSE

8M83
8M09

Board Level Repair

8G50

Component Level Repair


Only For Authorized Workshop

TO BACKLIGHT

8G51

8M59

25P

41P

1M84

1G50

51P

(1174)

1G51

23P

(1150)

USB

9P

1M99

CONDITIONAL ACCESS

11P

1M95

ETHER
NET

HDMI

HDMI

HDMI

VGA

2P3

1308

AL

8735

J1

SPDIF

(1005)

HDMI

TUNER

MAIN POWER SUPPLY


42 PLDF-P975A B
46 PLDG-P977A B

AL

3P

KEYBOARD CONTROL
(1114)

8M95

(1174)

1M59

SSB

B
8M99

AMBILIGHT MODULE 24 LED

1M09
4P

11P

4P

1M95

12P

4P

11P

8P

1735

1M09

9P

1316

AMBILIGHT MODULE 24 LED

1M20
1319

1M99

25P

1M83

8M20

2P3

LCD DISPLAY
(1004)

LOADSPEAKER RIGHT

LOADSPEAKER LEFT
(5215)

TCON

8191

MAINS CORD

(5215)

25P

TO DISPLAY

+ -

+ -

TO DISPLAY

1M83

1311

8311
MAINS
SWITCH
(8311)

1M59 (B13)
15. AMBI-TEMP
1. AMBI-SPI-CLK-OU
16. GND
2. AMBI-SPI-SDO-OUT
17. GND
3. AMBI-SPI-SDI-OUT-GI
18. GND
4. GND
19. GND
5. AMBI-PWM-CLK_B2
20. GND
6. V-AMBI
21. +24V
7. AMBI-SPI-CS-OUTn_R2
22. +24V
8. AMBI-LATCH1_G2
23. +24V
9. GND
24. +24V
10. AMBI-PROG_B1
25. +24V
11. AMBI-BLANK_R1
12. V-AMBI
13. AMBI-LATCH2_DIS
14. AMBI-SPI-CS-EXTLAMPSn

1M38 (AL1A)
1. +24V
2. +24V
3. +24V
4. +24V
5. +24V
6. GND
7. GND
8. GND
9. GND
10. GND
11. TEMP-SENSOR
12. N.C.
13. N.C.

14. +3V3
15. BLANK
16. PROG
17. GND
18. LATCH
19. SPI-CS
20. +3V3
21. PWM-CLOCK
22. GND
23. SPI-DATA-RETURN
24. SPI-DATA-IN
25. SPI-CLOCK

1M48 (AL2A)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
3. SPI-DATA-RETURN
4. GND
5. PWM-CLOCK-BUF
6. +3V3
7. SPI-CS
8. LATCH
9. GND
10. PROG
11. BLANK
12. +3V3
13. N.C.

14. N.C.
15. TEMP-SENSOR
16. GND
17. GND
18. GND
19. GND
20. GND
21. +24V
22. +24V
23. +24V
24. +24V
25. +24V

J2

J1

3P

8P

IR / LED BOARD
(1112)

1M95 (B03C)

1M99 (B03C)

1M20 (B09A)

1735 (B03A)

1. +3V3-STANDBY
2. STANDBY
3. GND
4. GND
5. GND
6. +12V
7. +12V
8. +12V
9. +24V-AUDIO-POWER
10. GND-AUDIO
11. MAINS-OK

1.
2.
3.
4.
5.
6.
7.
8.
9.

1.
2.
3.
4.
5.
6.
7.
8.

1.
2.
3.
4.

+12VD
+12VD
GND
GND
LAMP-ON
BACKLIGHT-PWM_BL-VS
BACKLIGHT-BOOST
BACKLIGHT-PWM-ANA-DISP
POWER-OK

LIGHT-SENSOR
GND
RC
LED-2
+3V3-STANDBY
LED-1
KEYBOARD
+5V

LEFT-SPEAKER
GND-AUDIO
GND-AUDIO
RIGHT-SPEAKER

1M09 (B09)
1.
2.
3.
4.

+24V
+24V
GND
GND

1KA1 (B14E)
1. GND
|
11. VLS_15V6
12. VLS_15V6
|
33. VCC_3V3
34. VCC_3V3
|
78. VGH_25V
79. VGL_6V
80. GND

1KA2 (B14E)
1. GND
|
11. VLS_15V6
12. VLS_15V6
|
33. VCC_3V3
34. VCC_3V3
|
78. VGH_25V
79. VGL_6V
80. GND
18990_400_100330.eps
100330

2010-Apr-02 back to

div. table

Block Diagrams

Q552.1A LA

9.

EN 60

9-2 Block Diagram Video


VIDEO
B02 PNX85500

B01A COMMON INTERFACE

B06B VIDEO OUT - LVDS


1G50
1

B02A VIDEO STREAM

51
52

CONDITIONAL
ACCESS

SDO
SCS

PX1

53

7KQB
M25P32

42

FLASH

50
L_LV

13
GMA

N.C.

1G51
51

TIMING
CONTROL

QUAD LVDS
1920x1080
100/120HZ

1
1KA2
81

REF
VOLTAGE
GEN

59
GMA

50
I2C

2F78

6 3F79-4

AE12

PNX-IF-P

BANDPASS
FILTER

AF12

PNX-IF-N

TO DISPLAY
(TCON ON DISPLAY)
PX4

90

IF_AGC

DRX2DRX1+

89
87

DRX1DRX0+

86
RXD
84

DRXC-

80

10

AVI-B

AD13

HDMI
SWITCH

ARX2+

23

ARX2ARX1+

22
20

ARX1ARX0+

19
RXA
17

EXT 2

11

Pb

AC14

AV4-PR

AE14

AV4-Y

R26
R25

B01I VGA

12

ARXC-

13

G-VGA
B-VGA
H-SYNC-VGA

10

R-VGA

15

14

AI13
XIO_D

11

Only 8000 Serie

3
13
14

AF16 VGA_R
AD16
VGA_G
AE16
VGA_B
AB18
HSYNC_IN
AC18
VSYNC_IN

V-SYNC-VGA

19
18

1
2

HDMI 2
CONNECTOR

1E08

BRX2+

42

BRX2BRX1+

41
39

BRX1BRX0+

39
RXB
36

BRXC+

33

12

BRXC-

32

EXT 3

B05A

1
2
19
18

HDMI 1
CONNECTOR

72

CRX2CRX1+

71
69

CRX1CRX0+

68
66

9
10

CRX0-

65

CRXC+

63

12

CRXC-

62

USB-DM1
USB-DP1

D(0-7)
AV3-Y

AE15

1ECB
1

AC12

C-SVHS

AF13

RXC

HDMIA-RXC+
HDMIA-RXC-

TX2_P 56
TX2_N 57

HDMIA-RX2+

HDMIA-RX0+
HDMIA-RX0HDMIA-RX1+
HDMIA-RX1HDMIA-RX23S0W

*6000 Serie mux SIL9187 - non Instaport


8000 Serie mux SIL9287 - Instaport

+3V3

SIDE USB
CONNECTOR

+3V3

7B00
*EDE1116AGBG
EDE1108AGBG

SDRAM
128MB

Y_G1

A1 E2

PB_B1

7B02
*EDE1116AEBG
EDE1108AGBG

SDRAM
128MB

A1 E2

7B03
EDE1108AGBG

SDRAM
128MB

A1 E2

7B01
EDE1108AGBG

SDRAM
128MB

A1 E2
DDR2-A(0-13)

A
ATV_CVBS_Y3

+1V8
DDR2-VREF-DDR

CR
6000 Serie 256MB

TXC_P 62
TXC_N 63
TX0_P 60
TX0_N 61
TX1_P 58
TXA_N 59

6000 Serie
12,37

SVHS IN 5
2

Y-SVHS

2
3

DDR2-D(0-31)

PR_R_C1

VREF_1
VREF_2

B02C HDMI_DV
CRX2+

4
6
7

VIDEO

AD15

1P02
1

9F20

DDR

VDDL
VREF

1P03

SIDE USB
CONNECTOR

*6000 Serie 256MB


8000 Serie 512MB

B04B ANALOGUE EXTERNALS B

35

9F21

DQ

AC15

+5V-USB1
1P07
1

NAND
FLASH

XIO-D(00-07)

B02B MEMORY

VGA
CONNECTOR

VCC33

2
3

8000 Serie

7F20
*NAND02GW3B2DN6F
NAND04GW3B2DN6F

VCC

16

BRX0-

USB-DM2
USB-DP2

B01B FLASH

1E05

ARX0-

9
10

9F25

256MB
512MB

ARXC+

4
6
7

9F26

USB-DM
USB-DP

AI33

AD14 AI23

AV4-PB

9
10

9,27,64

USB_DN
USB_DP

AV1_B

B02A FLASH
15

Pr

+3V3-HDMI

+5V-USB2
1P08
1

AV1_G

1E02

19
18

HDMI 3
CONNECTOR

Pb

1
2

1P04

AE13

B02E CONROL

AV1_R

D(24-31)

81

12

AV1-G

2
1

SSB 3104 313 6400*

VDDL
VREF

83

14
Y

CS(1U-12U)

B01C USB HUB

D(16-23)

DRX0DRXC+

AC13

LEVEL
SHIFTER

VDDL
VREF

9
10

EXT 1

AV1-R

19
13

SSB 3104 313 6364*

PNX85500

18

+VCC

PX4

40

TO DISPLAY
(TCON ON SSB)

DRX2+

1
2
19
18

24
20

3
2

1E01
Pr

1P05

+VDD

AD12

B04A ANALOGUE EXTERNALS A

7EC1
*SII9187ACNU
SII9287BCNU

4
6
7

7KUE
MAX17079GTL

4
PNX-IF-AGC

B04D HDMI

HDMI SIDE
CONNECTOR

B14D MPD

TO TCON SSB

+VDISP

4
6
7

25

TUNER_P
TUNER_N

13

PX3

CS(1-12)

SELECT-SAW
B02E
CONTROL

B01H HDMI

R_LV

PX3

AGC AMPLIFIER 7 3F79-1

OUT
4 IN
AGC CONTROL

SAW 36MHZ17
7F70

MAIN HYBRID
TUNER

40

B02I ANALOG VIDEO

VCC

3 2

48

VDDL
VREF

TUN-IF-N

11

2F74

D(8-15)

IF-OUT2

RF IN

5F73
5F70

IF-OUT1

TUN-IF-P

10

1F75

1
2F90

3 2

1T01
TH2603

49

50

7F75
UPC3221GV

B01F HDMI & CI

7KQA
ISL24837IRZ

41

MDI

TO DISPLAY
(TCON ON SSB)

13

PX2

MD0

CA-MDI(0-7)

36

+VCC

TO TCON SSB

+3V3

CA-MDO(0-7)

41
37

+VDD

SCK
TO DISPLAY
(TCON ON DISPLAY)
PX2

BUFFER

58

VOM & FLASH


SPI

PX1
7F01
74LVC245APW
20

MDO(0-7)

7KAA
UPD809900F

B02F LVDS

68P

PCMCIA

B14C P GAMMA &

+5VCA

18

B14E MINI LVDS (SHARP)


1KA1
81

7S00
PNX85507EB

1P00
17

B14A TCON CONTROL (SHARP)

A2
V1

8000 Serie 512MB

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

W25
RXC_B_N
W26
RXC_B_P
V25
RX0_B_N
V26
RX0_B_P
U25
RX1_B_N
U26
RX1_B_P
T25
RX2_B_N
T26
RX2_B_P
W24
RREF
18990_402_100331.eps
100331

2010-Apr-02 back to

div. table

Block Diagrams

Q552.1A LA

9.

EN 61

9-3 Block Diagram Audio


AUDIO
B02 PNX85500

B01A COMMON INTERFACE

B02D CLASS-D

B03A AUDIO

7S00
PNX85507EB
B02A VIDEO STREAM

B02D AUDIO
7D10
TPA3123D2PWP
PVCC_L
7S05
LM324P

1P00
17

+5VCA

18

ADAC_1

51
52

14

+AUDIO-L

OUT-L

IN-L

ADAC_2

ADAC(2)

AE7

10

-AUDIO-R

MDO(0-7)

CA-MDO(0-7)

BUFFER

+24V-AUDIO-POWER
1735
1

LEFT-SPEAKER

22

A-STBY

A-PLOP

MD0

CA-MDI(0-7)

B03H STANDBY

MDI

PO_7

A-PLOP

B04E
AC19

2
SPEAKER L
3

IN-R

7D15
CONDITIONAL
ACCESS

5D07
10,12 5D08
1,3

CLASS D
POWER
AMPLIFIER

+3V3

68P

PCMCIA

7F01
74LVC245APW
20

12

ADAC(1)

AD7

PVCC_R

OUT-R

AUDIO-MUTE-UP

15

RIGHT-SPEAKER

4
SPEAKER R

SD

1D38
1

MUTE
5D03

DETECT2
B02G
MAINS-OK
B03C

B01F HDMI & CI

7F75
UPC3221GV

+5V-TUN-PIN
1T01
TH2603

IF-OUT2

11

5F73

TUN-IF-P
TUN-IF-N

1F75

AGC AMPLIFIER 7 3F79-1

2F78

6 3F79-4

BANDPASS
FILTER

PNX-IF-P

AE12

PNX-IF-N

AF12

OUT
4 IN
AGC CONTROL

SAW 36MHZ17

7EE0-1

7EE0-2

7D03
STANDBY &
PROTECTION

B04E HEADPHONE

B02I ANALOG VIDEO


TUNER_P

PO_6

AD1

B04A

7EE1
TPA6111A2DGN

SELECT-SAW

B02E
CONTROL

B04D

PNX-IF-AGC

AD12

IF_AGC

HEADPHONE
AMPLIFIER

B04A

HDMI

ANALOGUE EXTERNALS A

B02D

PNX85500: AUDIO

ADAC3

7EC1
*SII9187ACNU
SII9287BCNU

DRX2+

90

AUDIO-IN1-L

DRX2DRX1+

89
87

AE10 AIN1_L

AUDIO-IN1-R

AF10

DRX1DRX0+

86
RXD
84

ARX2+

23

ARX2ARX1+

22
20

1
2

VDD

+3V3

HEADPHONE
OUT 3.5mm

ARX1ARX0+

19
RXA
17

9
10

ARX0-

16

ARXC+

14

12

ARXC-

13

BRX2+

42

BRX2BRX1+

41
39

BRX1BRX0+

39
RXB
36
35

BRXC+

33

12

BRXC-

32

AUDIO-IN3-L

AE9

AUDIO-IN3-R

AF9

AUDIO-IN4-L

AD9

AUDIO-IN4-R

AC9

SPDIF-OUT

SEL-HDMI-ARC

62
63

HDMIA-RXC+
HDMIA-RXC-

60

HDMIA-RX0+

61
58

HDMIA-RX0HDMIA-RX1+

CRX1CRX0+

68
66

59
56

HDMIA-RX2+

57

HDMIA-RX2-

62

HDMIA-RX1-

+3V3
5EC2

9F21

USB-DM1
USB-DP1

2
3
4

SIDE USB
CONNECTOR

6000 Serie

12,37

+3V3

AIN4_L
*6000 Serie 256MB
8000 Serie 512MB

AIN4_R

AF5

B05A DDR

SPDIF_OUT

AF18

DDR2-D(0-31)

DQ

P0_4

W24

7B00
*EDE1116AGBG
EDE1108AGBG

SDRAM
128MB

W25
RXC_B_N
W26
RXC_B_P
V25
RX0_B_N
V26
RX0_B_P
U25
RX1_B_N
U26
RX1_B_P
T25
RX2_B_N
T26
RX2_B_P
3S0W

ARC-eHDMI+

SIDE USB
CONNECTOR

8000 Serie

256MB
512MB

AIN3_R

B02G STANDBY

71
69

CRXC-

+5V-USB1
1P07
1

NAND
FLASH

XIO-D(00-07)

2
3

72

12

XIO_D

AIN3_L

B02B MEMORY
SPDIF-OUT-PNX

CRX2CRX1+

63

USB-DM2
USB-DP2

+3V3
7S09
2
3 &
1

CRX2+

CRXC+

9F25

B01B FLASH

B02c HDMI_DV

RXC

9F26

USB-DM
USB-DP

VCC

65

R25

9F20

CRX0-

R26

1E09

DIGITAL
AUDIO
OUT

1P02

9
10

USB_DN
USB_DP

AIN2_R

7F20
*NAND02GW3B2DN6F
NAND04GW3B2DN6F

1E07

BRX0-

AIN2_L

AC10

3 2

AD10

AUDIO-IN2-R

AUDIO-IN2-L

1E08

VCC33

9
10

+5V-USB2
1P08
1

B04B ANALOGUE EXTERNALS B

AUDIO IN
L+R
9,27,64

B01C USB HUB

B02A FLASH

1P03

19
18

1
2
19
18

HDMI
SWITCH

1
2

IN-2

1E02

VGA (OR DVI)


AUDIO

19
18

AMP2

3 2

80

14

DRXC-

+3V3-HDMI

HDMI 1
CONNECTOR

VO_2

A1 E2

7B02
*EDE1116AEBG
EDE1108AGBG

SDRAM
128MB

A1 E2

7B03
EDE1108AGBG

SDRAM
128MB

A1 E2

7B01
EDE1108AGBG

SDRAM
128MB
VDDL
VREF

12

4
6
7

IN-1

AMP1

B02E CONROL

VDDL
VREF

81

PNX85500

AIN1_R

D(16-23)

83

Only 8000 Serie

HDMI 2
CONNECTOR

VDDL
VREF

DRX0DRXC+

4
6
7

ADAC(4)

VDDL
VREF

9
10

1P04

HDMI 3
CONNECTOR

1E01

4
6
7

AD6

D(0-7)

1
2
19
18

HDMI SIDE
CONNECTOR

VO_1

ADAC(3)

AF7

1328

SHUTDOWN

1
ADAC4

1P05

4
6
7

SUBWOOFER
(RES)

B03A

A-PLOP

RESET-AUDIO

D(8-15)

B01H

TUNER_N

HDMI

B01J TEMP SENSOR + HEADPHONE

VCC

2F74

7F70

MAIN HYBRID
TUNER

A-STBY

D(24-31)

RF IN

10

5F70

IF-OUT1

2F90

7D03
MAIN SWITCH
DETECT

A1 E2
DDR2-A(0-13)

+1V8
DDR2-VREF-DDR
*6000 Serie 256MB

RREF
VREF_1
VREF_2

eHDMI+

*6000 Serie mux SIL9187 - non Instaport


8000 Serie mux SIL9287 - Instaport

A2
V1

8000 Serie 512MB

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3
18990_403_100331.eps
100331

2010-Apr-02 back to

div. table

Block Diagrams

Q552.1A LA

9.

EN 62

9-4 Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS
B01A

B02A

COMMON INTERFACE

B06C

PNX85500

AMBILIGHT
7GA0
XC9572XL

7S00
PNX85507EB

AMBI-SPI-CLK-OUT

27

AMBI-SPI-SDO-OUT

23
29

AMBI-SPI-SDI-OUT_G1
AMBI-PWM-CLK_B2

30

AMBI-SPI-CS-OUTn_R2

3
5
7

31

AMBI-LATCH1_G2

19
20
28

AMBI-PROG_B1
AMBI-BLANK_R1
AMBI-LATCH2_DIS

10
11
13

21
32

AMBI-SPI-CS-EXTLAMPSn
AMBI-TEMP

14

SENSE+1V1

B05A

26

B03B

SENSE+1V2

VIO

DDR
DDR2-D(0-31)

DQ

7B00
*EDE1116AGBG
EDE1108AGBG

7F20
*NAND02GW3B2DN6F
NAND04GW3B2DN6F

+3V3

7B02
*EDE1116AEBG
EDE1108AGBG

SDRAM
128MB

SDRAM
128MB

F8 E8

F8 E8

7B03
EDE1108AGBG

SDRAM
128MB

F8 E8

7B01
EDE1108AGBG

SDRAM
128MB

F8 E8
DDR2-A(0-13)

A
DDR-CLK_N
DDR-CLK_P
*6000 Serie

ETHERNET

SDCD
SDWP

ETH-RXCLK

AA3

20

ETH-TXCLK

AA2

TXCLK
RXCLK

BACKLIGHT-PWM
PXCLK54

B02A

RESET-SYSTEMn
PNX-SPI-CS-AMBIn
PNX-SPI-CS-BLn
USB-DM
USB-DP

B04V

ETHERNET
CONNECTOR
RJ45

USB HUB

B01F
B13
B06C
B01K
B06E
B01K

B13
B02G
B06D B13
B02G B02G

+5V-USB2
1P08
1
1

ETH-RXD
ETH-TXD

SELECT-SAW

U23

U23
GPI0_11
AC5
CLK_54_OUT
AE4
RESET_SYS
W23
GPI0_6
V22
GPI0_7
R26
USB_DN
R25
USB_DP

7E10
LAN8710A-EZK

8000 Serie

B01C

PNX85500: MIPS

9F26

USB-DM2
USB-DP2

9F25

B03C

DVBS CONNECTOR BOARD

GPI0_3

DC / DC

ETHERNET + SERVICE

SIDE USB
CONNECTOR

8000 Serie

+5V-USB1
1P07
1

Y23

RXD1-MIPS

Y24

TXD1-MIPS

3
1

UART
SERVICE
CONNECTOR

1E06
GPI0_2

2
3

3 2

GPI0_11

B02E ETHERNET

ETHERNET + SERVICE

B02E

9F21

USB-DM1
USB-DP1

9F20

CONNECTORS

2
3

3 2

B02E CONTROL

*6000 Serie 256MB


8000 Serie 512MB

CLK_N
CLK_P

XIO-D(00-07)

B09A
B14F

15

B03D

D(24-31)

XIO_D

XIO-D(00-15)

256MB
512MB

B04C

TO AMBILIGHT
MODULE

VCCIO

B02H POWER
AF1
VDD_1V1
AA15
VDDA_1V2

XIO_A

B02B MEMORY

CA-D(0-7)

12,37

PNX-SPI-CS-AMBIn

D(16-23)

XIO-A(0-14)

7F04
7F05

VCC

CPLD

1M59
1

22

B02A FLASH

CA-A(00-14)

NAND
FLASH

39

PNX-SPI-CS-BLn

V22
W23

D(0-7)

FLASH

PNX-SPI-SDO

40

B02G

B02E CONTROL

MDI

CA-MDO(0-7)
7F02
7F03

68

B01B

PNX85500

MDO(0-7)

COMMON INTERFACE

CONDITIONAL
ACCESS

41

MDO

CA-MDI(0-7)
7F01

PCMCIA

43

D(8-15)

1P00
1

PXCLK54
PNX-SPI-CLK
PNX-SPI-SDI

B02E

B02A VIDEO STREAM

SIDE USB
CONNECTOR

6000 Serie

B02G
V23

PNX85500: STANDBY CONTROLLER

PNX85500-CONTROL

9CH0

BOOST-PWM

V23

B01E

BACKLIGHT-BOOST

B01E

B06C
B02G STANDBY

2
3
4

RC
LED-2

9U41

P1_0

LED2

AD19
AC25

LED1

AD26

PWM_0

PWM_1

LED-1

KEYBOARD

AD23

P5_O

+5V

SPI_CLK
P6_5
SPI_CSB
SPI_SDO
SPI_SDI
UA_RX_0
UA_TX_1
P1_7
RESET_IN
P6_4

AF24

PNX-SPI-CLK

AE22
AF23
AE23

PNX-SPI-WPn

PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI

1
5
2

AF25

B03C
B02E
B04A
B04A
B04A
B04A
B03H

DETECT2
RESET-SYSTEM
AV1-BLK
AV2-BLK

AB22
AD22
AC22

AV1-STATUS
AV2-STATUS
LCD-PWR-ONn

AE25
AE24
AC20

AA22

P3_2
P3_3
P3_5
P3_4

19
18

1
2

B04D HDMI

4x HDMI
CONNECTOR

XTAL_O

TO PIN:
1P02-13
1P03-13 PCEC-HDMI
1P04-13
1P05-13
ARX-HOTPLUG
1P04-19
BRX-HOTPLUG
1P03-19
CRX-HOTPLUG
1P02-19
DRX-HOTPLUG
1P05-19

7EC0
EF

P2_7
CEC-HDMI

AF19

7EC1
*SII9187ACNU
SII9287BCNU
31
35
41
45

HDMI
SWITCH

P1_2

B02C HDMI_DV
HDMI_RX

HDMIB-RC
3S0W
+3V3

W24

RREF

P0_4
P2_2
P0_3
P2_6
P0_6
P1_1
P2_3

+3V3-STANDBY

1 LEVEL SHIFTED
2
FOR
4 DEBUG USE
ONLY
5

FF04
FF29

7S20
NCP303LSN28G
2
INP
3
GND

XTAL_I

1F51
3

SDM
RESET-STBYn
SPI-PROG
+3V3-STANDBY

CADC_2
CADC_3
P2_0

VCC

512K

TXD-UP

AF22

PNX85500: STANDBY CONTROLLER

FLASH

RXD-UP

AG1
AH5
AB20
AA26

OUTP

B03C

DC / DC

RESET-STBYn

AE17

1S02

B02G

P5_1

7U43

+3V3-STANDBY

7
8

AE26

+12V
+3V3-STANDBY

AF17
AD21

ENABLE-3V3n

AF18
AE20

SEL-HDMI-ARC

AE18

RESET-ETHERNETn

AC21
AB19
AE19

RESET-AUDIO
TACH0

AF20

STANDBY

LAMP-ON

POWER-OK

*6000 Serie mux SIL9187 - non Instaport


8000 Serie mux SIL9287 - Instaport

2010-Apr-02 back to

div. table

CONTROL

LIGHT-SENSOR

54M

1M20
1

TO IR / LED BOARD AND 5


KEYBOARD CONTROL 6

7F52
M25P05-AVMN6P

B02D
B07A
B04C
B04E
B03G

B01E

BACKLIGHT-OUT
BACKLIGHT-BOOST

ENABLE -3V3-5V
ENABLE -1V8
DETECT2
1M99
5
6
7
9
1M95
2

B03E
B03B B03D
B02G B03A

TO
POWER
SUPPLY

TO
POWER
SUPPLY

18990_404_100331.eps
100331

Block Diagrams

Q552.1A LA

9.

EN 63

9-5 Block Diagram I2C


IC
B01E

PNX85500: MIPS

B04D

PNX85500-CONTROL

B01K

HDMI

B02A

B02I

Y25

XIO_D

XIO-D(00-07)

DDC_A_SCL

3F64

Y26

3S84

3S83

GPIO_2
Y24

B02I
DDR

B02I

VGA_EDID_SCL

44

DRX-DDC-SCL

RXD1-MIPS

3E53-4

3E53-3

TXD1-MIPS

3E53-2

3E53-1

1E06

PNX85500: ANALOG VIDEO

47

UART
SERVICE
CONNECTOR

EDID
SW

48

9FC1

VGA-SCL-EDID-HDMI

9FC3

3S5V-1

VGA-SDA-EDID

9FC2

3S5V-3

VGA-SCL-EDID

9FC4

9S15

VGA-SDA-EDID-TCON

9S14

VGA-SCL-EDID-TCON

3FD4

3FE8

3FD3
12
15

VGA
CONNECTOR

B01F

SDA-TUNER

3F75

TUN-P7

SCL-TUNER

3F76

TUN-P6

ERR
18

8000 Serie 512MB

RXD_2
RXD_3
RXCLK

B26

3S58

A25

3S5W

ETH-TXCLK

AA2

2_SCL

SDA-DISP

3KTV

9S12

SDA-DISP

3G2W

50

SCL-SET

9S11

SCL-DISP

3G2Y

49

LVDS
CONNECTOR

+3V3

TXD_2
TXD_3

+3V3

ERR
14

TXCLK
W21
GPIO_2
GPIO_3

W22

RXD2-MIPS
TXD2-MIPS

7S01
PCA9540B
2 CHAN.
MULTIPLEX.
ERR
24

ERR
64

3S66

20

TXD_0
TXD_1

Only for SHARP display with TCON on SSB


VIDEO OUT - LVDS

SDA-SET

3S68

ETH-TXD(2)
ETH-TXD(3)

AA1
AA4
AB1
AB2

3S80

ETH-TXD(0)
ETH-TXD(1)

3S81

22
23
24
25

TCON
SW

1G51

2_SDA

3S65

AA3

CONTROL

FLASH

B06B

3S67

AC1

E20

7KAA
UPD809900F1

7KQB
M25P32

+3V3
3S6B

ETH-RXD(2)

E19

Only for SHARP display with TCON on SSB


RXD_0
RXD_1

3S6C

ETH-RXD(3)
ETH-RXCLK

13

8-CHANNEL
PROG I2C
REF VOLT GEN

RES

ERR
34

7E10
LAN8710A-EZK

12

7KQA
ISL24837IRZ

MAIN
TUNER

ETHERNET + SERVICE

SDA-TCON
SCL-TCON

1T01
TH2603

Y5
Y6
AB4

RES

9JB6

3S61

3S6F

3S60

2 CHANNEL
MULTIPLEXER

3S6G

D(24-31)

B24
A23

7KQH
PCA9540B

HDMI & CI

4_SDA
4_SCL

ETH-RXD(0)
ETH-RXD(1)

TCON CONTROL
(SHARP)

1KQB
1

+3V3

11
10
9

B14A

P GAMMA & VCOM & FLASH (SHARP)

3KTU

D(0-7)

B14C

7B03
EDE1108AGBG

D(16-23)

1E05

VCC_3V3
A

1
2

VGA-SDA-EDID-HDMI

MEMORY

DQ

ETHERNET

19
18

+5V-VGA

AD24

B02B

DDR2-A(0-13)

*6000 Serie 256MB

HDMI
CONNECTOR
SIDE

RES

DDR2-D(0-31)

SDRAM

16

VGA

AD25

9JB7

SDRAM

1P05

15

+5V-EDID

SCL-DISP

SDRAM

ETHERNET
CONNECTOR
RJ45

DRX-DDC-SDA

ETHERNET + SERVICE

ANALOGUE
VIDEO

D(8-15)

7B01
EDE1108AGBG

7B02
*EDE1116AEBG
EDE1108AGBG

B04C

43

VGA_EDID_SDA

7B00
*EDE1116AEBG
EDE1108AGBG

SDRAM

+3V3

B01I
B04C

DIN-5V

HDMI
CONNECTOR 1

DDCA-SCL

Y23

B05A

uP
LEVEL SHIFTED
FOR DEBUG
2
USE ONLY

+3V3

MAIN
SW

GPIO_3

1F51
1

1
2

TXD-UP

HDMI_DV

*6000 Serie 256MB


8000 Serie 512MB

19
18

3F65

DDCA-SDA

DDC_A_SDA
FLASH

15

FLASH
(4Gx16)

AF21

16

CRX-DDC-SCL

RES

HDMI

11

P3_1

CRX-DDC-SDA

RES

B01H

19
18

P3_0

RXD-UP

3ECU-4

7F20
*NAND02GW3B2DN6F
NAND04GW3B2DN6F

HDMI
CONNECTOR 2
1P02

40

3ECU-2

AE21

MAIN NVM
SW

3S1H

FLASH

3S1G

B01B

15

10

39
+3V3-STANDBY

BRX-DDC-SCL
CIN-5V

ERR
35

RES

16

15

3S2G

ERR
42

1P03
BRX-DDC-SDA

AC24

TEMP
SENSOR

MC_SCL

TUNER
BRAZIL

HDMI
CONNECTOR 3

34
EEPROM
(NVM)

7FD1
LM75BDP

3FBF-1

3S2F

33

7FE0
TC90517FG

3FBF-2

AC23

15

3FC2

6
ERR
23

MC_SDA

16

ARX-DDC-SCL

3FC1

STANDBY
SW

ERR
53

ARX-DDC-SDA

BIN-5V

7F58
M24C64

STANDBY
ERR
15

30

HDMI
MUX

1
2

PNX-SPI-CSBn
PNX-SPI-SDO
PNX-SPI-SDI

29

3ECP-1

1
5
2

+3V3-STANDBY

AF24

SPI_CLK
AE22
P6_5
AF23
SPI_CSB
AE23
SPI_SDO
AF25 SPI_SDI

DEBUG
ONLY

3ECP-3

512K

PNX-SPI-CLK
PNX-SPI-WPn

3S6W

VCC

6
3

3F62

PNX85500: STANDBY
CONTROLER

3S6V

+3V3-STANDBY

FLASH

B02G

3F63

1_SCL
B02G

7EC1
SII9287B
*SII9187A

1F52
3

3F63

SCL-UP-MIPS

45

19
18

SDA-UP-MIPS

46

1P04

1
2

3S57

AIN-5V
54

3ECA-4

3S56

C26

1_SDA

3F59

C25

3S69

CONTROL

3S6A

53

3EC1-3

ERR
13

PNX85500

3ECA-2

+3V3

3FE9

SCL-SSB
3EC5

3_SCL

TEMP SENSOR +
HEADPHONE

SDA-SSB

3EC1-1

3S5Z

3ECA-1

3S5Y

A24

3_SDA

3ECA-3

B25

3S6D

B02E

7F52
M25P05-AVMN6P

B01J

TUNER BRAZIL

+3V3

7S00
PNX85507EB

3EC3

B02E

PNX85500: CONTROL

3S6E

B01E

B09A

NON DVBS CONNECTOR BOARD

B14F

CONNECTORS (SHARP)

1F53

3C84

3C85

3C83

1M71
3

1F53

2D
DIMMING

3K84

3K85

3K83

1M71
1

2D
DIMMING

7
8

3C81
RES
9S13
9S10

RES

TO
1 TEMPERATURE
SENSOR
SDA-BL

3K81

TO
3 TEMPERATURE
SENSOR

RES

div. table

Programmable via USB


Programmable via ComPair

SW

Pre-programmed device

SCL-BL

Only for SHARP display with TCON on SSB

2010-Apr-02 back to

SW
SW

18990_405_100331.eps
100331

Block Diagrams

Q552.1A LA

9.

EN 64

9-6 Supply Lines Overview


SUPPLY LINES OVERVIEW

B03D

1M99
1

+12V

GND1

BL_ON_OFF
DIM
BOOST
N.C
POK
N.C.
N.C.
N.C.

+3V3

5FE4

LAMP-ON
BACKLIGHT-PWM_BL-VS
BACKLIGHT-BOOST

8
9

8
9

BACKLIGHT-PWM-ANA-DISP

10

10

11

11

BL-SPI-SDO
BL-SPI-CSn

12

12

BL-SPI-CLK

POWER-OK

B02G
B06C
B01E
B02G

+12V
+12V
+12V
+VSND
GND_SND
N.C.

6
7
8

6
7
8

9
10

9
10

11

11

+12V
3U16

+3V3
+2V5

IN OUT
COM

B02h
+2V5-LVDS

CUA0

B02G

1U40

+12V

T 3.0A

PNX85500: SDRAM

+12V
+2V5-REF

DDR2-VREF-CTRL3

3S06

DDR2-VREF-CTRL2

+12V

B03c

B02C

+12V

7UD1

PNX85500: DIGITAL VIDEO IN

+3V3

5UD3
+3V3

IN OUT
COM

5UD2

+3V3

5UD1

+5V5-TUN

7UD0
5UD0
IN OUT
COM

6UD0
+3V3

+3V3

+5V

+5V

B02D

B03e

+3V3

B03e

3S11

B03e

3F01

+24V-AUDIO-POWER

B03c

+24V-AUDIO-POWER

+3V3

+3V3-STANDBY

5UM1

1UM0

B01C

USB HUB

+3V3

+3V3

+5V

+5V

B03e

3F25
3F32

+T

B02G

+1V1

+3V3-STANDBY

+3V3

+3V3

B03e

B03d

3F40

+3V3-SD
B03b

+T

+3V3

+3V3

B03e
B03c

+3V3-STANDBY

+1V2

+1V2

+1V8

+1V8

+3V3

+12V

+12V

+2V5-AUDIO

1M72
1
2

+3V3

+3V3-STANDBY

+3V3-STANDBY

B03e

+VDISP-INT

B06a,B11b,
B14b

B04A

9F71

AUDIO

+5V

+5V

+3V3-STANDBY

+24V-AUDIO-POWER

B03e

5E08

B14B

B03e

B03B

+3V3
5FA3

+1V2-BRA-VDDC

B03c

5FA4

+1V2-BRA-DR1

B03c

1P05
18

DIN-5V

B04d

VGA

VGA
CONNECTOR

7U02-1

12
Dual
Synchronous
7U02-2
Step-Down
Controller
14

1
1E05
9

+5V-VGA

7U04

B04d

+3V3
B03e

mini_AVDD

5KAD

SSCG_AGND
VCC_+3V3

5KAE

VDD33

5KAF

VDDQ

B03h

TCON DC / DC (SHARP)
VCC_1V2

+VDISP-INT

+VDISP-INT

1KFA

+VDISP

T 3.0A

+3V3-STANDBY

B14a,c,d

VLS_15V6_B

7KFE

+5V-VGA

12V/1V8
COVERSION
5U00

+1V8

+5V
B03e

B02b,h,B03d,
B05a

HDMI 2
CONNECTOR
HDMI 1
CONNECTOR

12V/1V1
COVERSION

5U01

+1V1

1P04
18

AIN-5V

1P03
18

BIN-5V

1P02
18

CIN-5V

DIN-5V

B01h

DIN-5V

B04E
+3V3

+3V3

+3V3

+3V3-STANDBY

VLS_15V6

9KFE

VGH_35V

3KFP

VGL_-6V

B14c,d,e

B14b

VCC_3V3

B14a,c,d,e
B14e
B14e

P GAMMA & VCOM & FLASH (SHARP)

VCC_3V3
+VDISP

VCC_3V3
+VDISP

VLS_15V6

VLS_15V6

7KQA
ISL248371RZ

HEADPHONE

B03e
B03c

B14C
B14b

B14b

B02g,h,
B03e,B08a

TEMP SENSOR + HEADPHONE

IC
LCD
SUPPLY

+5V

HDMI 3
CONNECTOR

9KFC

7KFA
ISL97653AIRZ

+5V-EDID

23
24

B01J

LVDS_AVDD

VCC_1V2

+3V3-HDMI

+5V-VGA

B01I

7U01

B01I

5KAB
5KAC

B14b

+12V

+12V

B01k

HDMI

HDMI SIDE
CONNECTOR

+3V3-STANDBY

B03c
B01k

+3V3
5EC0

+3V3-STANDBY

7U03
TPS53126PW

B01H

HDMI

B03e

DC / DC

+3V3-STANDBY

7FA3
IN OUT
COM

B14a

+3V3

TOSHIBA SUPPLY

+3V3

VDD12

+3V3-ET-ANA

+AVCC

B04D
B01G

5KAA

+3V3

+24V-AUDIO-POWER

3D09

VCC_1V2

VCC_3V3

ETHERNET + SERVICE

+3V3

B03c

+VDISP
5KAG

ANALOGUE EXTERNALS A
+3V3

B04C

+3V3-STANDBY

+5V-TUN-PIN

TCON CONTROL (SHARP)

+VDISP

VIN SW
GND

+3V3

B03c

B03d

B14A

7KAC

B14b

+5V-TUN

T 1.5A

+12VD

B03e

+5V-TUN

VIO
+24V

B03e

+5V

B03A

VINT

1HA0

7UU2
LCD-PWR-ONn

+3V3

+3V3-STANDBY

HDMI & CI

+3V3

+2V5-LVDS

B03c

B01F

AMBILIGHT CPLD

5HA1

7UU1

+2V5-AUDIO

+3V3

B03e

+3V3-STANDBY

+5V

B13
+3V3

B03e

VDISP - SWITCH

+12VD

B03c

+2V5

+2V5-LVDS

B03d

+12V

FAN - CONTROL

+3V3-STANDBY

B03c
+1V1

+2V5

B02d

PNX85500: CONTROL

T 2.0A

B14b

B03d

B01E

B03e

PNX85500: POWER

+1V1

1M59
21

+12V

+3V3

SD-CARD

TO
IR/LED
PANEL
B08a

B03c

+3V3

B03H
B02H

1C86
*1T86

5HA0

B03c

B03b

8
+24V

+3V3-STANDBY

+T

B01D

+5V

1M09
1
2

B03e
B03c

+5V-USB1
+5V-USB2

B03G

PNX85500: STANDBY CONTROLLER

+1V1

B03b

+3V3

V-AMBI

T 1.0A

+3V3-STANDBY

+12V

+3V3-STANDBY

+5V

B03e

+3V3

+3V3

+12V

(*NON) DVBS CONNECTOR BOARD

+3V3

TEMPSENSOR + AMBILIGHT

B03c

B03e

B03c
+3V3

B03e

+3V3

B03e

+3V3

SPI-BUFFER

TO
IR/LED
PANEL

1M20
5

+3V3

PNX85500: MIPS

FLASH

B03e

+24V-AUDIO-VDD

B03F
B02E

VIO

ONLY FOR 5000 SERIES

+T

B01B

1M20
5

5GA1

+3V3

B09A

+5V

VINT

B03c
+3V3

IN OUT
COM

B02h

+5V

B03e

+3V3
+3V3-STANDBY

5GA0

+3V3-STANDBY

+2V5-AUDIO

3S0Z

+5VCA

+3V3

CONNECTORS

+3V3-STANDBY

B03c

B11a

B06D

B01,a,c,e,k,
B03c,d,B04a,d,
B09a,B11d,
B14f
B03e

7UD3

7S08

+5V

B03d

+3V3-ARC

IN OUT
COM

+3V3

B03e
+5V

B03e

+2V5

IN OUT
COM

+3V3

COMMON INTERFACE

+3V3

+5V

PNX85500: AUDIO
7UD2

B03e

+3V3
B01,a,b,c,d,e,
g,j,jk,B14f
B02a,c,d,e,h,
B03c,f,g,h,
B04a,c,d,e,
B06b,c,d,
B08a,B09a,
B11d,B13

VLS_15V6

+3V3

DC / DC
B03e

VCC_3V3

VLS_15V6

B14F

+VDISP
B03e

+1V1

VCC_3V3

+3V3

+VDISP

B06C
B03E

VGH_35V

B14b

+3V3
B03e
B06a

+1V1

B03A

VIDEO OUT - LVDS

+1V8
3S20

+24V-AUDIO-POWER

MAINS-OK

ENABLE-1V8

VGL_-6V

VGH_35V

B14b

B06B

7UA0
VOLT.
REG.

MINI LVDS

VGL_-6V

B14b

T 3.0A
B01f

+12V

B14E

B14b

1G00

+5V-TUN

B03b

B03e

B01A

5G02

+3V3

B03b,d,e,g,
B08b,B09a,
B11d,B14f
B02d,B03a

B06b

T 3.0A

+5V5-TUN
7UA6

+1V8

B03b

B14b

+VDISP

B03e

3UA0

B02B

+VDISP-INT

5G01

B02h

PNX85500: NANDFLASH
CONDITIONAL ACCESS

+VDISP
VLS_15V6

B03h
1G03

3U15

B03c

STANDBY

+VDISP
B14b
VLS_15V6

7UC0

+2V5-BRA

+3V3

B01e,B02e,
g,h,B03a,b,h,
B04d,e,B09a,
B11d,B14f

VREF_15V2

B14c

+VDISP-INT

B03e

+5V5-TUN

+3V3-STANDBY

VREF_15V2

DISPLAY INTERFACING-VDISP

NOT FOR 5000 SERIES

B02A

VCC_3V3

B14b
DDR2-VREF-DDR

+5V

7FE3
IN OUT
COM

B02G

1M95
1

VCC_3V3

+1V8
3B20

B06A

+5V

+5V
5FE9

B03e

2
3
4
5

+3V3-BRA-FLT

+5V

B03e

Optional 1M99 is 12 pin connector

1M95
1
3V3_ST
2
STANDBY
3
GND1
4
GND1
5
GND1

+1V8
B03b

+3V3
+3V3-BRA

4
5
6
7

+1V2

7UA3

MPD

DDR

B02h

B03e

5
6
7

+1V8

+1V2-BRA-DR1

5FE7
4

+1V8
B03b

+1V2-BRA-DR1
B01g

6EC1

PSU

B03h
2

+1V2-BRA-VDDC

B01g

+12VD

B14D
B05A

+1V2-BRA-VDDC

1M99
1

DC / DC

TUNER BRAZIL

5U02

+12V
GND1

B01K

DC / DC

OR

B03C

IC
LCD
SUPPLY

VREF_15V2

B14d

+3V3-STANDBY

18990_406_100331.eps
100331

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 65

10. Circuit Diagrams and PWB Layouts


10-1 AL1 820400089786 AmbiLight Common
LiteOn LED Common 1

LiteOn 15 LED Common

AL1A
1

AL1A

10

11

12

13

14

+3V3
2B11
100n

8
150R
1K8

4 3B00-4 5
150R

PROG
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
3
SPI-DATA-IN
SPI-DATA-OUT 3B00-3

FB03

TEMP-SENSOR

FB05

3B18
FB35

22
25
32

3B22
10K

6
100p

XERR
XHALF
XLAT

12
13
28
29

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

0
1
2
3
4
5
6
7
OUT
8
9
10
11
12
13
14
15

BLANK
GSCLK
IREF
MODE
SCLK
SIN
SOUT

NC

GND

PWM-R1
PWM-G1
PWM-B1
PWM-G3
PWM-R3
PWM-R2
PWM-G2
PWM-B2
PWM-B3
PWM-G4
PWM-R4
PWM-B4
PWM-B5
PWM-G5
PWM-R5
DATA-SWITCH

SPI-DATA-RETURN
FB15
SPI-DATA-IN
FB16
SPI-CLOCK

27 26

+3V3

2K0
7B26-2
TLC5946RHB
34
VIA
35
VIA VIA
36
VIA

FB13

3B31

GND_HS

30

100p

2B04-3

2B04-4

LATCH
SPI-CS
FB12
PWM-CLOCK

+3V3

31
24
26
3
1
2
23

150R

BLANK
PROG

FB10
FB11

3B21
150R

+3V3

100p

FB06

FB07

FB20

+3V3

6
150R

2 3B00-2 7

LATCH

FB04

FB08

VCC

3B00-1

33

1
BLANK
PWM-CLOCK-BUF

27

+24V

2B04-2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

42
41
40

1M83
37
38
39

7B26-1
TLC5946RHB

FB01

100p
2B04-1

FH12-25S-0.5SH(55)

+3V3

3B34

6
3B39-3

5
2

100R

3B30-4

10n
3B39-1

2B09

SPI-CLOCK-BUF

2B10

33p

2B01

220R

+24V

100p

3B01-1

1K5 1%

SPI-CLOCK

SPI-DATA-RETURN

7B23-1
BC847BS(COL)
6

10K

8 3B07-1 1

FB41
7B20-2
74LVC2G17
+3V3

1K5 1%

7
3B39-2

1K5 1%
RES

10n
3004

GND

TEMP-SENSOR

LMV331IDCK

10K

10K

+3V3

2B08

-T

10K

7B30
1
3

3B11

FB40

PWM-CLOCK-BUF

220R

3B02-2
HOLD

1 3B30-1 8

100R

C
S

10K

100p

1 3B02-1 8

2 3B01-2 7

PWM-CLOCK

2B02

+3V3

+3V3

2
3

DATA-SWITCH

(64K)

VCC

33p

2B00

+3V3
7B06
74LVC1G32GW
1
SPI-CS

7B20-1
74LVC2G17

100K RES

100n

SPI-CLOCK-BUF
7B07
M95010-WDW6

+3V3

+3V3
2B17

100n

2B20

+3V3

SPI-DATA-IN-BUF

1
10K

2 3B07-2 7

FB30

PWM-B1

3B35

7B23-2
BC847BS(COL)
3

10K

5 3B07-4 4

7002
LTW-008RGB

7001
LTW-008RGB

BLUE

BLUE

270R

GREEN

GREEN

GREEN

3B37

RED

RED

RED

BLUE

BLUE

GREEN

GREEN

GREEN

RED

RED

RED

1
3

270R
3B36

BLUE

BLUE

7005
LTW-008RGB

7004
LTW-008RGB

7003
LTW-008RGB

68R

4
10K

3 3B07-3 6

1 3B03-1 8
FB31

PWM-R1

+24V

7000
LTW-008RGB

+24V

2
+24V

1K5
3B03-2

1K5

7B25
BC847BW 3

3
B002

2B03

2
10K

5 3B13-4 4

2
B001

FB32

PWM-G1

1K5

1K5
3B03-4

100n

10K

3 3B13-3 6

3 3B03-3 6

10

11

12

13

14

1M83 C1
2B00 E8
2B01 F8
2B02 E9
2B03 I14
2B04-1 B7
2B04-2 B6
2B04-3 B8
2B04-4 B7
2B08 E12
2B09 E12
2B10 F9
2B11 A9
2B17 D8
2B20 D4
3004 E12
3B00-1 A6
3B00-2 B6
3B00-3 B6
3B00-4 B6
3B01-1 E7
3B01-2 D7
3B02-1 E3
3B02-2 E5
3B03-1 H14
3B03-2 H14
3B03-3 H14
3B03-4 H14
3B07-1 F3
3B07-2 G3
3B07-3 H3
3B07-4 G3
3B11 E12
3B13-3 H3
3B13-4 I3
3B18 A8
3B21 B7
3B22 B8
3B30-1 D9
3B30-4 E9
3B31 B10
3B34 D13
3B35 G14
3B36 G14
3B37 G14
3B39-1 E13
3B39-2 D12
3B39-3 D13
7000 G5
7001 G7
7002 G8
7003 G10
7004 G11
7005 G13
7B06 D3
7B07 D4
7B20-1 D8
7B20-2 E8
7B23-1 F4
7B23-2 G4
7B25 H3
7B26-1 A8
7B26-2 C9
7B30 D13
FB01 A1
FB03 B1
FB04 B1
FB05 B1
FB06 B2
FB07 B1
FB08 B1
FB10 B2
FB11 B1
FB12 B2
FB13 C1
FB15 C1
FB16 C1
FB20 B7
FB30 G3
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13

B007

AL 2K10 LiteOn
15 LED Common

8204 000 8978

2009-12-04

2009-10-28

2009-10-07

2009-08-27

2009-07-03

18770_600_100212.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 66

LiteOn LED Common 2

AL1B
1

LiteOn 15 LED Common 2


2

AL1B

10

11

12

7B50-1
BC847BS(COL)

10K

5 3B55-4 4

+24V

1
10K

3 3B55-3 6

FB70

PWM-B2

3B50
+24V

7B50-2
BC847BS(COL) 3

10K

BLUE

BLUE

270R

BLUE

BLUE

BLUE

BLUE

GREEN

GREEN

3B52

GREEN

GREEN

GREEN

GREEN

RED

RED

RED

RED

RED

RED

8
+24V

1K5
3 3B53-3 6

100n

2 3B53-2 7
FB71

1K5

+24V

4 3B53-4 5
1K5
7B51
BC847BW 3

10K

3 3B57-3 6

68R
3B53-1

1K5

10K

1 3B55-1 8

7100
LTW-008RGB

PWM-G2

7101
LTW-008RGB

7102
LTW-008RGB

7103
LTW-008RGB

270R
3B51

2B50

7 3B55-2 2

7104
LTW-008RGB

7105
LTW-008RGB

2
10K

7 3B57-2 2

FB72

PWM-R2

7C20-1
BC847BS(COL) 6

10K

5 3C00-4 4

+24V

1
10K

3 3C00-3 6

FC01

PWM-B3

1 3C10 2
+24V

7C20-2
BC847BS(COL) 3

10K

7 3C00-2 2

1 3C11 2

4
10K

1 3C00-1 8

BLUE

BLUE

BLUE

Blue

3C12

GREEN

GREEN

GREEN

Green

RED

RED

RED

Red

1 3C15-1 8

1K5
3C15-2

1K5

FC02

PWM-G3

270R

68R

7202
LTW-008RGB

7201
LTW-008RGB

7200
LTW-008RGB

270R

3 3C15-3 6

1K5
4 3C15-4 5
1K5

7C22
BC847BW 3

10K

1 3C06-1 8

+24V

H
PWM-R3

2
10K

7 3C06-2 2

FC03

10

11

2B50 C11
3B50 B7
3B51 B7
3B52 B7
3B53-1 B7
3B53-2 C7
3B53-3 C7
3B53-4 C7
3B55-1 C3
3B55-2 B3
3B55-3 A3
3B55-4 A3
3B57-2 D3
3B57-3 C3
3C00-1 G3
3C00-2 F3
3C00-3 F3
3C00-4 E3
3C06-1 G3
3C06-2 H3
3C10 F4
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
3C15-3 G4
3C15-4 G4
7100 B11
7101 B10
7102 B9
7103 B7
7104 B6
7105 B5
7200 F8
7201 F9
7202 F10
7B50-1 A3
7B50-2 B3
7B51 C3
7C20-1 E3
7C20-2 F3
7C22 G3
FB70 B3
FB71 C3
FB72 D3
FC01 F3
FC02 G3
FC03 H3

12
AL 2K10 LiteOn
15 LED Common

8204 000 8978

2009-12-04

2009-10-28

2009-10-07

2009-08-27

2009-07-03

18770_601_100212.eps
100212

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 67

10-2 AL1 820400089691 9 LED LiteOn


9 LED LiteOn

AL2A

9 LED LiteOn

AL2A
3

10

A
7203
LTW-008RGB

1M84

7205
LTW-008RGB

7204
LTW-008RGB

SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN

Blue

BLUE

BLUE

BLUE

Green

GREEN

GREEN

GREEN

PWM-CLOCK-BUF

Red

RED

RED

RED

SPI-CS
LATCH

+24V

100n

+3V3

2D01

1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5

PROG
BLANK
+3V3

TEMP-SENSOR

C
+24V
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27

FH12-25S-0.5SH(55)

FD04

B003

10

B004
1

9 LED LiteOn
AL 2K10

2009-10-07

8204 000 8969


3104 313 63812
18770_610_100212.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 68

9 LED LiteOn

AL2B

9 LED LiteOn

AL2B
3

10

11

12

13

+24V

A
7D01-1
BC847BS(COL)
6

10K

8 3D02-1 1

FD01
1 3D10 2

+24V

7300
LTW-008RGB

7302
LTW-008RGB

7301
LTW-008RGB

7303
LTW-008RGB

7304
LTW-008RGB

7305
LTW-008RGB

7D01-2
BC847BS(COL)
3

10K

6 3D02-3 3

PWM-R4

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

270R

GREEN

GREEN

GREEN

GREEN

GREEN

GREEN

3D12

RED

RED

RED

RED

RED

RED

68R

1 3D13-1 8

1K5

FD02

2 3D13-2 7

1K5

7D02
BC847BW 3

10K

3 3D05-3 6

1K5
3 3D13-3 6
4 3D13-4 5
1K5
2D10

2
10K

5 3D05-4 4

+24V

PWM-G4

+24V

10K

4 3D02-4 5

270R
3D11

100n

PWM-B4

1
10K

2 3D02-2 7

FD03

10

11

12

2D10 D13
3D02-1 A1
3D02-2 B1
3D02-3 B1
3D02-4 C1
3D05-3 C1
3D05-4 D1
3D10 B12
3D11 B12
3D12 B12
3D13-1 C12
3D13-2 C12
3D13-3 C12
3D13-4 D12
7300 B5
7301 B6
7302 B7
7303 B8
7304 B10
7305 B11
7D01-1 A2
7D01-2 B2
7D02 C2
FD01 B1
FD02 C1
FD03 D1

13

9 LED LiteOn
AL 2K10

2009-10-07

8204 000 8969


3104 313 63812
18770_611_100212.eps
100212

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 69

10-3 AL1 820400089703 15 LED LiteOn


15 LED LiteOn

AL2A

15 LED LiteOn

AL2A
2

10

1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5
FD18 C7

FH12-25S-0.5SH(55)
7203
LTW-008RGB

SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN

Blue

BLUE

BLUE

BLUE

Green

GREEN

GREEN

GREEN

PWM-CLOCK-BUF

Red

RED

RED

RED

SPI-CS
LATCH

+24V

100n

+3V3
2D01

1M84

7205
LTW-008RGB

7204
LTW-008RGB

PROG
BLANK
+3V3

TEMP-SENSOR

C
+24V

26

FD18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

C
27

B003

B004

10

B005

15 LED LiteOn
AL 2K10

8204 000 8970


3104 313 63823

2009-12-07

2009-10-07

2009-07-02

18770_620_100212.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 70

15 LED LiteOn

AL2B

15 LED LiteOn
1

AL2B

10

11

12

13

7D01-1
BC847BS(COL)
6

10K

8 3D02-1 1

+24V

2 3D02-2 7

10K

FD01
3D10
+24V

7300
LTW-008RGB
7D01-2
BC847BS(COL)
3

10K

6 3D02-3 3

+24V

4 3D02-4 5

PWM-R4

7302
LTW-008RGB

7301
LTW-008RGB

7305
LTW-008RGB

7304
LTW-008RGB

7303
LTW-008RGB

270R
3D11

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

270R

GREEN

GREEN

GREEN

GREEN

GREEN

GREEN

3D12

RED

RED

RED

RED

RED

RED

10K

4
1 3D13-1 8
1K5

FD02

2 3D13-2 7
+24V

1K5
3 3D13-3 6
4 3D13-4 5
1K5

10K

2D10

1
5 3D05-4 4

1K5

7D02
BC847BW 3

10K

3 3D05-3 6

PWM-G4

68R

100n

PWM-B4

FD03

+24V

10K

7D03-1
BC847BS(COL)
6

3D04-3

10K

3D04-4

PWM-B5

FD04
3D15
+24V

+24V

7400
LTW-008RGB

10K

7D03-2
BC847BS(COL)
3

7401
LTW-008RGB

7404
LTW-008RGB

7403
LTW-008RGB

7402
LTW-008RGB

7405
LTW-008RGB

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

GREEN

GREEN

GREEN

GREEN

GREEN

GREEN

RED

RED

RED

RED

RED

RED

270R

270R
3D17
68R

10K

4
1 3D18-1 8

3D04-2

PWM-R5

3D16

3D04-1

1K5
2 3D18-2 7

FD05
+24V

1K5

1K5
4 3D18-4 5
1K5

2
10K

3D03-3

2D11

100n

10K

7D04
BC847BW 3

3D03-4

3 3D18-3 6

PWM-G5

FD06

10

11

12

2D10 C13
2D11 H13
3D02-1 A1
3D02-2 A1
3D02-3 B1
3D02-4 B1
3D03-3 H2
3D03-4 G2
3D04-1 F2
3D04-2 G2
3D04-3 E2
3D04-4 F2
3D05-3 C1
3D05-4 D1
3D10 B12
3D11 B12
3D12 B12
3D13-1 B12
3D13-2 C12
3D13-3 C12
3D13-4 C12
3D15 F12
3D16 F12
3D17 F12
3D18-1 G12
3D18-2 G12
3D18-3 G12
3D18-4 G12
7300 B5
7301 B6
7302 B7
7303 B8
7304 B10
7305 B11
7400 F5
7401 F6
7402 F7
7403 F8
7404 F10
7405 F11
7D01-1 A2
7D01-2 B2
7D02 C2
7D03-1 E2
7D03-2 F2
7D04 G2
FD01 A1
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1

13

15 LED LiteOn
AL 2K10

8204 000 8970


3104 313 63823

2009-12-07

2009-10-07

2009-07-02

18770_621_100212.eps
100219

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 71

10-4 AL1 3104313 - 63895, 63812


Layout AmbiLight LiteOn

AmbiLight LiteOn

7103

7103

3B51
3B50

3B53

7104

7105
7B50

FB70

FB20

FB72

FC02

FC03

FB71

7200
3C11

3B57

3C10

3C15

7201

7202

1M84

7203

B003

7102

7204

7204

B003

7101

3C12

7B26

3C06

2B11

7C20

FB35

3B55

7100
2B50

7C22

3B22

FB03

3C00

FC01

7005
3B21

2B04

7B51

2B03

FB07

FB06

FB15

3B52

7004
FB05

FB31

B002

FB11

3B35
3B36

FB01

7B06

7B07

3B37

7003

B002

FB10

3B18

1M83

B007

FB13

3B30

FB12

FB16

3B00

7B20

3B31

7002
2B17

3B02

FB40

FB08

2B10
2B02
2B20

3B39

3B01

7001

FB41

7B30

2B00
2B01

2B09

FB04

3B34

FB30

3004
2B08
3B11

3B13

7B25
3B07

7B23

B001

FB32

7000

3B03

18 LED

7205

2C15

7205

3104 313 6389.5

FD02

7104

7105
7B50

FB70

FB72

FB20

FC02

FC03

FB71

7200
3C11

3B57

3C10

3C15

7201

3C12

3B53

3C00

3B51
3B50

3B55

7102

3B52

FC01

7101

7202

7203

7300

7301
FD03

2D01
3D02

7D01
FD01

3D05

7302

1M84

7303

7304

7305
2D10

2B11

FD04

3D10
3D11

3D12

FB03

FB35

3D13

2B04

7100
2B50

B004

FB15

3B22

3B18

3B03

3B37

3B21

7D02

FB31

7005

3C06

7B07

2B03

7C20

FB10

3B31

3B30

1M83

FB07

FB06

7C22

FB13

7004
FB05

7B51

FB16

FB11

7B26

7B20

FB01

7B06

B007

FB08

7003

3B00

3B39

FB12

3B02

7B30

7002
2B17

3B01

FB40

2B00
2B01

2B09

7001

FB41

2B10
2B02
2B20

FB30

FB04

3B34

3004
2B08
3B11

3B07

7B23

3B13

7B25

B001

FB32

7000

3B35
3B36

24 LED

3104 313 6381.2

18770_602_100216.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 72

10-5 AL1 820400090592 AmbiLight Common


Everlight LED Common 1

Everlight 15 LED Common

AL1A
1

AL1A

11

10

12

13

14

+3V3
2B11
100n

FB03

TEMP-SENSOR

2 3B00-2 7

3B21
150R

+3V3

22
25
32

3B22
10K

100p

2B04-3

5
100p

XERR
XHALF
XLAT

12
13
28
29

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

0
1
2
3
4
5
6
7
OUT
8
9
10
11
12
13
14
15

BLANK
GSCLK
IREF
MODE
SCLK
SIN
SOUT

NC

GND

PWM-R1
PWM-G1
PWM-B1
PWM-G3
PWM-R3
PWM-R2
PWM-G2
PWM-B2
PWM-B3
PWM-G4
PWM-R4
PWM-B4
PWM-B5
PWM-G5
PWM-R5
DATA-SWITCH
3B31

GND_HS

30

LATCH
SPI-CS
FB12
PWM-CLOCK

100p

BLANK
PROG

+3V3

FB20

3B18
FB35

150R

FB10
FB11

6
150R

2B04-4

FB07
FB08

3
3B00-3

LATCH

FB06

1K8

4 3B00-4 5
150R

PROG
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-IN
SPI-DATA-OUT

+3V3

31
24
26
3
1
2
23

8
150R

100p
2B04-1

FB04

FB05

VCC

3B00-1

33

BLANK
PWM-CLOCK-BUF

27

+24V

2B04-2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

SPI-DATA-RETURN
FB15
SPI-DATA-IN
FB16
SPI-CLOCK

27 26

+3V3

2K0
7B26-2
TLC5946RHB
VIA
34
35
VIA VIA
36
VIA

FB13

42
41
40

1M83
37
38
39

7B26-1
TLC5946RHB

FB01

FH12-25S-0.5SH(55)

+3V3

3B34

6
3B39-3

7
8

2
1

100R

3B30-4

SPI-CLOCK-BUF

2B10

33p

2B01

220R

+24V

100p

3B01-1

10n
3B39-1

2B09

5
1

SPI-CLOCK

1K5 1%

4
SPI-DATA-RETURN

7B23-1
BC847BS(COL)
6

10K

8 3B07-1 1

FB41
7B20-2
74LVC2G17
+3V3

1K5 1%

3
RES

10n
3004

10K

TEMP-SENSOR

LMV331IDCK

10K

10K

GND

7B30
1
3

2B08

+3V3

3B11

FB40

PWM-CLOCK-BUF

1K5 1%

3B39-2
1 3B30-1 8

8
HOLD

220R

3B02-2

10K

100R

100p

1
1 3B02-1 8

2 3B01-2 7

PWM-CLOCK

-T

+3V3

2B02

(64K)
C

+3V3

4
DATA-SWITCH

VCC

33p

2B00

+3V3
7B06
74LVC1G32GW
1
SPI-CS

7B20-1
74LVC2G17

100K RES

100n

SPI-CLOCK-BUF
7B07
M95010-WDW6

+3V3

+3V3
2B17

100n

2B20

+3V3

SPI-DATA-IN-BUF

1
10K

2 3B07-2 7

FB30

PWM-B1

3B35

7B23-2
BC847BS(COL)
3

10K

5 3B07-4 4

BLUE

BLUE

BLUE

GREEN

GREEN

GREEN

RED

RED

RED

7004
99-235/RSBB7C-A24/2D

7003
99-235/RSBB7C-A24/2D

7002
99-235/RSBB7C-A24/2D

7001
99-235/RSBB7C-A24/2D

7005
99-235/RSBB7C-A24/2D

BLUE

BLUE

BLUE

270R

GREEN

GREEN

GREEN

3B37

RED

RED

RED

270R
3B36

68R

4
10K

3 3B07-3 6

1 3B03-1 8
FB31

PWM-R1

+24V

7000
99-235/RSBB7C-A24/2D

+24V

2
+24V

1K5
3B03-2

1K5

7B25
BC847BW 3

B002

2B03

2
10K

5 3B13-4 4

2
B001

FB32

PWM-G1

1K5

1K5
3B03-4

100n

10K

3 3B13-3 6

3 3B03-3 6

10

11

12

13

1M83 C1
2B00 E8
2B01 F8
2B02 E9
2B03 I14
2B04-1 B7
2B04-2 B6
2B04-3 B8
2B04-4 B7
2B08 E12
2B09 E12
2B10 F9
2B11 A9
2B17 D8
2B20 D4
3004 E12
3B00-1 A6
3B00-2 B6
3B00-3 B6
3B00-4 B6
3B01-1 E7
3B01-2 D7
3B02-1 E3
3B02-2 E5
3B03-1 H14
3B03-2 H14
3B03-3 H14
3B03-4 H14
3B07-1 F3
3B07-2 G3
3B07-3 H3
3B07-4 G3
3B11 E12
3B13-3 H3
3B13-4 I3
3B18 A8
3B21 B7
3B22 B8
3B30-1 D9
3B30-4 E9
3B31 B10
3B34 D13
3B35 G14
3B36 G14
3B37 G14
3B39-1 E13
3B39-2 D12
3B39-3 D13
7000 G5
7001 G7
7002 G8
7003 G10
7004 G11
7005 G13
7B06 D3
7B07 D4
7B20-1 D8
7B20-2 E8
7B23-1 F4
7B23-2 G4
7B25 H3
7B26-1 A8
7B26-2 C9
7B30 D13
FB01 A1
FB03 B1
FB04 B1
FB05 B1
FB06 B2
FB07 B1
FB08 B1
FB10 B2
FB11 B1
FB12 B2
FB13 C1
FB15 C1
FB16 C1
FB20 B7
FB30 G3
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13

14

B007

AL 2K10 Everlight
15 LED Common

2009-11-27

2009-11-03

8204 000 9059


18770_670_100212.eps
100219

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 73

Everlight LED Common 2

AL1B
1

Everlight 15 LED Common 2


2

AL1B

11

10

12

7B50-1
BC847BS(COL)

10K

5 3B55-4 4

+24V

1
10K

3 3B55-3 6

FB70

PWM-B2

3B50
+24V

7B50-2
BC847BS(COL) 3

10K

BLUE

BLUE

270R

BLUE

BLUE

BLUE

BLUE

GREEN

GREEN

3B52

GREEN

GREEN

GREEN

GREEN

RED

RED

RED

RED

RED

RED

68R
3B53-1

8
+24V

1K5

1K5
3 3B53-3 6

100n

2 3B53-2 7
FB71

1K5

+24V

4 3B53-4 5
1K5
7B51
BC847BW 3

10K

3 3B57-3 6

7100
99-235/RSBB7C-A24/2D

10K

1 3B55-1 8

7101
99-235/RSBB7C-A24/2D

PWM-G2

7102
99-235/RSBB7C-A24/2D

7103
99-235/RSBB7C-A24/2D

270R
3B51

2B50

7 3B55-2 2

7104
99-235/RSBB7C-A24/2D

7105
99-235/RSBB7C-A24/2D

2
10K

7 3B57-2 2

FB72

PWM-R2

7C20-1
BC847BS(COL) 6

10K

5 3C00-4 4

+24V

1
10K

3 3C00-3 6

FC01

PWM-B3

1 3C10 2
+24V

7C20-2
BC847BS(COL) 3

10K

7 3C00-2 2

1 3C11 2

4
10K

1 3C00-1 8

BLUE

BLUE

Blue

GREEN

GREEN

GREEN

Green

RED

RED

RED

Red

BLUE

3C12

1
3

1 3C15-1 8

1K5
3C15-2

1K5

FC02

PWM-G3

270R

68R

7202
99-235/RSBB7C-A24/2D

7201
99-235/RSBB7C-A24/2D

7200
99-235/RSBB7C-A24/2D

270R

3 3C15-3 6

1K5
4 3C15-4 5
1K5

7C22
BC847BW 3

10K

1 3C06-1 8

+24V

H
PWM-R3

2
10K

7 3C06-2 2

FC03

10

11

12

AL 2K10 Everlight
15 LED Common

2B50 C11
3B50 B7
3B51 B7
3B52 B7
3B53-1 B7
3B53-2 C7
3B53-3 C7
3B53-4 C7
3B55-1 C3
3B55-2 B3
3B55-3 A3
3B55-4 A3
3B57-2 D3
3B57-3 C3
3C00-1 G3
3C00-2 F3
3C00-3 F3
3C00-4 E3
3C06-1 G3
3C06-2 H3
3C10 F4
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
3C15-3 G4
3C15-4 G4
7100 B11
7101 B10
7102 B9
7103 B7
7104 B6
7105 B5
7200 F8
7201 F9
7202 F10
7B50-1 A3
7B50-2 B3
7B51 C3
7C20-1 E3
7C20-2 F3
7C22 G3
FB70 B3
FB71 C3
FB72 D3
FC01 F3
FC02 G3
FC03 H3

2009-11-27

2009-11-03

8204 000 9059


18770_671_100212.eps
100212

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 74

10-6 AL1 820400090601 9 LED Everlight


9 LED Everlight

AL2A

9 LED Everlight

AL2A
4

10

A
7203
99-135/RSGBB7C-A24/2D

7204
99-135/RSGBB7C-A24/2D

1M84

7205
99-135/RSGBB7C-A24/2D

SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN

Blue

BLUE

BLUE

BLUE

Green

GREEN

GREEN

GREEN

PWM-CLOCK-BUF

Red

RED

RED

RED

SPI-CS
LATCH

+24V

100n

+3V3
2D01

1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5

PROG
BLANK
+3V3

TEMP-SENSOR

C
+24V
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27

FH12-25S-0.5SH(55)

B003

10

B004

9 LED Everlight
AL 2K10

2009-11-03

8204 000 9060


3104 313 64191
18770_640_100212.eps
100219

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 75

9 LED Everlight

AL2B

9 LED Everlight
1

AL2B

10

11

12

13

7D01-1
BC847BS(COL)
6

10K

8 3D02-1 1

+24V

FD01
1 3D10 2
+24V

7301
99-135/RSGBB7C-A24/2D

7300
99-135/RSGBB7C-A24/2D

7302
99-135/RSGBB7C-A24/2D

7303
99-135/RSGBB7C-A24/2D

7305
99-135/RSGBB7C-A24/2D

7304
99-135/RSGBB7C-A24/2D

7D01-2
BC847BS(COL)
3

10K

6 3D02-3 3

PWM-R4

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

270R

GREEN

GREEN

GREEN

GREEN

GREEN

GREEN

3D12

RED

RED

RED

RED

RED

RED

1 3D13-1 8
1K5

FD02

2 3D13-2 7
1K5
3 3D13-3 6
1K5

7D02
BC847BW 3

10K

3 3D05-3 6

1K5
2D10

2
10K

5 3D05-4 4

4 3D13-4 5

68R

+24V

PWM-G4

+24V

10K

4 3D02-4 5

270R
3D11

100n

PWM-B4

1
10K

2 3D02-2 7

FD03

FD04

10

11

12

2D10 C13
3D02-1 A1
3D02-2 A1
3D02-3 B1
3D02-4 B1
3D05-3 C1
3D05-4 C1
3D10 A12
3D11 B12
3D12 B12
3D13-1 B12
3D13-2 C12
3D13-3 C12
3D13-4 C12
7300 B5
7301 B6
7302 B7
7303 B8
7304 B10
7305 B11
7D01-1 A2
7D01-2 B2
7D02 C2
FD01 A1
FD02 C1
FD03 D1
FD04 D1

13

9 LED Everlight
AL 2K10

2009-11-03

8204 000 9060


3104 313 64191
18770_641_100212.eps
100212

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 76

10-7 AL1 820400090621 15 LED Everlight


15 LED Everlight

AL2A

15 LED Everlight

AL2A
3

10

A
7203
99-235/RSBB7C-A24/2D

SPI-CLOCK-BUF
SPI-DATA-OUT
SPI-DATA-RETURN

Blue

BLUE

BLUE

BLUE

Green

GREEN

GREEN

GREEN

PWM-CLOCK-BUF

Red

RED

RED

RED

SPI-CS
LATCH

+24V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

100n

+3V3
2D01

1M84

7205
99-235/RSBB7C-A24/2D

7204
99-235/RSBB7C-A24/2D

PROG
BLANK
+3V3

TEMP-SENSOR

C
+24V
FD18

26

1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5
FD18 C7

C
27

B003

B004

10

B005

15 LED Everlight
AL 2K10

2009-11-27

8204 000 9062


3104 313 64211
18770_660_100212.eps
100219

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 77

15 LED Everlight

AL2B

15 LED Everlight
1

AL2B

10

11

12

13

7D01-1
BC847BS(COL)
6

10K

8 3D02-1 1

+24V

2 3D02-2 7

10K

FD01
3D10
+24V

7300
99-235/RSBB7C-A24/2D
7D01-2
BC847BS(COL)
3

10K

6 3D02-3 3

+24V

4 3D02-4 5

PWM-R4

7302
99-235/RSBB7C-A24/2D

7301
99-235/RSBB7C-A24/2D

7305
99-235/RSBB7C-A24/2D

7304
99-235/RSBB7C-A24/2D

7303
99-235/RSBB7C-A24/2D

BLUE

BLUE

BLUE

BLUE

BLUE

BLUE

68R

GREEN

GREEN

GREEN

GREEN

GREEN

GREEN

3D12

RED

RED

RED

RED

RED

RED

68R

10K

4
1 3D13-1 8
1K5

FD02

2 3D13-2 7
+24V

1K5
3 3D13-3 6
4 3D13-4 5
1K5

10K

2D10

1
5 3D05-4 4

1K5

7D02
BC847BW 3

10K

3 3D05-3 6

PWM-G4

68R
3D11 RES

100n

PWM-B4

FD03

+24V

10K

7D03-1
BC847BS(COL)
6

3D04-3

10K

3D04-4

PWM-B5

FD04
3D15
+24V

+24V

10K

7D03-2
BC847BS(COL)
3

7403
99-235/RSBB7C-A24/2D

7402
99-235/RSBB7C-A24/2D

7405
99-235/RSBB7C-A24/2D

7404
99-235/RSBB7C-A24/2D

BLUE

BLUE

BLUE

GREEN

GREEN

GREEN

RED

RED

RED

BLUE

BLUE

BLUE

GREEN

GREEN

GREEN

RED

RED

RED

PWM-R5

RES

68R

10K

4
1 3D18-1 8

3D04-2

68R
3D16

68R
3D17

3D04-1

7401
99-235/RSBB7C-A24/2D

7400
99-235/RSBB7C-A24/2D

1K5
2 3D18-2 7

FD05
+24V

1K5

1K5
4 3D18-4 5
1K5

2
10K

3D03-3

2D11

100n

10K

7D04
BC847BW 3

3D03-4

3 3D18-3 6

PWM-G5

FD06

10

11

12

13

2D10 C13
2D11 H13
3D02-1 A1
3D02-2 A1
3D02-3 B1
3D02-4 B1
3D03-3 H2
3D03-4 G2
3D04-1 F2
3D04-2 G2
3D04-3 E2
3D04-4 F2
3D05-3 C1
3D05-4 D1
3D10 B12
3D11 B12
3D12 B12
3D13-1 B12
3D13-2 C12
3D13-3 C12
3D13-4 C12
3D15 F12
3D16 F12
3D17 F12
3D18-1 G12
3D18-2 G12
3D18-3 G12
3D18-4 G12
7300 B5
7301 B6
7302 B7
7303 B8
7304 B10
7305 B11
7400 F5
7401 F6
7402 F7
7403 F8
7404 F10
7405 F11
7D01-1 A2
7D01-2 B2
7D02 C2
7D03-1 E2
7D03-2 F2
7D04 G2
FD01 A1
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1

15 LED Everlight
AL 2K10

2009-11-27

8204 000 9062


3104 313 64211
18770_661_100212.eps
100212

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 78

10-8 AL1 3104313 - 64201, 64191, 64211


Layout AmbiLight Everlight

AmbiLight Everlight

FC03

7200

3B57

3B57

FB71

3C11
3C10

3C15

7201

7202
3C06

1M84

7203

B003

FC02

7204

7204

B003

7105
7B50

FB70

FB20

3C12

7104

3B53

FB72

7C20

7103

3B51
3B50

7C22

7103

3C00

7102

3B55

7101

7B51

7B26

7B51

2B11

FB35

3B52

7100
2B50

3B18

3B35
3B36

3B37

3B21

B002

FB15

FC01

7005

FB03

B002

FB31

2B03

FB07

FB06

3B22

FB05

B007

7B07

7004
3B00

FB10

FB11

3B31

1M83

3B30

3B01

FB16

FB01

7B06

7003

2B04

7B20

FB13

3B02

FB08

2B17

2B10
2B02
2B20

3B39

FB30

FB12

7002
2B01

FB40

FB41

7B30

2B00

2B09

3B07

3B13

7001

FB04

3B34

3004
2B08
3B11

7B23

7B25

B001

FB32

7000

3B03

18 LED

7205

2C15

7205

3104 313 6420.1

FC02

FC03

FB71

7200
3C11
3C10

3C15

7201

7202

7203

3C06

FD03

7300
3D02

2D01

7D01

7301

7302

FD01

7303

1M84

3D05
FD02

7304
FD04

7305
3D10
3D11

3D12

7105
7B50

FB70

FB20

2D10

7104

3B53

FB72

3D13

3B51
3B50

3C12

7102

3C00

FC01

7101

B004

2B11

7D02

FB35

3B55

7100
2B50

7C20

3B21

3B52

3B03

3B37

7005

FB03

7C22

FB15

FB31

2B03

3B18

FB07

FB06

7B26

FB05

3B22

7B07

7004

B007

FB10

FB11

3B31

3B30

1M83

FB01

7B06

7003

3B00

FB16

FB13

2B04

FB08

7B20

3B02

3B39

FB30

FB12

7002
2B17

2B10
2B02
2B20

FB40

3B01

7001

FB41

7B30

2B01

3B34

2B00

FB04

2B09

3B13

3B07

7B25

3004
2B08
3B11

7B23

B001

FB32

7000

3B35
3B36

24 LED

3104 313 6419.1

FC03

FB71

7201

7202

7203

3C06

7204

7205
2D01

7300
3D02

7D01

FD03

7301

FD01

FD02

3D05

7302

7303

7304

7305
3D10
3D11

FD04

7400
7D03

FD05

FD06

7401

7402

1M84

7403
FD18

7404

7405
3D17
3D15
3D16

3D18

2D11

3C15

B004

3C10

3D03

7200
3C11

3B57

7D04

FC02

3D04

7105
7B50

FB70

FB20

2D10

7104

3D12

3B53

3D13

3B51
3B50

FB72

B005

7103

7D02

7102

3C12

7101

3C00

7B26

B003

2B11

7C20

FB35

3B55

7100
2B50

3B52

FC01

7005
3B21

FB03

3B18

2B03

7C22

FB06

FB15

7B51

FB05

3B22

7004
FB31

3B03

FB11

3B37

FB01

7B06

7B07

FB07

7003

B002

FB10

3B31

3B30

1M83

B007

FB13

3B00

FB16

2B04

7B20

3B02

FB12

7002
2B17

3B01

FB40

FB08

2B10
2B02
2B20

3B39

2B01

7001

FB41

7B30

2B00

FB04

3B34

2B09

3B07

3B13

7B25

FB30

3004
2B08
3B11

7B23

B001

FB32

7000

3B35
3B36

30 LED

3104 313 6421.1

18770_672_100216.eps
100325

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 79

10-9 B01 820400089943 Tuner, HDMI & CI


Common Interface

Common Interface

B01A
1

B01A
4

+3V3
3F01

2F01

22u 16V

RES

2F00

TRANSPORT STREAM FROM CAM

+5VCA

7F00
74LVC245A
1

+T 0R4

19

3F03-2 2

3F03-1

IF02

8
100R

7
100R

CA-CD2n

3EN1
3EN2
G3

CA-DATAENn

100R
CA-MOVAL
CA-MOSTRT

CA-CD1n

IF01

3F02

CA-MOCLK

3
4
5
6
7
8
9

IF03

1
2

18

MOCLK

17
16
15
14
13
12
11

MOVAL
MOSTRT

CA-DATADIR

CA-ADDENn
MOCLK
MOVAL

10

MOSTRT

MDO0

+3V3
2F02

19

MDO1
RES
MDO2

100n

20

7F01
74LVC245A
1

MDO3

3EN1
3EN2
G3

MDO4

IF05
CA-MDO0

3F04-1 1

8 100R

2
IF06

CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

3F04-2
6 100R
3F04-4
8 100R
3F05-2
6 100R
3F05-4

3F04-3 3
3F05-1 1
3F05-3 3

7 100R

5 100R

7 100R

5 100R

3
4
5
6
7
8
9

1
2

18

MDO0

17
16
15
14
13
12
11

MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7

MDO5
MDO6
MDO7

CA-RDY
10

IF07

CA-WAITn
+3V3

CA-INPACKn
2F03

15-BIT ADDRESS

3EN1
3EN2
G3
18

XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07

17
16
15
14
13
12
11

CA-WP

1
2

CA-VS1n

1
19

CA-ADDENn

CA-A00

3
4
5
6
7
8
9

CA-A01
CA-A02
CA-A03
CA-A04
CA-A05
CA-A06
CA-A07

10

XIO-A00

RES

100n

20

7F02
74LVC245A

3F06

CA-RST
RES

100n

20

+5V

20
3EN1
3EN2
G3

18

XIO-A08

1
2

17
16
15
14
13
12
11

XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14

1 3F08-1 8
10K
2 3F08-2 7
10K
3 3F08-3 6
10K
4 3F08-4 5
10K
1 3F09-1 8
10K
2 3F09-2 7
10K
3 3F09-3 6
10K
4 3F09-4 5
10K
1

B
IF04

3F10-1

8
10K
7
10K
3F10-3
3
6
10K
4 3F10-4 5
10K

3F10-2

3F12
+3V3

10K
2 3F11-2 7
10K
3F11-3
3
6
10K
4 3F11-4 5
10K
3F11-1
8
1
10K

IF08

+5VCA

+3V3

CA-D03
CA-D04
CA-D05
CA-D06
CA-D07
CA-CE1n
CA-A10
CA-OEn
CA-A11
CA-A09
CA-A08
CA-A13
CA-A14
CA-WEn
CA-RDY

1
19

CA-ADDENn

CA-A08

3
4
5
6
7
8
9

CA-A09
CA-A10
CA-A11
CA-A12
CA-A13
CA-A14

CA-MIVAL
CA-MICLK
CA-A12
CA-A07
CA-A06
CA-A05
CA-A04
CA-A03
CA-A02
CA-A01
CA-A00
CA-D00
CA-D01
CA-D02
CA-WP

ROW_A
1P00-A
GND1
1
D3
2
D4
3
D5
4
D6
5
D7
6
CE1
7
A10
8
OE
9
A11
10
A9
11
A8
12
A13
13
A14
14
WE|P
15
RDY|BSY
16
VCC1
17
VPP1
18
A16
19
A15
20
A12
21
A7
22
A6
23
A5
24
A4
25
A3
26
A2
27
A1
28
A0
29
D0
30
D1
31
D2
32
WP|IOIS16
33
GND2
34
70 69

10

RES

100n

+3V3

+5VCA
2F04

11

100K

4 3F07-4 5
10K
2 3F07-2 7
10K
3F07-3
3
6
10K
3F07-1
1
8
10K

+3V3

7F03
74LVC245A

10

10074595-050MLF
+3V3
2F05

8-BIT DATA
20

3EN1
3EN2
G3
18

XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

17
16
15
14
13
12
11

1
2

CA-DATADIR

19

CA-DATAENn

CA-D00

3
4
5
6
7
8
9

CA-D01
CA-D02
CA-D03
CA-D04
CA-D05
CA-D06
CA-D07

CA-CD1n
MDO3
MDO4
MDO5
MDO6
MDO7
CA-CE2n
CA-VS1n
CA-IORDn
CA-IOWRn
CA-MISTRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
+5VCA

10

XIO-D00

RES

7F04
100n
74LVC245A
1

+3V3
2F06

CONTROL
3EN1
3EN2
G3
18

XIO-D11

1
2

17
16
15
14
13
12
11

1
19

CA-ADDENn

CA-REGn

3
4
5
6
7
8
9

CA-CE1n
CA-CE2n
CA-OEn
CA-WEn
CA-IORDn
CA-IOWRn
XIO-D10

1X04
REF EMC HOLE

1X01
REF EMC HOLE

10074595-050MLF

10

XIO-D09
XIO-D08
XIO-OEn
XIO-WEn
XIO-D14
XIO-D15
CA-WAITn

RES

100n

20

7F05
74LVC245A

CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
MOCLK
CA-RST
CA-WAITn
CA-INPACKn
CA-REGn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
CA-CD2n

ROW_B
1P00-B
GND3
35
CD1
36
D11
37
D12
38
D13
39
D14
40
D15
41
CE2
42
VS1
43
IORD
44
IOWR
45
A17
46
A18
47
A19
48
A20
49
A21
50
VCC2
51
VPP2
52
A22
53
A23
54
A24
55
A25
56
VS2
57
RESET
58
WAIT
59
INPACK
60
REG
61
BVD2|SPKR
62
BVD1|STSCHG
63
D8
64
D9
65
D10
66
CD2
67
GND4
68
72 71

1P00-A D10
1P00-B G10
2F00 A6
2F01 A2
2F02 B6
2F03 D6
2F04 E6
2F05 G6
2F06 H6
3F01 A2
3F02 A4
3F03-1 A4
3F03-2 A4
3F04-1 C4
3F04-2 C4
3F04-3 C4
3F04-4 C4
3F05-1 C4
3F05-2 C4
3F05-3 C4
3F05-4 C4
3F06 A9
3F07-1 A9
3F07-2 A9
3F07-3 A9
3F07-4 A9
3F08-1 A9
3F08-2 A9
3F08-3 B9
3F08-4 B9
3F09-1 B9
3F09-2 B9
3F09-3 B9
3F09-4 B9
3F10-1 C9
3F10-2 C9
3F10-3 C9
3F10-4 C9
3F11-1 D9
3F11-2 C9
3F11-3 D9
3F11-4 D9
3F12 C9
7F00 A5
7F01 B5
7F02 D5
7F03 E5
7F04 G5
7F05 I5
IF01 A4
IF02 A5
IF03 A4
IF04 B9
IF05 C4
IF06 C5
IF07 C5
IF08 D9

10

11

TUNER, HDMI & CI

2009-10-22

8204 000 8994


18770_500_100118.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 80

Flash

Flash

B01B
2

4
2F20 A3
2F21 A3
3F19 D2

+3V3

3F20-1 1

3F20-3 3

3F21-1 1

3F21-3 3

100R
3F20-2
100R
3F20-4
100R
3F21-2
100R
3F21-4

100R

100R

100R

100R

3F22-2
+3V3

XIO-OEn
XIO-WEn
NAND-WPn

3F23
3F22-4

100R
3F22-3 3
10K
3F22-1 1
5 100R

16
17
9
8
18
19
7

100R

100R
IF22

3F24

+3V3
NAND-RDY1n

0
1
2
3
IO
4
5
6
7

CLE
ALE
CE
RE
WE
WP
R
B

2K2

10K

13

VSS

1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
27
28
33
34
35
38
39
40
45
46
47
48

3F23 C2
3F24 D2
7F20 B3

IF21 C3
IF22 D3
IF23 D3

36

3F19

IF23

3F22-2 C1
3F22-3 C2
3F22-4 C2

37
VCC

NC

IF21

NAND-CE1n
NAND-CLE
NAND-ALE

29
30
31
32
41
42
43
44

3F21-3 C1
3F21-4 C2
3F22-1 C2

[FLASH]
4Gx16
XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07

12

7F20
NAND04GW3B2DN6F

3F20-4 C2
3F21-1 C1
3F21-2 C2

100n

100n
2F21

2F20

3F20-1 B1
3F20-2 B2
3F20-3 B1

+3V3

B01B

4
3

TUNER, HDMI & CI

2009-10-22

8204 000 8994


18770_501_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 81

USB Hub

B01C

USB Hub

B01C

IF44

1F24 E9
1F25 B1
1P07 B9
1P08 D9
2F25 A2
2F26 A2
2F27 A2
2F28 A4
2F29 A4
2F30 A4
2F31 A5
2F32 A5
2F33 A5
2F34 B1
2F35 B2
3F25 A8
3F26-1 A8
3F26-2 A8
3F26-3 A8
3F26-4 B8
3F28 B2
3F30 C2
3F31-2 C2
3F31-3 C2
3F31-4 D2
3F32 C8
3F34-1 C8
3F34-2 C8
3F34-3 D8
3F34-4 D8
3F35 B1
3F36 D6
7F25 B2
9F20 B7
9F21 B7
9F25 B8
9F26 B8
FF30 E8
FF31 E9
FF32 E9
FF33 C9
FF34 C7
FF35 C7
FF36 D7
FF37 D7
FF38 E9
FF39 E8
FF40 A8
IF30 C2
IF31 C1
IF32 C1
IF33 B2
IF34 B2
IF35 B5
IF36 C5
IF37 C5
IF39 D2
IF40 C2
IF41 C2
IF42 C2
IF43 A3
IF44 A3
IF45 D9

+5V
+T 0R4

3F25

100n

2F25

+3V3

FF40

3F26-1

+5V-USB1

100K
IF43
2

USB-OC1n

3F26-2

100n

100n
2F33

100n
2F32

100n
2F31

100n
2F30

1u0
2F29

2F28

1u0

100n
2F27

2F26

100K
3

IF42

10K

IF31
IF32

+3V3
3F30
3

3F31-3
10K

IF41

12K IF40

6
4

3F31-4

IF39

28
31
30
27
35
22
24
25

36
23
15
5
10
29

RESET
OSC2
USBDP_DN2|PRT_DIS_P2
TEST
USBDM_DN2|PRT_DIS_M2
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2
DP
USBUP
DM
VBUS_DET

USB-DP2

USB-DM

9F26

USB-DM2

OSC3
USBDP_DN3|PRT_DIS_P3
USBDM_DN3|PRT_DIS_M3
BC_EN3|PWRTPWR3

RBIAS
SDA|SMBDATA|NON_REM1
SCL|SMBCLK|CFG_SEL0
HS_IND|CFG_SEL1

NC

13
2
1
12

USB-OC1n
USB-DP1
USB-DM1
IF36

17
4
3
16

USB-OC2n
USB-DP2
USB-DM2

USB-DM1
USB-DP1

1P07

FF34
FF35
+5V

19
7
6
18

USB-OC3n
USB-DP3
USB-DM3
1

8
9
20
21

3F34-1

C
FF33

+5V-USB2

100K
2

USB-OC2n

3F34-2

100K
3

38
39
40
41

1
2
3
4

292303-4

IF37

VIA

37

SIDE USB BOTTOM


+5V-USB1

10K
GND_HS

IF35

OSC1
USBDP_DN1|PRT_DIS_P1
USBDM_DN1|PRT_DIS_M1
BC_EN1|PWRTPWR1

XTALOUT

9F25

+T 0R4

26

XTALIN|CLKIN

USB-DP

3F32

32

VDD_3V3

USB HUB

9F20

33

11

USB-DP
USB-DM

9F21

10p

IF33

RESET-USBn

34

CR PLL
FILT

IF30

3F31-2

14

1M0

3F28

7F25
USB2513B-AEZG

IF34

3F26-4
100K

24M

10p

10K
2F34

3F35

4
2

1F25

2F35

100K
4

+3V3

3F26-3

+3V3

3F36

100K
USB-OC3n
4

10K

3F34-3

3F34-4

SIDE USB TOP

100K

1P08
+5V-USB2

FF36
FF37

USB-DM2
USB-DP2

FF32

1
2
3
4 IF45

292303-4

FF38

1F24

+5V

FF39

USB-DM3
USB-DP3

FF30
FF31
7

1
2
3
4
5

502382-0570

TUNER, HDMI & CI

2009-10-22

8204 000 8994


18770_502_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 82

SD Card

B01D

SD Card

B01D
1

A
3F40
+3V3
22u 16V

2F40

+T

FF45

+3V3-SD

0R4

B
+3V3

3F41-2

IF47

47K

SDIO-DAT3
3

3F41-3

SDIO-CMD

SDIO-DAT3

3F44-2

FF47

100R

SDIO-CMD

47K

SDIO-CLK

SDIO-CLK

3F41-1

47K
1

3F42-1

3F41-4

47K

SDIO-DAT0

SDIO-DAT0

SDIO-DAT1

SDIO-DAT1

SDIO-DAT2

SDIO-DAT2

47K

+3V3-SD

1 3F44-1 8

10K
1

1P09-1
FF48

100R

3F45 RES

3F43-2

100R
3F43-3
100R

3F44-3

FF49
FF41

6
1
6

3F43-1

100R

FF42

1314

FF43

1939115-1

3F42-2

FF46

1P09-2
7

SDIO-CDn

SDIO-CDn

FF44

SDIO-WP

SDIO-WP

FF50

10
11
12

47K
3

100R

2
3F42-3

1
2
3
4
5
6
7
8
9

IF46

1P09-1 C4
1P09-2 D4
2F40 A2
3F40 A2
3F41-1 C1
3F41-2 C1
3F41-3 C1
3F41-4 C1
3F42-1 C1
3F42-2 D1
3F42-3 D1
3F43-1 C3
3F43-2 C3
3F43-3 C3
3F44-1 C3
3F44-2 C3
3F44-3 C3
3F45 C1
FF41 C3
FF42 C3
FF43 C3
FF44 D3
FF45 A2
FF46 C4
FF47 C3
FF48 C3
FF49 C3
FF50 D3
IF46 D1
IF47 B1

1939115-1

47K

TUNER, HDMI & CI

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 83

PNX85500 Control

B01E

PNX85500 Control

B01E

A
+3V3-STANDBY

IF52
6

10K
RES

IF53
PNX-SPI-CSBn
IF54
3

HOLD

+5V

PNX-SPI-CLK

BACKLIGHT-BOOST
7F53 RES
PDTA114EU

PNX-SPI-SDO

RES

512K
FLASH

PNX-SPI-WPn
+3V3-STANDBY
FF29

VSS

3F66
3F67

IF50
5

IF55

BOOST-PWM

IF61

47K

3F68

+3V3

+3V3

10K

7F52
M25P05-AVMN6

VCC
IF51

3F52

B
PNX-SPI-SDI

+3V3

100n
RES

10K

2F52

3F51

+3V3-STANDBY

10K
RES

+3V3-STANDBY

7F54-1 RES
BC847BPN(COL) 6

7F54-2 RES
BC847BPN(COL)

SPI-PROG

IF56
4

IF57

FF04

IF62
SDM

3F54

RES

3F69

FF58

RES

10K

1u0

2F53

MAIN NVM

+3V3

RES

9CH0

10K

1K0
RES

3F53

DEBUG ONLY
IF58

2F58 RES

3F58

10K

IF59

1
2
3

0
1
2

100R

SDA-SSB
3F63

FF63

WC
SCL

ADR
SDA

100R

SCL

1
2
3

SDA
5

7
6
5

FF55

3F59
100R

3F60

SCL-UP-MIPS

FF56

SDA-UP-MIPS

100R

(8K8)
EEPROM

1F52

3F62

FF62

100n
7F58

FF61

SCL-SSB

FF57

LEVEL

DEBUG / RS232 INTERFACE

SHIFTED
TXD-UP
RXD-UP
RESET-STBYn
SPI-PROG

FF65

3F64

FF66

100R

1F51
FF64

3F65
100R

1
2
3
4
5

UP

FOR
DEBUG
USE ONLY

1F51 F8
1F52 D8
2F52 B1
2F53 D6
2F58 D2
3F51 B1
3F52 B3
3F53 C6
3F54 D7
3F58 E1
3F59 E3
3F60 E3
3F62 D5
3F63 E5
3F64 F5
3F65 F5
3F66 B7
3F67 B6
3F68 C7
3F69 D7
7F52 B2
7F53 B7
7F54-1 C7
7F54-2 C7
7F58 D1
9CH0 C7
FF04 C4
FF29 C4
FF55 E3
FF56 E3
FF57 E2
FF58 C7
FF61 D4
FF62 D7
FF63 E4
FF64 F7
FF65 F4
FF66 F4
IF50 B3
IF51 B1
IF52 B3
IF53 B3
IF54 C3
IF55 C6
IF56 C7
IF57 C7
IF58 D2
IF59 E1
IF61 C4
IF62 C4

9
3

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 84

HDMI & CI

HDMI & CI

B01F
1F75 B5
1T01 A1
2F59 B1
2F60 B1
2F61 B1

B01F
2F80 B9
2F81 B1
2F82 B9
2F84 C1
2F85 C4

2F75 B8
2F76 B9
2F77 B9
2F78 B6
2F79 B8

2F70 B10
2F71 A7
2F72 A9
2F73 A9
2F74 B6

2F62 B10
2F63 C9
2F64 C9
2F65 B10
2F66 C10

2F86 D1
2F88 E5
2F90 C6
2F91 D6
2F92 C7

2F93 C2
2F94 D7
3F71 C7
3F72 C7
3F75 D2

3F76 C2
3F77 C4
3F78 C7
3F79-1 B8
3F79-4 B8

3F80 C9
3F81 C9
3F82 B10
5F66 C10
5F70 D6

5F71 B9
5F72 E4
5F73 C5
5F74 B10
5F76 B10

6F72 C7
7F70 D8
7F75 A6
9F00 A6
9F01 A6

9F02 A8
9F03 A8
9F04 B3
9F05 C4
9F06 C4

FF00 B2
FF01 C4
FF71 A1
FF74 B1
FF75 B2

9F71 E4
AF70 B3
AF71 B3
AF72 B9
AF73 B9

FF76 B1
FF81 C1
FF82 C2
IF10 A5
IF11 A5

IF12 C9
IF13 C9
IF14 C9
IF15 C9
IF16 B10

IF82 C4
IF86 C5
IF87 C2
IF88 D2
IF89 D5

IF77 B6
IF78 B8
IF79 C5
IF80 B8
IF81 B6

IF72 C5
IF73 B6
IF74 B8
IF75 B6
IF76 B8

IF90 D7

10

IF10
IF11

220R

15p

2F65
1p0

10p
2F70

820n
2F62

5F74

22p

AF73

820R

IF16

330n
3F82

10n

5F76

AGC CONTROL

3F79-4

1p0

10n

IF80

15p
2F82

2F79

3F79-1
220R

10n
IF78

1p0

AF72
1

2p2 RES
2F77

IF76

15p
2F73

2F72

9F03

9F02

2F75

2F76

VAGC

OUTPUT2

IF74

680n

5F71

INPUT2

VCC

OUTPUT1

2F80

IF-AGC

IF77

INPUT1

GND2

X7251X
36M17

10n
2F78

IF81

GND

IF73

4u7

100n

4u7

RES
2F60

TUN-IF-N
TUN-IF-P

4
O1
5
O2

I
IGND

2F74

GND1

9F00

NC

IF75

PNX-IF-P

FF75

3F75

15p

47R

IF88

TUN-IF-N

SDA-TUNER

TUN-IF-P

5F73

2
1

ATB2012

10n

2F64

IF15

2F66

IF+

10n

2F91

TUN-P7

10n

1K0
2F92

3F71
10n

TUN-P6

IF14

3K3

2F86

SCL-TUNER

3F78

47R

220R

IF-

10n

470n

15p

IF87

5F70

3F76

3F72

IF13

2F90

IF86
2F84

BA591

3F81

2F63

22p

+5V-TUN-PIN

9F06

9F05

47n

IF72
2F85

IF12

220R

FF01

+5V-TUN-PIN

IF-AGC

3F80

IF79

4K7

680n

3F77

5F66

IF82

6F72

PNX-IF-AGC

FF82

4K7

100n

2F93

PNX-IF-N

FF81

TUN-P6
TUN-P7

12

11

10

1
RES

2F59

2F81

2F61

9F04

10n
7F75
UPC3221GV-E1

1
2

AF71
AF70

FF76
FF00

4n7

FF74

+5V-TUN-PIN

13

1F75

TUN-P1

2F71

9F01

14
IF_OUT2

B+_TUN

I2C_SDA

I2C_SCL

TUN

RF_AGC

B+_LNA

RF_IO

16

I2C_ADR

TUNER

15

IF_OUT1

FF71

4MHZ_REF

1T01
TX31XX

RES

IF89
IF90

RES
2F94

SELECT-SAW

7F70
PDTC114EU

10n

9F71

5F72
+5V-TUN-PIN

+5V-TUN

22u

RES
2F88

30R

10
3

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 85

Toshiba Supply

B01G

Toshiba Supply

B01G

2FA2 C1
2FA3 C2
2FA4 C3
5FA3 B2
5FA4 B3
7FA3 B2
FFA2 C2
FFAF B2

+1V2-BRA-DR1

+3V3

+1V2-BRA-VDDC

B
5FA4

30R
10u

2FA4

OUT

30R

IN

100n

5FA3

7FA3
LD1117DT12

2FA3

B
FFAF

100n

2FA2

COM

FFA2

Not yet implemented


1

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 86

HDMI

B01H

HDMI

1P05 B1

B01H
3FBF-1 C4

3FBF-2 C4

FFB1 C2

FFB2 C2

FFB3 C2

FFB4 C2

FFB5 C1

FFB6 C2

HDMI CONNECTOR SIDE


1P05

DRX2DRX1+

DRX0DRXC+
DRXCPCEC-HDMI
FFB1
FFB2

DRX-DDC-SCL
DRX-DDC-SDA

DRX-DDC-SCL
DRX-DDC-SDA

47K

DRX1DRX0+

3FBF-2
47K

FFB3
FFB4

DIN-5V

DRX-HOTPLUG

DIN-5V

20
23 22

DIN-5V

1 3FBF-1 8

DRX2+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FFB5 21

FFB6

4
3

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 87

VGA

B01I

VGA

B01I

A
3FC5
CDS4C12GTA
12V

RES 6FC1

1FC1

100p

2FC1

FFC1

FFC2

RES 6FC2

1FC2

100p

2FC2
1E05

FFC4

CDS4C12GTA
12V

RES 6FC3

1FC3

100p

2FC3

FFC3

FFC6

1216-00D-15S-1EF

B-VGA

C
9FC5

H-SYNC-VGA

9FC6

V-SYNC-VGA

4K7

3FC3

CDS4C12GTA
12V

RES 6FC4

1FC4

16
17

6FC7

47p

2FC7

4K7

CDS4C12GTA
12V

FFC9

10K

D
9FC1

VGA-SDA-EDID-HDMI

9FC2

VGA-SDA-EDID

RES

CDS4C12GTA
12V

6FC6

47p

2FC6
RES
3FC2

3FC4

FFC8

10K

CDS4C12GTA
12V

RES 6FC5

1FC5

2FC5
RES
3FC1

47p

FFC7

18R

FFC5

47p

G-VGA

18R

3FC7

2FC4

VGA
CONNECTOR

CDS4C12GTA
12V

3FC6

B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

R-VGA

18R

9FC3

VGA-SCL-EDID-HDMI

9FC4

VGA-SCL-EDID

RES

CDS4C12GTA
12V

6FC8

1FC6

47p

2FC8

+5V-VGA

1E05 B2
1FC1 B4
1FC2 B4
1FC3 C4
1FC4 C4
1FC5 D4
1FC6 F4
2FC1 B4
2FC2 B4
2FC3 C4
2FC4 C4
2FC5 D4
2FC6 E4
2FC7 E4
2FC8 F4
3FC1 D3
3FC2 E3
3FC3 C6
3FC4 D6
3FC5 A6
3FC6 B6
3FC7 C6
6FC1 B5
6FC2 B5
6FC3 C5
6FC4 C5
6FC5 D5
6FC6 E5
6FC7 E5
6FC8 F5
9FC1 D6
9FC2 E6
9FC3 E6
9FC4 E6
9FC5 C6
9FC6 D6
FFC1 A4
FFC2 B4
FFC3 C4
FFC4 C3
FFC5 C4
FFC6 D2
FFC7 D4
FFC8 D4
FFC9 E4

9
3

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 88

Temp Sensor + Headphone

B01J

Temp Sensor + Headphone

B01J
3

IFD4

1K0

3FD2 RES

9FD2

9FD1

100n

2FD1
2

SDA

A1

SCL

A2

IFD1

IFD3

IFD5

100R

A0

9FD5

100R

OS

1K0

3FD4

SCL-SSB

1K0
3FD7 RES

SDA-SSB

IFD2

3FD6 RES

3FD3

+VS

7FD1
LM75BDP

GND

6FD1

RES

1K0

RES

LTST-C190KGKT

3FD1

+3V3

C
1329

1
2
3

502382-0370

FFDA

1n0

FFDB
1n0
2FDD

CDS4C12GTA
12V
2FDC

6FD3

CDS4C12GTA
12V
1FD3

6FD2

1FD2

1K0

7
1K0

3FDG-2
2

3FDG-1

AMP1
AMP2

2
3
1

1328

FFDC
MSJ-035-29D PPO (PHT)

1328 D6
1329 C6
1FD2 D4
1FD3 D5
2FD1 A4
2FDC D5
2FDD D5
3FD1 A3
3FD2 B5
3FD3 B3
3FD4 B2
3FD6 C4
3FD7 C4
3FDG-1 D4
3FDG-2 D4
6FD1 B3
6FD2 D4
6FD3 D5
7FD1 B3
9FD1 A4
9FD2 A4
9FD5 C5
FFDA D5
FFDB D5
FFDC D6
IFD1 B4
IFD2 B3
IFD3 B4
IFD4 B3
IFD5 B4

9
3

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 89

Tuner Brazil

Tuner Brazil

B01K

B01K

10

12

11

13

A
5FE0

IF63

IF64

+2V5-BRA

+1V2-BRA-VDDC

+3V3-BRA-FLT

1u0

100n
2FF1

100n
2FF0

100n
2FE5

2FE3

100n
2FE4

1u0

2FE0

30R

AGND
5FE3

IF66

IF65

+3V3-BRA-FLT

5FE4
+3V3-BRA

30R

1u0

100n
2FF6

100n
2FF5

100n
2FF4

2FF2

100n
2FF3

1u0

2FE6

30R

AGND
5FE5

IF67

IF68
+1V2-BRA-DR1
IF48

5FE7

+3V3-BRA

+3V3

1u0

100n
2FF9

100n
2FF8

2FF7

1u0

2FE8

30R

30R

5FE8

IF69

+2V5-BRA
7FE3
LD3985M25

5FE9

+5V
30R

18p

2FG3

18p

2FG2

25M4
4 2

1u0

2FG0

100n
2FG1

30R
1FE0

IN

OUT

INH

BP

FF03

+2V5-BRA

30
29

100n

BFE1
BFE2

28
27

100n
2FH6

100n

BFE3
BFE4

2FH7

100n

BFE5

10n
2FG6

2FG7
AGND

2FG9

100n
2FG8

AGND

10n

24
25
26
39

AGND

0
XSEL
1

PBVAL
RERR
RLOCK

P
ADI_AI
N

RSEORF

P
ADQ_AI
N

SBYTE
SLOCK

P
AD_VREF
N

SRCK

AD_VREF

SRDT
STSFLG1

DTCLK

1n5

3FG6-4

11
3FE8

100R
3FE9

IF49
100R

45
46

SLADRS

CKI
SCL
SDA

23

SCL-SSB
SDA-SSB

SYRSTN
AGCI

AGND

TN

0
1

SCL
SDA

33R

1u0

10n

2FH4

TS-FE-VALID
4

9F27-4

TS-DVBS-VALID

DFE8

55
59

3FG6-3

9F27-2

TS-DVBS-SOP

33R

TS-FE-SOP

DFE9

52

9F28

61

3FG7
3FG6-2

60

33R

33R

3FE5
18K

DFF2

51

30R

TS-FE-DATA
1

10

5FG0

TS-FE-CLOCK

DFF1

38

TS-DVBS-CLOCK

9F27-1

5FG2

TS-DVBS-DATA

30R

IF28

AGND

IF-AGC

42
6
5

3FG2-1

RESET-SYSTEMn
10K

3FG2-2

12
14

4K7

3FG4-1
4K7

VSS

10K

3FG4-2

+3V3-BRA-FLT

4
15
33
37
44
47
50
57
62

STSFLG0

PLLVSS

10K IF29

0
TSMD
1

AD_DVSS

3FE7

1
41

10K

AGCCNTR

31

3FE6

AGCCNTI

DTMB
S_INFO

17

AD_AVSS

40

DFE7

54

IF27
+3V3-BRA-FLT

AGND

DFE6

53

2FH3

2FH5

21
58

1u0

43
FIL

2FH2

VDDS

DR2VDD

16
36
56
63

22

13
35
49
64

34
DR1VDD 48

VDDC

10n

IF17
IF18

2FG4

IF+
IF-

2FH8

3
2

PLLVDD

18

AD_AVDD

19

32

7FE0
TC90517FG

AGND

AD_DVDD

AGND

20

COM
AGND

AGND

Not yet implemented


1

10

11

12

1FE0 C2
2FE0 A3
2FE3 A6
2FE4 A6
2FE5 A6
2FE6 B3
2FE8 C3
2FF0 A6
2FF1 A7
2FF2 B6
2FF3 B6
2FF4 B6
2FF5 B6
2FF6 B7
2FF7 C6
2FF8 C6
2FF9 C7
2FG0 C6
2FG1 C7
2FG2 C1
2FG3 C2
2FG4 D3
2FG6 D3
2FG7 E3
2FG8 E3
2FG9 E3
2FH2 D11
2FH3 D12
2FH4 D12
2FH5 D6
2FH6 E3
2FH7 E3
2FH8 E7
3FE5 E7
3FE6 F3
3FE7 F3
3FE8 F3
3FE9 F3
3FG2-1 F6
3FG2-2 F7
3FG4-1 F7
3FG4-2 F6
3FG6-2 E7
3FG6-3 E7
3FG6-4 D7
3FG7 E7
5FE0 A3
5FE3 B3
5FE4 B7
5FE5 B3
5FE7 C11
5FE8 C7
5FE9 C11
5FG0 E11
5FG2 E11
7FE0 D4
7FE3 C11
9F27-1 E8
9F27-2 D8
9F27-4 D8
9F28 E8
BFE1 E4
BFE2 E4
BFE3 E4
BFE4 E4
BFE5 E4
DFE6 D6
DFE7 D6
DFE8 D6
DFE9 E6
DFF1 E6
DFF2 F6
FF03 C12
IF17 D4
IF18 D4
IF27 E7
IF28 E7
IF29 F4
IF48 C12
IF49 F4
IF63 A4
IF64 A5
IF65 B4
IF66 B5
IF67 B4
IF68 B5
IF69 C6

13

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 90

10-10 B02 820400089506 PNX85500


PNX NandFlash - Conditional Access

B02A

PNX NandFlash - Conditional Access

B02A

10

11

12

13

14

7S00-5
PNX85500

FLASH

NAND-ALE
NAND-CLE

D22
ALE
C21
NAND
CLE

XIO-A00
XIO-A01
XIO-A02
XIO-A03
XIO-A04
XIO-A05
XIO-A06
XIO-A07
XIO-A08
XIO-A09
XIO-A10
XIO-A11
XIO-A12
XIO-A13
XIO-A14
XIO-A15

J25
J26
H21
H22
H23
H24
H25
H26
G21
G22
G23
G24
G25
G26
F22
F23

IS25

00
01
02
03
04
05
06
07
XIO_A
08
09
10
11
12
13
14
15

D25
D26
C24
D23
C23
B23
A22
E22
F24
F25
F26
E23
E24
E25
E26
D24

XIO-D00
XIO-D01
XIO-D02
XIO-D03
XIO-D04
XIO-D05
XIO-D06
XIO-D07
XIO-D08
XIO-D09
XIO-D10
XIO-D11

B22
OE_
C22
XIO
WE_

XIO-OEn
XIO-WEn

00
01
02
03
04
05
06
07
XIO_D
08
09
10
11
12
13
14
15

CLK_BURST

INPACK
XIO-D14
XIO-D15

B
INPACK

IS26

3S15
10K

B21

E21
CE1_
D21
CE2_
A20
NAND RDY2
F21
RDY1
A21
WP_

NAND-CE1n

NAND-RDY1n
NAND-WPn

9S08
IS00

3S01-1 E2
3S01-2 E3
3S01-3 E2
3S01-4 E3
3S02-1 E3
3S02-2 E2
3S02-3 E2
3S02-4 E3
3S03 F3
3S04-1 F3
3S04-2 F3
3S15 B6
3S1R F7
3S1S G7
3S1T G7
3S1U G7
3S23 G7
3S24 G7
3S28 G7
3S29 H7
7S00-11 E3
7S00-5 A4
9S00 F5
9S08 C5
IS00 C5
IS25 C3
IS26 B6

7S00-11
PNX85500
3S01-1 8
33R
3S01-3 6

CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7

7 3S01-2 2
3 33R
33R 5 3S02-4 4
3S02-2
33R
7
2
33R 8 3S02-1 1
6
3 33R
3S02-3
33R 5 3S01-4 4
33R

P21
P22
P23
P24
P25
P26
N21
N22

CA-ADDENn

J22

CA-DATADIR

K25

CA-DATAENn

K26
3S03

CA-MICLK

N23
10R
L25

CA-MOCLK
7

CA-MISTRT
8
33R

CA-MIVAL

3S04-1

3S04-2

2
33R

N24
N25

CA-MOSTRT

L22

CA-MOVAL

L23
J21

CA-RDY

L24

CA-RST

L26
J23
J24

VIDEO_STREAM

0
1
2
3
MDI
4
5
6
7

0
1
2
3
MDO
4
5
6
7

N26
M21
M22
M23
M24
M25
M26
L21

CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7

ADD_EN
DATA_DIR

VS

DATA_EN

CA-VS1n
CA-MOCLK

9S00 *
RES

K21
1
CD
K22
2

I
MCLK

K23
1
K24
2

CA-CD1n
CA-CD2n

CA

+3V3

MISTRT
MIVAL

TS-FE-DATA

3S1R

MOSTRT

TS-FE-CLOCK

3S1S

MOVAL

TS-FE-VALID

3S1T

OOB_EN

TS-FE-SOP

3S1U

560R
560R
560R
560R

RDY
RST
VCCEN
VPPEN

TS-FE-DATA

T21
DATA
T23
ERR
T22
TNR_SER1 MICLK
R23
MIVAL
R22
SOP

TS-FE-ERR
TS-FE-CLOCK
TS-FE-VALID
TS-FE-SOP

TS-FE-DATA
TS-FE-CLOCK
TS-FE-VALID

3S23
RES
3S24
RES
3S28
3S29

TS-FE-SOP

1X06
EMC HOLE

470R
470R
470R
470R

10

11

12

13

14
6

PNX85500

2009-12-07

8204 000 8950


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100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 91

PNX SDRAM

B02B

PNX SDRAM

B02B
2

10

11

F3
C2
F2
C3
B4
F1
C1
E1
F4
B2
E5
C5
A4
G5
B3
F5
U3
P2
U2
P3
N1
U1
P1
T1
V4
R5
U5
P5
N3
V3
R4
V5

FS02

2S12

100u 2.0V

3S06

180R 1%

3S20

180R 1%

+1V8

FS01

3S07

DDR2-VREF-CTRL2
180R 1%

3S22

180R 1%

DDR2-VREF-CTRL3

CLK

N
P

DQS0

N
P

DQS1

N
P

DQS2

N
P

DQS3

N
P

CASB
CKE
CSB
ODT
PCAL
RASB
WEB
1
VREF
2

N5
N4

DDR2-CLK_N
DDR2-CLK_P

3S30
10R

3S33
10R

E2
E3

DDR2-DQS0_N
DDR2-DQS0_P

D3
D4

DDR2-DQS1_N
DDR2-DQS1_P

R1
R2

DDR2-DQS2_N
DDR2-DQS2_P

T3
T4

DDR2-DQS3_N
DDR2-DQS3_P

K3
K4
L5
M4
M1
M5
H3

DDR2-CAS
DDR2-CKE
DDR2-CS
DDR2-ODT
DDR2-RAS
DDR2-WE

A2
V1

DDR2-CKE

3S6Q
10K

DDR2-ODT

3S6P
10K

DDR2-VREF-CTRL2
DDR2-VREF-CTRL3

3S0V

2S24

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DQ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

1%

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D6
DDR2-D5
DDR2-D4
DDR2-D7
DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15
DDR2-D16
DDR2-D17
DDR2-D19
DDR2-D18
DDR2-D22
DDR2-D23
DDR2-D20
DDR2-D21
DDR2-D24
DDR2-D30
DDR2-D26
DDR2-D25
DDR2-D28
DDR2-D31
DDR2-D27
DDR2-D29

M0

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13
DDR2-A14

IS42
261R

0
1
DM
2
3

J1
J3
K1
G4
L3
G3
L2
H5
L1
J5
J2
M3
J4
M2
K5

100p

D1
D5
R3
T5

0
1
2
3
4
5
6
7
A 8
9
10
11
12
13
14

100n
2S25

DDR2-DQM0
DDR2-DQM1
DDR2-DQM2
DDR2-DQM3

MEMORY

0
1 BA
2

100n
2S17

DDR2-BA2

H1
H2
G1

DDR2-BA0
DDR2-BA1

100p
2S20

7S00-8
PNX85500

2S12 D4
2S17 E7
2S20 E7
2S24 E7
2S25 E7
A 3S06 D3
3S07 D3
3S0V F8
3S20 D2
3S22 D2
B 3S30 C7
3S33 C8
3S6P E10
3S6Q E10
7S00-8 B6
C FS01 D3
FS02 D2
IS42 E8

10

11

PNX85500

2009-12-07

8204 000 8950


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100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 92

PNX Digital Video In

B02C
1

PNX Digital Video In


2

B02C

10

11

12

13

14

2S2E F5
3S0W E5
7S00-6 D6
IS01 E6
IS10 E7

D
7S00-6
PNX85500
T25
T26

HDMIA-RX1+
HDMIA-RX1-

U25
P
RX1_A
U26
N

DDCA-SCL
DDCA-SDA
IS10

W25
P
RXC_A
W26
N

HDMIA-RXC+
HDMIA-RXC+3V3

P
RX0_A
N

Y26
SCL
Y25
DDC_A
SDA
V25
P
V26
T24
RX2_A
HOT_PLUG_A
N

HDMIA-RX0+
HDMIA-RX0-

HDMI_DV

HDMIA-RX2+
HDMIA-RX2-

IS01

3S0W

W24

RREF

10u

RES

2S2E

12K

10

11

12

13

14
6

PNX85500

2009-12-07

8204 000 8950


18770_513_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 93

PNX Audio

PNX Audio

B02D

B02D

10

11

12

13

14

A
3S0Z
+2V5-AUDIO

3S53-1

+24V-AUDIO-POWER
4R7

100R
3S53-2

3
3S17-3

3S13-3

6
10K

AUDIO-IN4-L

1 22K

22K

3S17-1

8
10K

2S33

7
10K

2S32

8
2

1u0

AF8
L
AIN5
AE8
R

3S10
100R

2S2L

3S3G-1

AD7
AE7
AF7
AD6
AE6
AF6

4 3S3G-4 5
33R

AE5

220n

2S3J
2S34

RES

2S2S

100n

IS03

ADAC(2)

10

7S05-3
LM324 8

3S39

-AUDIO-R

100R
11

ADAC(3)

33R

ADAC(4)

3 3S36-3 6

10K

10K

5 3S36-4 4
2S2H

ADAC(5)

33R
3S3U

47p

ADAC(6)

+24V-AUDIO-VDD

33R

SPDIF_OUT
SPDIF_IN1

IS07
3

ADAC(5)

9S06

100n

10u
2S3G

100n
2S3H

2S3F

10u
2S3E

DBS8

ADAC(2)

2S3D

AF5

56R

3S3H

AE1
1
AF2
2
VREF_AADC
AE3
I2S_OUT_SD 3
AC8
AF3
VCOM_AADC
4

3S3F

3S3G-3

3S3G-2
2
7

IS1S

ADAC(1)
3

33R

AD8

IS1A

33R

AD4
OSCLK
AD1
SCK
AD2
WS

I2S_OUT
AB9
POS
VR_AADC
AB8
NEG

IS1B

1u0

1
IS1N

1u0

AC6
P
AB6
N

1
2
3
ADAC
4
5
6

AD9
L
AC9
AIN4
R

IS19

ADACR

AE9
L
AF9
AIN3
R

1u0
3S17-2

2 3S13-2

AUDIO-IN4-R

AD10
L
AIN2
AC10
R

1u0

22K
3S13-1

+24V-AUDIO-VDD
2S36

AUDIO
AC7
AE10
L
P
AF10
AIN1
ADACL
AB7
R
N

2S30

47p

7S00-2
PNX85500

1u0

1n0

1n0
2S38

AUDIO-IN3-R

22K

10K
8 3S36-1 1
2S2G

1n0
2S39

+AUDIO-L

11

10K

2S31

3S38
100R

2 3S36-2 7

1n0
2S3A

7S05-4
LM324 14

13

1u0

1u0
4 3S17-4 5
10K

IS0R

4
IS02

2S2Y

1n0
2S3B

22K
3S13-4

AUDIO-IN3-L

22K

12

ADAC(1)

100u 4V

10K

1u0

3S16-4 5

3S14
+2V5

2S2Z

2S41

IS13

COM

6
10K

IS0V

4 3S12-4

FS03

1
3

100R

22K
AUDIO-IN2-R

IN
INH

BP

1n0
2S3C

3S16-3 3

OUT

1u0

3S12-3 6

5
IS12

2S2V

22K
AUDIO-IN2-L

FS08

100n

7
10K

100R
3S53-4

2S2T

2 3S12-2

AUDIO-IN1-R

3S53-3

1u0

4R7
2S42

2
3S16-2

2S2W

10u

22K

10u

100R

1 3S16-1 8
10K

7S08
LD3985M25

2S2R

3S12-1

3S51

1
AUDIO-IN1-L

+24V-AUDIO-VDD

+3V3

7S05-1
LM324 1

AUDIO-OUT-L

11

3S37

3S6L

10K

22K
2S2K

+3V3

47p

+3V3-ARC

+24V-AUDIO-VDD
3S11

IS1L

100n

2S3Q

1R0
5

ADAC(6)

IS06

7S05-2
LM324 7

AUDIO-OUT-R

2S3K

1 3S18-1 8

IS1G

SPDIF-OUT

220R

100n
7

+3V3
+3V3

220R

&

3 3S18-3 6

IS1D

220R

SPDIF-OUT-PNX

2 3S18-2 7

SPDIF-OUT-PNX

11
14

7S09-1
74LVC00APW
1

3S34

3S32

10K

22K
2S2J
47p

IS1E

SEL-HDMI-ARC

&
6

14

7S09-3
74LVC00APW
9

&
8

5
+3V3

10

2S3L

180R

100n

3S6M

IS1K

2S3M

IS44
eHDMI+

100n
68R

3S25

+3V3-ARC
14

10K

3S19

+3V3-ARC
7S09-2
74LVC00APW
4

14

+3V3-ARC
7S09-4
74LVC00APW
12

&
11

13
7

+3V3

10

11

12

13

2S2G C12
2S2H D12
2S2J G12
2S2K F12
2S2L D4
2S2R B7
2S2S B9
2S2T B8
2S2V B3
2S2W B3
2S2Y C3
2S2Z B3
2S30 C3
2S31 C3
2S32 D3
2S33 C3
2S34 B9
2S36 C6
2S38 E9
2S39 E9
2S3A E8
2S3B E8
2S3C E8
2S3D E8
2S3E E3
2S3F E2
2S3G E3
2S3H E3
2S3J B11
2S3K G6
2S3L H8
2S3M H9
2S3Q G5
2S41 C6
2S42 C6
3S0Z A11
3S10 D4
3S11 F5
3S12-1 B2
3S12-2 B2
3S12-3 B2
3S12-4 C2
3S13-1 C2
3S13-2 D2
3S13-3 C2
3S13-4 C2
3S14 B9
3S16-1 B3
3S16-2 B3
3S16-3 B3
3S16-4 C3
3S17-1 C3
3S17-2 D3
3S17-3 C3
3S17-4 C3
3S18-1 G7
3S18-2 G8
3S18-3 G8
3S19 H5
3S25 H9
3S32 G12
3S34 G11
3S36-1 C12
3S36-2 B11
3S36-3 D11
3S36-4 D12
3S37 F11
3S38 B13
3S39 C13
3S3F E4
3S3G-1 C7
3S3G-2 D8
3S3G-3 C8
3S3G-4 D7
3S3H D7
3S3U D8
3S51 C6
3S53-1 A6
3S53-2 B6
3S53-3 B6
3S53-4 B6
3S6L F12
3S6M H8
7S00-2 C5
7S05-1 E12
7S05-2 G12
7S05-3 C12
7S05-4 B12
7S08 B8
7S09-1 G6
7S09-2 H6
7S09-3 H7
7S09-4 I7
9S06 E4
DBS8 E4
FS03 B12
FS08 B7
IS02 B11
IS03 C11
IS06 G11
IS07 E11
IS0R C2
IS0V C2
IS12 B8
IS13 B9
IS19 D3
IS1A D3
IS1B D4
IS1D G5
IS1E H5

IS1G G7
IS1K H9
IS1L F5
IS1N C7
IS1S D7
IS44 H9

14

PNX85500

2009-12-07

8204 000 8950


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2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 94

PNX Mips

PNX Mips

B02E
1

B02E

3S80
3S81

10K

3S21
+3V3
10K
3S62

10K
10K

FS10 TXD2-MIPS
FS11 RXD2-MIPS
PNX-SPI-CS-AMBIn

IS04
PNX-SPI-CS-BLn

+3V3

R26
DN
R25
USB
IS4Z R24 DP
RREF

USB-DM
USB-DP

FS64

SELECT-SAW

B25
SDA
3
A24
SCL

1 3S5Y 2
100R

B24
SDA
4
A23
SCL

1 3S60 2
100R

TRSTN
TMS
TCK
TDO
TDI

RESET_SYS

5K6

3S64
+3V3

3S55

10K

BL_PWM

10K
CLK_54_OUT

3S83
+3V3

12

13

14

1
100R
1
100R
1
100R
1
100R

2 3S57

2 3S5W

SDA-SET
SCL-SET

SDA-SET
SCL-SET

3S5Z

SDA-SSB
SCL-SSB

SDA-SSB
SCL-SSB

3S61

SDA-TUNER
SCL-TUNER

AA25
AA24
AA23
AB26
AB25

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

3S00

AE4

3S69

SDA-UP-MIPS
SCL-UP-MIPS

3S6A

4K7

3S6C

4K7
3S6B

4K7

3S6D

2K2

3S6F

4K7

4K7

3S6E

SDA-TUNER
SCL-TUNER

1F10

2K2

3S6G

FS44

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500

FS49
FS50
FS51
FS52

EJTAG-DETECTn

FS53
10 9

1
2
3
4
5
6
7
8

FOR FACTORY
USE ONLY

4K7

3S6K

EJTAG-TRSTn-PNX85500
EJTAG-TMS-PNX85500
EJTAG-TCK-PNX85500
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500

8 3S6H-1
10K
3
6 3S6H-3
10K
2
10K

1
10K

FS57

+3V3-STANDBY

+3V3

BM08B-SRSS-TBT

7 3S6H-2
5 3S6H-4
4
10K

RESET-SYSTEMn

33R

AD5

BACKLIGHT-PWM

AC5
10K

3S82 RES

+3V3
+3V3
+3V3

DS52
BOOST-PWM

1 3S58 2
100R

SDA-UP-MIPS
SCL-UP-MIPS

3S27

10K

B26
SDA
2
A25
SCL

10K

GPIO1

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_10
GPIO_11

3S26

+3V3

Y21
Y22
Y23
Y24
W21
W22
W23
V22
V23
U23

BOOTMODE
GPIO1
RXD1-MIPS
TXD1-MIPS
RXD2-MIPS
TXD2-MIPS
PNX-SPI-CS-AMBIn
PNX-SPI-CS-BLn
BOOST-PWM
SELECT-SAW

10K

BOOTMODE

C25
SDA
1
C26
SCL

1 3S56 2
100R

3S6J

3S45
10K
3S40

11

10

+3V3

IS05

+3V3

7S00-3
PNX85500

CONTROL

RXD1-MIPS

10K
3S84
+3V3

+3V3
TXD1-MIPS

+3V3
IS40

3S72

PXCLK54

10K
47R

RES

D
+3V3
2S89
100n

VDD

+3V3

7S01
PCA9540B

SCL-SET

SCL

SDA-SET

SDA

INP
FIL

I 2 C
-BUS
CTRL

SC0

SCL-DISP

SC1

SCL-BL

SD0

SDA-DISP

SD1

SDA-BL

SCL-DISP

3S65

3S66 4K7
1
3S67 4K7
1
2
4K7
3S68
2
1
4K7
2

SCL-BL
SDA-DISP
SDA-BL

VSS

FS31

9S10
IS08

SCL-SET

SDA-SET

IS09

SCL-BL

9S11

FS2W

SCL-DISP

9S12

FS2Y

SDA-DISP

9S13

1F10 A12
2S89 D8
3S00 B5
3S21 B1
3S26 C5
3S27 C6
3S40 A1
3S45 A1
3S55 C3
3S56 A5
3S57 A6
3S58 A5
3S5W B6
3S5Y B5
3S5Z B6
3S60 B5
3S61 B6
3S62 B1
3S64 C1
3S65 E11
3S66 E11
3S67 E11
3S68 E11
3S69 A9
3S6A A8
3S6B A9
3S6C B8
3S6D B9
3S6E B8
3S6F B9
3S6G B8
3S6H-1 B8
3S6H-2 B9
3S6H-3 B9
3S6H-4 B9
3S6J C5
3S6K B9
3S72 C6
3S80 B1
3S81 B1
3S82 B1
3S83 C1
3S84 C1
7S00-3 A4
7S00-4 G12
7S01 E8
9S10 F8
9S11 F8
9S12 F8
9S13 F8
DS52 B2
FS10 B2
FS11 B2
FS2W F9
FS2Y F9
FS31 F8
FS44 A12
FS49 A12
FS50 A12
FS51 B12
FS52 B12
FS53 B12
FS57 B12
FS64 C2
IS04 B2
IS05 A2
IS08 F8
IS09 F8
IS40 C6
IS4Z B4
IS50 G12

SDA-BL

7S00-4
PNX85500

10

11

ETHERNET

ETH-RXCLK

AA3

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

Y5
0
Y6
1
AB4
RXD ETH
2
AC1
3

IS50

RXCLK

ETH-RXDV
ETH-RXER

AC2
RXDV
Y4
RXER

SDIO-DAT3
SDIO-CLK
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP

W2
W1
W6
W5
W4
W3
U6
V6

12

TXCLK
0
1
2
3
TXEN
TXER
COL
CRS
MDC
MDIO

TXD
ETH

CC_DAT3
CLK
CMD
0
SDIO
1 DAT
2
SDCD
SDWP

AA2

ETH-TXCLK

AA1
AA4
AB1
AB2
AA5
AB3
AC3
Y2
Y3
Y1

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)
ETH-TXD(3)
ETH-TXEN
ETH-TXER
ETH-COL
ETH-CRS
ETH-MDC
ETH-MDIO

13

14

PNX85500

2009-12-07

8204 000 8950


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100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 95

PNX Video Out - LVDS

B02F
1

PNX Video Out - LVDS


2

B02F
4

10

11

12

13

14
7S00-7 C8

7S00-7
PNX85500

PX1APX1A+

A7
B7

PX1BPX1B+

C8
B8

PX1CLKPX1CLK+

C10
N
CLK
B10
P

PX1CPX1C+

A9
B9

PX1DPX1D+
PX1EPX1E+

N
A
P

LVDS

N
B
P

N
P

N
P

D7
E7

PX3APX3A+

E8
D8

PX3BPX3B+

E10
N
CLK
D10
P

PX3CLKPX3CLK+

LOUT1 LOUT3
C

N
P

D9
E9

PX3CPX3C+

A11
N
D
B11
P

D11
N
E11
P

PX3DPX3D+

C12
N
B12
E
P

E12
N
D12
E
P

PX3EPX3E+

PX2APX2A+

A14
N
A
B14
P

D14
N
E14
P

PX4APX4A+

PX2BPX2B+

C15
N
B
B15
P

E15
N
B
D15
P

PX4BPX4B+

PX2CLKPX2CLK+

C17
N
B17
CLK
P

E17
N
CLK
D17
P

PX4CLKPX4CLK+

PX2CPX2C+

A16
B16 N
C
P
A18
B18 N
D
P
C19
B19 N
E
P

D16
N
E16
P

PX4CPX4C+

D18
N
E18
P

PX4DPX4D+

E19
N
E
D19
P

PX4EPX4E+

PX2DPX2D+
PX2EPX2E+

N
C
P

LOUT2 LOUT4

10

11

12

13

14

PNX85500

2009-12-07

8204 000 8950


18770_516_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 96

PNX Stand-by Controller

PNX Stand-by Controller

B02G

B02G
3

10

13

12

11

POL

+1V1

2S13

100n

1u0
2S10

30R

RES
5S04

IS3B

2S37
9S24
RES

1u0

2S11
100n

IS20

DS50

3S1E
10K
+3V3-STANDBY

3S3L

10K

3S3M
10K
3S3P
10K
RES 3S3S
10K
3S3T
10K

+3V3-STANDBY
3S1H
10K

RES
10K
3S3N RES
10K
3S3Q RES
10K
3S3R
10K RES

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

3S1G

RXD-UP
TXD-UP

10K
3S2A RES

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

AD19
0
AE19
1
AF19
2 P1
AA20
3
AB20
7

LCD-PWR-ONn
EJTAG-DETECTn
LAMP-ON
STANDBY
FAN-CTRL1
FAN-CTRL2
POWER-OK
ENABLE-3V3n

AC20
0
AD20
1
AE20
2
AF20
3
P2
AA21
4
AB21
5
AC21
6
AD21
7

DETECT2

RESET-SYSTEMn

10K
3S1J

KEYBOARD

100K

2S4E
100n

3S1L

SPI-PROG

10K

RESET_IN
EA
ALE
PSEN
MC

SPI

AF22
4
AE22
P6
5

SPI-PROG
PNX-SPI-WPn

+3V3-STANDBY

54M

1S02

10p

AF17
AA26

RESET-STBYn

AB24

EA

AB23

ALE

AC26

PSEN

AC23
SDA
AC24
SCL

AD26
0
AC25
PWM
1

AD23
0
AE26
1
AE25
P5
2
AE24
3

RESET-SYSTEMn
AV2-BLK
AV1-BLK
KEYBOARD
LIGHT-SENSOR
AV1-STATUS
AV2-STATUS

AE17

10p
2S4F

AF26

AC17
XTAL_IN
XTAL_OUT

STANDBY

AE21
0
AF21
1
AA22
2
AB22
P3
3
AC22
4
AD22
5

RXD-UP
TXD-UP
DETECT2

10K
3S1K RES

VDD_XTAL

RC
TACHO
CEC-HDMI
BACKLIGHT-PWM-ANA-DISP
SDM

1
7S00-9
PNX85500

3S2F
100R

100R

3S2G

100R

3S2K

3S2H
100R

EA
ALE
PSEN

SDA-UP-MIPS
SCL-UP-MIPS

IS3F

3S44

IS3E

10K

3S43

IS3D

10K 3S42

10K

RES

SDA-UP-MIPS
SCL-UP-MIPS

3S6V
4K7

3S6W

LED2

10K

IS2V

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

RES

3S41
10K

PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK
PNX-SPI-CSBn

IS2Z

4K7

3S1P

RES

LED1

LED1
LED2

AE23
SDO
AF25
SDI
AF24
CLK
AF23
CSB
AB17
0
AA18
1
AD18
2
AE18
3
P0
AF18
4
AA19
5
AB19
6
AC19
7

AD17

10K
3S1D
27K

RES
10K
RES
3S1F

VDDA_ADC2V5

2S4D
1n0

3S1B
3S1C

VSS_XTAL

+3V3-STANDBY

VDDA_1V1_DCS

AA17

2S4G

D
3S2L

RES
10K
RES 3S3Y
10K

CTRL-DISP
RESET-DVBS
RESET-USBn
RESET-ETHERNETn
SEL-HDMI-ARC
RESET-AVPIP
RESET-AUDIO
AUDIO-MUTE-UP

10K

3S2S
RES
3S3W
4K7

3S46

RES
10K
RES
10K

+3V3-STANDBY

3S47
3S2M
RES
3S49

10K
4K7

1S02 B8
2S10 B6
2S11 B5
2S13 B6
2S37 B5
2S4D C3
2S4E E2
2S4F B9
2S4G B9
2S4K G10
3S1B C2
3S1C C1
3S1D C2
3S1E C1
3S1F C2
3S1G D2
3S1H D1
3S1J D2
3S1K D1
3S1L E2
3S1P D11
3S2A D2
3S2F D7
3S2G D7
3S2H D7
3S2K D7
3S2L D10
3S2M E10
3S2S E10
3S2V F11
3S3L C2
3S3M C1
3S3N C2
3S3P C1
3S3Q C2
3S3R D2
3S3S D1
3S3T D1
3S3W E9
3S3Y D9
3S41 D12
3S42 C11
3S43 C11
3S44 C11
3S46 D10
3S47 E10
3S49 E10
3S6V C11
3S6W D12
5S04 B6
7S00-9 B6
7S20 G10
9S0D G9
9S0E G9
9S24 B6
DS50 B8
FS0Z G11
FS45 G9
IS20 B6
IS2U G10
IS2V D7
IS2Z D7
IS3B A6
IS3D C10
IS3E C10
IS3F C10

7S20
NCP303LSN28
2

FS45
1

INP

IS2U
5

OUTP
CD

FS0Z

RESET-STBYn

NC GND

100n

2S4K

RES

9S0D

10K

1 3S2V 2

+3V3-STANDBY

9S0E

+3V3-STANDBY

10

11

12

13
6

PNX85500

2009-12-07

8204 000 8950


18770_517_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 97

PNX Power

PNX Power

B02H
1

B02H

10

11

12

13

14

5S80

IS3Q

2S5A

RES 10u

100n

2S6A

+1V1
30R

5S81

2S5B

RES 10u

30R

100n

2S6B

+2V5

5S82

IS3S

100n

100n
2S68

100n
2S67

100n
2S66

+3V3
2S5D

2S4M

100n

U22

10u

VDDA_2V5_USB
VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB

100n
100n

2S4W

2S4Y

RES 1u0

+2V5

10u

2S50

100n

2S4Z

+1V2

10u

100n

AA7

6.3V

5S84
30R
c000

SENSE+1V2

Y17
D13
T20

POL

Y13

+2V5-AUDIO

Y10

100n

VDDA_2V5_LVDS_BG

30R

30R

2S46

VDDA_2V5_DCS

5S95

Y12
AA9
2S52

VDDA_2V5_ADAC

VSSA_USB

+1V1

2S51

VDDA_2V5_AADC

5S83

IS3L

AA15
Y15
AA13

VDDA_2V5

VSSA_2V5_LVDS_BG

10u

100n

1
10u
2S4U

IS3K
B13

VDDA_1V1_LVDS_PLL

R21

+2V5-AUDIO
100n

2S45

VDD_1V1_DDR

2S6P

2
100n
2S6C

2
100n
2S6N
1

2
2S6F

100n
1 2S6G 2

Y19
Y18

VDD_3V3_SBY

VDDA_1V2

+3V3

30R

+3V3-STANDBY
2S4V

VDD_1V1

5S85

W20
P20
M20
K20
V7
Y8

VDD_3V3

100n

2S4N

C7
C9
C11
C14
C16
C18

2S4P

+2V5-LVDS

N6
N7

VDD_2V5_LVDS

220u 6.3V

100n
2S6E 2

2S6D
1

U20
U21

+2V5

30R

R20

HDMI_VDDA_2V5

VDD_2V5

C13

100u 2.0V
1u0

2S21

RES

HDMI_VDDA_1V1

V20
V21

HDMI_VDDA_3V3_TERM

VSSA_1V1_LVDS_PLL

30R
2S4S

G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6

J7
2

+1V1

VSS

VDD

A13

47u

2S23

5
100n

100n
2S5H-4
5

100n

100n
2S5J-4
4

7
100n
2S5J-2

100n
2S5J-1 8

3
5S94

100n

VSS

VSS

2S5P

VSS

M7
N2
N20
P10
P12
P14
P16
P18
P4
P6
P7
T10
T12
T14
T16
T18
T2
T6
T7
U4
V10
V12
V14
V16
V18
V2
Y20

10u

VSSA

VDD_1V8

U24
V24 HDMI_AGND

6
100n
2S5H-3

8
100n
2S5H-2

100n
2S5J-3 6

5
4

2S29

AA16
AA8
Y11
Y14
Y16
Y9

100n
2S5K-4

6
100n
2S5K-3

2S5K-1
1

100n
2S5K-2

100n
2S5H-1

100n
2S5G-4

100n
2S5G-3
3

100n
2S5G-2

2S5G-1
1

22u

22u
2S4R

100n

2S4Q

100n

2S27

2S28

100n

2S43

A1
A10
A12
A15
A17
A19
A26
A3
A8
B1
B20
C20
C4
D2
D20
E13
E20
E4
F10
F12
F14
F16
F18
F20
F8
G10
G12

AF1
AE2
AD3
AC4
AB5
H20
F11
G11
F13
G13
F15
G15
F17
G17
F19
G19
J9
J11
J13
J15
J17
L9
L11
L13
L15
L17
N9
N11
N13
N15
N17
R9
R11
R13
R15
R17
U9
U11
U13
U15
U17
J6
AA6
Y7
W7
F9
G9

+1V1

30R

5S93
L6
L7
R6
R7
U7
A5
A6
B5
B6
C6
D6
E6
F6
G6
F7
G7

7S00-10
PNX85500

7S00-12
PNX85500

RES 10u

c001

SENSE+1V1

100n

2S5C

100n
2S65

100n
2S64

100n
2S63

100n

2S62

100n
2S61

47u
2S60

2S26

+1V8

5S87

2S21 F6
2S23 B6
2S26 A6
2S27 B3
2S28 B3
2S29 C6
2S43 B2
2S45 F11
2S46 F11
2S4M B12
2S4N C11
2S4P C11
2S4Q B3
2S4R B4
2S4S F5
2S4T H11
2S4U D11
2S4V D11
2S4W D11
2S4Y D11
2S4Z E11
2S50 E11
2S51 E9
2S52 E9
2S53 H11
2S55 G11
2S56 G11
2S57 G11
2S58 H11
2S59 I11
2S5A A11
2S5B A11
2S5C B11
2S5D B11
2S5G-1 B4
2S5G-2 B4
2S5G-3 B4
2S5G-4 B5
2S5H-1 B5
2S5H-2 B5
2S5H-3 B5
2S5H-4 B5
2S5J-1 C5
2S5J-2 C5
2S5J-3 C5
2S5J-4 C5
2S5K-1 C4
2S5K-2 C4
2S5K-3 C4

2S5K-4 C5
2S5M G11
2S5P F5
2S60 A6
2S61 A6
2S62 A7
2S63 A7
2S64 A7
2S65 A7
2S66 A7
2S67 A8
2S68 A8
2S6A A11
2S6B A11
2S6C C11
2S6D B11
2S6E B11
2S6F C11
2S6G C11
2S6H H11
2S6K H11
2S6L I11
2S6M I11
2S6N C11
2S6P C12
2SHW I11
5S80 A12
5S81 A12
5S82 A12
5S83 D12
5S84 E12
5S85 C12
5S87 F12
5S88 G12
5S89 H12
5S90 H12
5S92 I12
5S93 B12
5S94 F5
5S95 E10
7S00-10 B6
7S00-12 C1
IS3K D10
IS3L D10
IS3Q A10
IS3S A10
IS58 I10
c000 E13
c001 B5

+2V5
1u0

2S56

100n

2S55

30R

5S88
10u

100n
2S57

2S5M

+2V5-LVDS
30R

10u

100n
2S58

100n
2S6K

+2V5
30R

2S6H

5S89

5S90
+2V5
10u

100n

2S53

2S4T

100n

2SHW

30R

I
5S92

10

11

1u0

100n
2S59

2
100n
2S6L

+3V3
30R

2S6M

IS58

12

13

14
6

PNX85500

2009-12-07

8204 000 8950


18770_518_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 98

PNX Analog Video

PNX Analog Video


2

10

11

12

2S87

AV1-CVBS

9S17

2S8A

2S7J
2S22

3S4J

56R

22n

C-SVHS
22n

3S05

AV1-R

EU: SCART1

CVBS-MON-OUT1

56R

3S4L

22n

560R

3S5E

2S7K

AV1-B

Y-SVHS

22n
47R

Connectivity

3S59

47R

22n

AP:

14

13

3S5B

B02I

56R

B02I

B
3S08

560R

47p

2S7H

2S40

IS4V

22n

10n
2S7L
56R

3S4P

AV3-Y

22n

AF15
AE15
AC15
AD15

2S8G

AV2-CVBS

47R

3S5L

22n

AB14
AF14
AE14
AC14
AD14

2S7Q

YPBPR2-SYNCIN2

10n

2S7R

AV4-Y
22n
56R

YPBPR2

3S4U

SCART2

SCL VGA_EDID
P
TUNER N
SDA

AF11
AE11
AB10
AA11
AC16
AB16
AB13
AB12
AA12
AA10

IS5E

3S5S
10K

IS5D
IS5F
IS5G
IS5H
IS5J

3S75

AD12
AB11

BS15

AE12
AF12

BS09

BS17

56R

PNX-IF-AGC

47K

BS10

IS11

3S76
10n

AA14

PNX-RF-AGC

47K

3S4W

22n

2S14

BS13

AGND
AV4-PR

2S15
22n

AD11
AC11

+CVBS
2S7U

2S16
22n

IS5C

22n

AC12
AF13

2S76

EU:
AP:

AF16
AD16
AE16
AB18
AC18
AF4
AD24
AD25

CVBS_Y1 ATV_CVBS_Y3
C3
R
B AV1
G
CVBS_Y7
C7
SYNCIN1
CVBS1_OUT
Y_G1
CVBS2_OUT
PR_R_C1
PB_B1
RESREF
CVBS_Y2
CURREF
SYNCIN2
Y_G2
1
PR_R_C2
2
PB_B2
3
REF 4
R
5
6
G VGA
B
HSYNC_IN
IF_AGC
IN
RF_AGC
VSYNC
OUT

22n

22n

2S18
22n

ANALOG_VIDEO
AB15
AC13
AD13
AE13

2S19

56R

3S4T

AV3-PB

7S00-1
PNX85500
2S7P

10n

YPBPR1

2S75

56R

YPBPR1

3S4R

AP:

22n

2S7N

AV3-PR

2S7M

YPBPR1-SYNCIN1

EU:

8K2

IS4W
3S09

56R

3S4K

AV1-G

2S77

PNX-IF-P

10n

2S7E
56R

3S4G

AV4-PB

22n

2S78

PNX-IF-N

10n

2S84
56R

3S50

R-VGA

22n

2S85
56R

3S52

G-VGA

22n

2S86

VGA-SDA-EDID

1 3S5V-1 8

100R

3 3S5V-3 6

2 3S5V-2 7

VGA-SCL-EDID

100R

100R
3 3S5T-3 6

4 3S5V-4 5

V-SYNC-VGA

100R

1 3S5T-1 8

100R

H-SYNC-VGA

2 3S5T-2 7

AP: VGA

22n
4 3S5T-4 5

56R

EU: VGA

3S54

B-VGA

100R

100R

VGA-SCL-EDID-TCON

9S14

VGA-SDA-EDID-TCON

9S15

100R

*
*

*
4

= TCON ONLY

10

11

12

13

14

2S14 D12
2S15 D12
2S16 D12
2S18 D12
2S19 D12
2S22 A11
2S40 B11
2S75 F11
2S76 F11
2S77 F12
2S78 G12
2S7E G6
2S7H B6
2S7J A6
2S7K B6
2S7L C6
2S7M C6
2S7N D6
2S7P D6
2S7Q E6
2S7R F6
2S7U F6
2S84 G6
2S85 H6
2S86 H6
2S87 A6
2S8A A11
2S8G E6
3S05 A11
3S08 B11
3S09 C11
3S4G G6
3S4J A6
3S4K C6
3S4L B6
3S4P D6
3S4R D6
3S4T D6
3S4U F6
3S4W F6
3S50 H6
3S52 H6
3S54 I6
3S59 A6
3S5B A11
3S5E B11
3S5L E6
3S5S E9
3S5T-1 I5
3S5T-2 I11
3S5T-3 I5
3S5T-4 I11
3S5V-1 I5
3S5V-2 I12
3S5V-3 I5
3S5V-4 I12
3S75 E12
3S76 F12
7S00-1 D8
9S14 I3
9S15 I3
9S17 A13
BS09 F9
BS10 F10
BS13 E9
BS15 F9
BS17 F10
IS11 F13
IS4V B10
IS4W C10
IS5C D9
IS5D E9
IS5E E9
IS5F E9
IS5G E9
IS5H E9
IS5J E9

PNX85500

2009-12-07

8204 000 8950


18770_519_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 99

10-11 B03 820400089514 CLASS D


Audio

Audio

B03A
3

7D03-1
BC847BS(COL)
6

3D09

+24V-AUDIO-POWER

+24V-AUDIO-POWER

220R

GND-AUDIO

7D15-2
BC847BS(COL)
4

4K7

ID19
ID18

6
5
18
17

2D16

GND-AUDIO

ID29

11
7
4
2

1u0

2D17

ID30

1u0
ID37

AUDIO-MUTE-UP

10
12

AVCC

47n

3
3D02-2

4K7

1u0

IN
L

2D26

2D22
220n

8
1

3D14-1
220n

7
3D14-2
22K
2

3D14-3
22K

5
3D14-4
22K

22K

220n

7D10-1
TPA3120D2PWP

PVCC
BSR

CLASS-D
AUDIO AMP

GND-AUDIO

1
3

2D23

ID15

19
20

2D29

3D02-4

FD03

+AUDIO-L

2D08

220n

2D07

2D20

7D15-1
BC847BS(COL)
1

4K7

47n

220u 35V

A-PLOP

3D02-1

6
3D02-3

4K7

1u0

ID28

ID27

2D24

2D19

ID14

2D28

FD01

-AUDIO-R

GND-AUDIO

220u 35V

2D05

10u 35V

22K

220R
5D08

ID11

A
5D07

ID12

220n

3D16

2D06

4R7

FD14

+AVCC

B03A

R
OUT
L

0
GAIN
1

BSL

16

ID32

2D10
5D05
ID06

22u

22
21

5D02

ID10
220n

15

5D01

ID09
ID31

2D09

22u

ID05

2D12

220R

ID08

5D04

ID07

220R

RIGHT-SPEAKER

25V 220u
2D11

LEFT-SPEAKER

25V 220u

220n
VCLAMP
BYPASS
MUTE
SD

2D27

3D10-1
220n
1

2D21
220n

6
3D10-3
22K

3D10-2
22K
2

3D10-4
22K

25

22K

4K7

GND-AUDIO

+3V3-STANDBY
5

3D01-2

DETECT2

47K

GND-AUDIO

10n

2D14

VIA

V_NOM

VIA

37
36
35
34

1D50

GND-AUDIO

BZX384-C

LEFT-SPEAKER

VIA

VIA
VIA

MAINS-OK

1D38

1735
30
31
32
33
3D06-4 FD07

LEFT-SPEAKER
4

100K 5

3D06-2

3D06-3
100K

1735446-3

1735446-4

RIGHT-SPEAKER
1

ID33
1D52

GND-AUDIO
3

1
2
3

100K

RIGHT-SPEAKER

FD02

1
2
3
4

100K
3D06-1

GND-AUDIO

10n

GND-AUDIO
3 7D03-2
BC847BS(COL)

10n

220R

GND-AUDIO

FD05
FD06

5D03

2D13

GND-AUDIO

2D02

V_NOM

2K2

4K7

26
27
28
29

+AVCC

3D04

4K7

GND-AUDIO
ID13 6D01

GND-AUDIO

2D01

GND-AUDIO
3D15-2
3D15-1
1
8 7
2

GND-AUDIO

40
39
38

100p

7D10-2
TPA3120D2PWP

ID36

7D13-2
BC847BS(COL)
4

GND-AUDIO

ID34

2D03

GND-AUDIO

ID39

13
14

8
9
5
3

CD10

ID35
7D11-2
BC847BS(COL)
4

5
47K

7D13-1
BC847BS(COL)
1

3D01-4

MAINS SWITCH DETECT

GND_HS

47K
2

7D11-1
BC847BS(COL)
1
+3V3-STANDBY

3D15-4

+3V3-STANDBY

3D01-1

L
23
24

PGND
AGND

ID38

A-STBY

6
10u
GND-AUDIO

1735 E8
1D38 E9
1D50 E8
1D52 F8
2D01 F7
2D02 F4
2D03 E3
2D05 A5
2D06 A5
2D07 B5
2D08 B6
2D09 C7
2D10 C7
2D11 C8
2D12 C8
2D13 F8
2D14 E8
2D16 C4
2D17 C4
2D19 B6
2D20 B5
2D21 D8
2D22 B8
2D23 B4
2D24 B4
2D26 B8
2D27 D8
2D28 B2
2D29 B2
3D01-1 D3
3D01-2 D3
3D01-4 E2
3D02 B3
3D02 C3
3D02 B4
3D02 C4
3D04 E2
3D06-1 F4
3D06-2 F4
3D06-3 F3
3D06-4 F3
3D09 A3
3D10-1 D8
3D10-2 D8
3D10-3 D7
3D10-4 D7
3D14-1 B8
3D14-2 B8
3D14-3 B7
3D14-4 B7
3D15-1 E2
3D15-2 E3
3D15-4 D5
3D16 A5
5D01 C7
5D02 C7
5D03 E7
5D04 C8
5D05 C8
5D07 A6
5D08 A6
6D01 E3
7D03-1 A5
7D03-2 F5
7D10-1 B6
7D10-2 E5
7D11-1 D2
7D11-2 D3
7D13-1 E1
7D13-2 E2
7D15 B3
7D15 C3
CD10 D5
FD01 B1
FD02 F8
FD03 B1
FD05 E8

FD06 E8
FD07 F4
FD14 A5
ID05 C8
ID06 C8
ID07 C8
ID08 C8
ID09 C7
ID10 C7
ID11 A4
ID12 A5
ID13 E3
ID14 B3
ID15 B3
ID18 C5
ID19 C5
ID27 B6
ID28 B6
ID29 C5
ID30 C5
ID31 C6
ID32 C6
ID33 F4
ID34 D3
ID35 D3
ID36 E2
ID37 D4
ID38 D5
ID39 E2

9
4

CLASS D

2009-10-22

8204 000 8951


18770_520_100118.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 100

DC/DC

DC/DC

B03B
2U00 D2
2U01 E3
2U02 D4
2U03 E2

2U04 F4
2U05 F4
2U06 F1
2U07 H3

B03B

2U08 G9
2U09 F9
2U10 F10
2U11 F9

2U16 C10
2U17 C9
2U18 D9
2U19 B12

2U12 F11
2U13 F12
2U14 E14
2U15 C10

2U24 B5
2U25 B12
2U29 G14
3U00 F1

2U20 B14
2U21 C6
2U22 D8
2U23 B5

3U01 F1
3U02 F2
3U03 F3
3U04 D3

3U11 B6
3U14 D7
3U17 G10
3U18 G10

3U05 E4
3U08 G2
3U09 H3
3U10 H3

3U27 D5
3U28 D5
5U00 C10
5U01 E10

3U24-1 F9
3U24-2 F9
3U24-3 F9
3U24-4 F8

3U23-1 C9
3U23-2 C9
3U23-3 C9
3U23-4 C8

3U19 G9
3U20 F11
3U21 G13
3U22 G2

5U02 B13
5U03 A13
6U00 E8
7U00 F1

7U01 D8
7U02-1 B6
7U02-2 C6
7U03 E3

FU02 B9
FU03 C14
FU04 F4
FU05 B9

7U04 E8
CU00 H7
FU00 G13
FU01 E14

10

IU04 G3
IU05 D3
IU06 D3
IU07 D4

FU06 E8
IU01 F3
IU02 F3
IU03 F1

11

IU12 D7
IU13 D7
IU14 E8
IU15 C9

IU08 D4
IU09 C6
IU10 B 6
IU11 C6

14

13

12

IU16 E5
IU17 F9
IU18 F9
IU19 G10

IU20 G9
IU21 H9
IU22 B13
IU23 C9

IU24 E3
IU25 F4

15

A
5U03 RES
30R
5U02

FU05

IU22
+12V

1u0

2U20

10u

10u

7 8

IU10

12V/1V8 CONVERSION

3R3

3U11

2U19

2U25

7U02-1
SI4952DY

10u

10u

2U23

2U24

30R

FU02

2U21

5U00

FU03

22u

47u

2U16

2U15

3u6

47R

47R
1 3U23-1 8

47R

2 3U23-2 7

7U02-2
SI4952DY

47R

3U23-4

220p

3 3U23-3 6

+1V8
IU11

5 6

IU09

1n0

2U17

IU23

IU15

IU08

5 6 7 8

IU12

10R

2U22
IU07

3U28

IU05

22K

GND-SIG

IU02

GND-SIG

20

VIN

2U06

V5FILT
VREG5

2U14

RES 100u 2.0V

22u

2U13

IU17

1u0

2U05

10K

10u

100n

IU18

GND-SIG

1u0

1n0

2U10

GND-SIG

2U09

3U01

FU04

IU25

GND

+1V1

10K

GND-SIG

18
19

2U04

3U00

7
17

47u

1
2

2U12

TEST

2u0

10R
RES

1
TRIP
2

22
15

3U20

1
2

47R

PGND

FU01
+1V1

47R
3U24-1

1
2

5U01

FU06

24
13

47R

SW

1
VFB
2

12V/1V1 CONVERSION

1
12

47R

1
VO
2

1 2 3

3U24-2

21
16

1
2

5 6 78
4
IU14

2U11

3U03

DRVH

IU01

22K

1
EN
2

23
14

3U24-3

GND-SIG
3U02

2
+3V3-STANDBY

5
8

1
2

3U24-4

1n0 RES

2U03
7U00
BC847BW
IU03

4
9

+1V1
+1V8

DRVL

7U04
SI4778DY
IU16

6U00

3
10

ENABLE-1V8

1
VBST
2

220p

STPS2L30A

2
11

IU13

3R3

7U03
TPS53126PW

IU24

RES

3U05

100n

2U01

100n

1n0

2U02

10R

IU06

3R3

3U14

1 2 3

3R3

3U04

10u

2U00

1n0

3U27

2U18

7U01
SI4778DY

3U21

FU00

SENSE+1V1

IU19

3U18

5K6

3U19

100n

IU21

RES 100p

22K

2U07

3U10

RES
2U29

3U17
IU04

1K0 1%

3U09

330R 1%

100p RES

3U22

+1V8

1K0 1%

3U08

2U08

IU20

1% 1K0

1% 330R

100R 1%

GND-SIG

GND-SIG

GND-SIG

CU00

GND-SIG

GND-SIG

GND-SIG
GND-SIG

10

11

12

13

14

15
4

DC/DC

2009-10-22

8204 000 8951


18770_521_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 101

DC/DC

DC/DC

B03C

B03C

+3V3-STANDBY

+3V3

3U75

+5V +3V3-STANDBY

RES 10K

3U74

RES 10K

LED-2

IU43

3U69

RES 10K

LED-1

10K

3U68

9U41

IU44

optionally 1M99 is a 9 pin connector

LED2

3U59

LED2

10K RES

10K RES

7U42 RES
BC847BW
IU47

2U41 RES

3U41

IU45
9U42
RES

7U43
BC847BW

100p

+3V3

3U70

LED1

3U53

LED1

10K

10K

+12VD

FU49
FU50

10K
3U45

BACKLIGHT-BOOST

1K0 RES
BACKLIGHT-PWM-ANA-DISP

7U48-1
BC857BS(COL)

100K
IU41
2

3U56
+3V3

3U83-4

ENABLE-3V3-5V

FU07

3U44

10n

1n0
2U45

3U43

IU64

3U82

100R

2U46

10n

100p

2U43

2U44

3U65

BACKLIGHT-PWM_BL-VS

10K
IU55

100K

100R

FU54
RES 1K0

1n0

2U53

RES 100p

2U52

2U51

RES 100p

2U72

100p

1K0

3U42

3U83-1

100R

3U64

FU55

LAMP-ON

100R

FU52
FU53

FU51

1-1735446-2

IU56

3U81

+3V3

1u0

100n

1
2
3
4
5
6
7
8
9
10
11
12

RES

POWER-OK

3U66
BL-SPI-SDO

FU56
3U67

RES 100R

BL-SPI-CSn

FU57

+3V3-STANDBY

3U84
BL-SPI-CLK

FU74
100R RES

3U71

2U68

100R RES

2U42

FU48

2U71

1M99

STANDBY

7U48-2
BC857BS(COL)
3U83-3

3U83-2

100K

IU40

100K

DETECT2

6
1
7U41-1
BC847BS(COL)
1

3U60-1

IU57
1

ENABLE-3V3n

22K

IU52

10K

3U63

3K3

22K

3U60-4

IU50

4K7

3U80

IU62

7U41-2
BC847BS(COL)

3U84 D2
6U40 E3
7U40-1 F4
7U40-2 E4
7U41-1 F4
7U41-2 F5
7U42 B5
7U43 B3
7U48-1 C6
7U48-2 E6
9U41 B5
9U42 B4
FU07 C3
FU48 C1
FU49 C1
FU50 C1
FU51 C1
FU52 C3
FU53 C2
FU54 C2
FU55 C1
FU56 D1
FU57 D1
FU58 E1
FU59 E1
FU60 E1
FU61 E1
FU62 E1
FU63 E1
FU64 F1
FU65 F1
FU66 F1
FU67 F1
FU68 F1
FU72 F4
FU73 E5
FU74 D1
IU40 E5
IU41 D5
IU43 B5
IU44 B5
IU45 B4
IU47 B4
IU48 E4
IU49 E3
IU50 F4
IU51 F3
IU52 F5
IU55 D3
IU56 C3
IU57 F6
IU61 E4
IU62 F4
IU63 F3
IU64 C6

RES 10K

+3V3-STANDBY

3U61

6
3
22K

FU72

IU63

3U62-1

ENABLE-1V8

22K

7U40-1
BC847BPN(COL)

FU73

10K

3U62-3

7
6

3U60-3

RES 10K

10K

3U62-2

IU49

3U73

3U60-2

6U40

2
10n

100R
10n
2U54

3
IU61

2U55

MAINS-OK

BZX384-C6V2

IU51

+24V-AUDIO-POWER
3U76

100p RES
2U50

2U48

IU48

1u0 RES

FU66

FU68

GND-AUDIO

+12V

T 3.0A 32V

1K0

1U40

FU67

1-1735446-1

3
4

+3V3-STANDBY

3U72

FU58
FU59
FU60
FU61
FU62
FU63
FU64
FU65

100p RES

1
2
3
4
5
6
7
8
9
10
11

10n

1M95

2U49

7U40-2
BC847BPN(COL)

1u0
2U47

10K

3U62-4

100R

1M95 E1
1M99 C1
1U40 E2
2U41 B1
2U42 C2
2U43 D2
2U44 D3
2U45 D3
2U46 D3
2U47 E1
2U48 F1
2U49 F1
2U50 F1
2U51 D1
2U52 D1
2U53 D2
2U54 F2
2U55 F3
2U68 E1
2U71 D5
2U72 D1
3U41 B5
3U42 C3
3U43 C3
3U44 C3
3U45 C3
3U53 B6
3U56 D3
3U59 B6
3U60-1 F5
3U60-2 F4
3U60-3 E5
3U60-4 F5
3U61 E5
3U62-1 F4
3U62-2 E3
3U62-3 E4
3U62-4 E3
3U63 F5
3U64 C2
3U65 D2
3U66 D2
3U67 D2
3U68 B3
3U69 B3
3U70 B4
3U71 D3
3U72 F3
3U73 F3
3U74 A4
3U75 A4
3U76 F2
3U80 F4
3U81 C3
3U82 C5
3U83-1 D6
3U83-2 E5
3U83-3 E5
3U83-4 C5

9
4

DC/DC

2009-10-22

8204 000 8951


18770_522_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 102

DC/DC

B03D

DC/DC

B03D

RESERVED
+12V

2UA3
2UA2

3UA6

330p

2UA6

1u0

2UA5

22K

3UA8

1u0

3U15-1

+2V5

+3V3

+5V

+2V5-LVDS

3U16-1

100R

IUA7

7UA1-2
LM833
7

FUA2

3UB0

1u0

7UA3
PHD38N02LT

330R
1%

3U13

IU26

IUA5

3U15-3

3U16-2

3U16-3

100R
4

3U16-4

100R

1u0

2UB2

+3V3

100R

100R

1K0

3UA9

IUA8

RES 1u0

2UB1

330p

2UA8

3U15-4

+1V2

1n0

2UA9

FUA3

100R
2

100R

22R

100n

2UA7

470R

3U15-2
100R

IUB4

3UB7-2
7
470R
3UB7-3
3
6
470R
3UB7-1
1
8

+5V

22u

2UB8

7UA7-2
4
BC847BS(COL)

+1V8
+12V

2UB0

7
IUB3
1K0 IUB2
3UB6-3
6
6
1K0
3UB6-4
2
4
5
1K0
3UB6-1
IUB5
7UA7-1
1
8
3 1
BC847BS(COL)
1K0
3UB7-4
4
5
5
3

CUA0

330R
1%

7UA6
BC817-25W
3UB6-2

3U12

+5V-TUN

1u0

B
FUA4

1K0

IUB6

470R

IUA9

3UA7

+5V5-TUN

+2V5-REF

FUA1

IUA2

+12V

22R

IUA4

3UA5

2UA4

2
IUA3

OUT
COM

1n0

IN

1K0

IUA1

2UA1

47K

7UA1-1
LM833
1

7UC0
LF25ABDT

7UA2
PHD38N02LT

100n

7UA0
TS2431

3UA2

3UA3

+2V5-REF
1

3K3 1%

FUA0

1K0

3UA4

2K2

3UA0

3UA1

+3V3
2UA0

100n

+12V

3K3 1%

+2V5-REF

NOT FOR 5000 SERIES

ENABLE-1V8
5

3UB1

SENSE+1V2

RESERVED
5UA0

1K0

30R
3U29-1

RES

+12V

470R

RES
5

470R

2
4

3U29-4

RES

NC

REF

470R
1

3U26-1

3U26-2

3U26-3

4K7

IN

OUT

INH

BP

+5V-TUN

IUB1

COM

RES
3UB5

3UB4

100K

1K0

IUB0

2UB3

+5V

470R
+3V3

NC

RES

470R

+5V5-TUN

1u0

3U29-3

7UA4
TS431AILT

2UB7

+3V3

IU30

3UB2

RES

4K7

470R

3UB3

3U29-2

100K RES

3U25-1

6
RES
7U06-1
BC847BS(COL)
1

3
RES
7U06-2
BC847BS(COL)
4

IU29

7UA5
LDS3985M50

1u0

100n
2UB6

3U25-2

100K RES

IUA6

2UB5

3U25-3

100K RES

3U25-4

100K RES

RES

22n
2UB4

470R
4

3U26-4

330p
RES

RES

470R

2UA0 A5
2UA1 A4
2UA2 B5
2UA3 B5
2UA4 A7
2UA5 B6
2UA6 B7
2UA7 D4
2UA8 D5
2UA9 D5
2UB0 C7
2UB1 D6
2UB2 D7
2UB3 F6
2UB4 F6
2UB5 F8
2UB6 F8
2UB7 F7
2UB8 D2
3U12 C3
3U13 C3
3U15-1 C8
3U15-2 C8
3U15-3 D8
3U15-4 D8
3U16-1 C9
3U16-2 C9
3U16-3 D9
3U16-4 D9
3U25-1 E3
3U25-2 E3
3U25-3 E2
3U25-4 E2
3U26-1 F3
3U26-2 F3
3U26-3 F3
3U26-4 F3
3U29-1 E3
3U29-2 E3
3U29-3 E3
3U29-4 F3
3UA0 A2
3UA1 A3
3UA2 B3
3UA3 B4
3UA4 A4
3UA5 A6
3UA6 B5
3UA7 B6
3UA8 B5
3UA9 D5
3UB0 D6
3UB1 E6
3UB2 E6

3UB3 F6
3UB4 F5
3UB5 F5
3UB6-1 C2
3UB6-2 C2
3UB6-3 C2
3UB6-4 C2
3UB7-1 D3
3UB7-2 D2
3UB7-3 D2
3UB7-4 C2
5UA0 E8
7U06-1 F2
7U06-2 F1
7UA0 B2
7UA1-1 A5
7UA1-2 C5
7UA2 A6
7UA3 C6
7UA4 E5
7UA5 E8
7UA6 C3
7UA7-1 C3
7UA7-2 D2
7UC0 A8
CUA0 B9
FUA0 A2
FUA1 A7
FUA2 D5
FUA3 D7
FUA4 B9
IU26 C3
IU29 E2
IU30 F3
IUA1 A4
IUA2 B5
IUA3 A6
IUA4 A6
IUA5 C6
IUA6 E5
IUA7 C4
IUA8 D5
IUA9 B6
IUB0 F6
IUB1 E8
IUB2 C2
IUB3 C3
IUB4 D3
IUB5 C2
IUB6 B3

DC/DC

2009-10-22

8204 000 8951


18770_523_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 103

DC/DC

DC/DC

B03E
2

5UD0

2U27 B8
2U28 D8
2UD0 A2
2UD1 A2
2UD2 A3
2UD3 B3
2UD4 B5
2UD5 B5
2UD6 B6
2UD7 B6
2UD8 C2
2UD9 C2
2UE0 C3
2UE1 D5
2UE2 D6
2UE3 D6
2UE4 D6
2UE5 E4
2UE6 E6
2UE7 F4
2UE8 F5
2UE9 B8
3U06 B8
3U07 D8
3UD0 B5
3UD1 B5
3UD2 B6
3UD3 D5
3UD4 D5
3UD5 D5
5UD0 A2
5UD1 A5
5UD2 C5
5UD3 C2
6UD0 A6
6UD1 E4
7U05-1 B7
7U05-2 D7
7UD0-1 A4
7UD0-2 B4
7UD1-1 C4
7UD1-2 D4
7UD2 E5
7UD3 F5
FUD2 C5
FUD3 A7
IU27 B8
IU28 D8
IUD0 A2
IUD1 C2
IUD2 D5
IUD3 A5
IUD4 C5
IUD5 E4
IUD6 B6
IUD7 A5

IUD0

+12V

FUD3

2UD7

33K
1%

12

68K
3UD1

1%
3UD0

VIA

10

4n7
3UD2

15

7UD0-2
ST1S10PH

13

IUD6

7U05-1
BC847BS(COL)
RES 1

120K

100n

22u

IU27

10K

RES 3U06

+1V1

RES 2U27

SS36

RES 2UE9

+5V
3u6

VFB
GND
P HS

6UD0

IUD7

220u 16V

SYNC

5UD1

2UD6

IUD3

SW

VIN

22u

INH

2UD4

RES 1n0

2UD3

ENABLE-3V3-5V

22u
2UD5

SW

10u

2UD2

10u

2UD1

10u

2UD0

7UD0-1
ST1S10PH

+5V5-TUN

30R

B03E

14

11

5UD3

3
7U05-2
RES
4

100n
IU28

D
RES 3U07

33K
1%

12

1M0
3UD5

VIA

10

3UD4

15

7UD1-2
ST1S10PH

13

IUD2

BC847BS(COL)

RES 2U28

220u 16V

2UE4

22u

3UD3

+1V1

10K

+3V3
3u6

VFB
GND
P HS

FUD2

5UD2

22u
2UE3

SYNC

IUD4

SW

VIN

2UE2

INH

1% 100K

4n7

SW

A
ENABLE-3V3-5V

2UE1

7UD1-1
ST1S10PH

10u

2UE0

10u

2UD9

10u

2UD8

30R

IUD1

+12V

14

11

IN

S1D

OUT

100n

2UE5

+2V5

COM

22u 16V

IUD5

+5V

2UE6

7UD2
LD1117DT25
6UD1

() FOR 5000 SERIES ONLY


() NOT FOR 5000 SERIES

7UD3
LD1117DT33

IN

OUT

+3V3

2UE8

100n

2UE7

COM

22u 16V

DC/DC

2009-10-22

8204 000 8951


18770_524_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 104

Temp Sensor + AmbiLight

B03F

Temp Sensor + AmbiLight

B03F
3

7
1UM0 A4
5UM0 A3
5UM1 A3
FUM0 A5
IUM0 A4

5UM1

1UM0

IUM0

+3V3

FUM0

V-AMBI

T 1.0A 63V

30R
5UM0
+5V
RES 30R

DC/DC

2009-10-22

8204 000 8951


18770_525_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 105

Fan Control

B03G

Fan-Control

B03G
2

+12V

+12V

1K0

FAN-CTRL1

IUS3 3US5-3
6
3

IUT1

100n

7
7US1-1
LM339P
14

2US3

10K

3US5-2

3US7

10K

3US4-1

+12V

10K

3US2

+3V3

IUS6

10K

7US2
BC807-25W

12
+12V

IUS7

IUT2

7US1-2
LM339P
13

22R

IUS4 3US5-4
5
4

10

FAN-CTRL2

10K

BC807-25W
7US3

IUS8

12

3US6

IUS9
47R

11

10K

3US3

+12V

10K

3US5-1

3US9

+3V3

FAN-DRV
+3V3

10K

7US1-3
LM339P
2

10K

3US4-3
3

+12V

IUS5

3US4-4

+12V

4
12

TACH01

RES

+12V

10K

3US4-2

9US0

+12V

7US1-4
LM339P
1

IUS0

12

TACH02

TACHO

2US3 A7
3US2 A3
3US3 B3
3US4-1 A4
3US4-2 D4
3US4-3 C4
3US4-4 C5
3US5-1 B6
3US5-2 A6
3US5-3 A5
3US5-4 B5
3US6 C6
3US7 A4
3US9 B6
7US1-1 A5
7US1-2 B5
7US1-3 C5
7US1-4 D5
7US2 A6
7US3 B6
9US0 D4
IUS0 D5
IUS3 A5
IUS4 B5
IUS5 C5
IUS6 A6
IUS7 B7
IUS8 B6
IUS9 B6
IUT1 A4
IUT2 B4

9
4

DC/DC

2009-10-22

8204 000 8951


18770_526_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 106

Vdisp Switch

VDisp-Switch

B03H
3

1 9UU0-1
RES
2 9UU0-2
RES
3 9UU0-3
RES
4 9UU0-4
RES
1 9UU1-1
RES
2 9UU1-2
RES
3 9UU1-3
RES
4 9UU1-4
RES

3UU0-2

6
5

8
7
6
FUU0

+VDISP-INT

2
IUU2

1u0

IUU1

3UU3-2

IUU3
7

47K RES
7UU3 RES
BC847BW

+3V3-STANDBY

47K

2
3

7UU2-1
PUMD12
1

C
IUU4 3UU3-3 IUU5 3UU3-4
6
3
4
5

3UU0-3

3UU0-1

47K

47K

47R
7

47K RES
2UU1

3UU1

IUU0

3UU3-1

7UU1
SI3441BDV

+12VD

7UU0
SI4835DDY
RES

4
PUMD12
7UU2-2

+3V3

47K RES

47K RES
2

100n

2UU0

B03H

IUU6

VDISP-SWITCH

3UU2

+3V3

4K7 RES

D
LCD-PWR-ONn

2UU0 C6
2UU1 C4
3UU0-1 C4
3UU0-2 C4
3UU0-3 C2
3UU1 C4
3UU2 D6
3UU3-1 C4
3UU3-2 C5
3UU3-3 C6
3UU3-4 C7
7UU0 B4
7UU1 B5
7UU2-1 C3
7UU2-2 C3
7UU3 C6
9UU0-1 A4
9UU0-2 A4
9UU0-3 A4
9UU0-4 A4
9UU1-1 A4
9UU1-2 A4
9UU1-3 A4
9UU1-4 A4
FUU0 A5
IUU0 C3
IUU1 C4
IUU2 C5
IUU3 C6
IUU4 C6
IUU5 C7
IUU6 D6

7
4

DC/DC / CLASS D

2009-10-22

8204 000 8951


18770_527_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 107

10-12 B04 820400089524 Analog I/O


Analogue Externals A

Analogue Externals A

B04A
1

B04A

10

11

12

13

RESET-AVPIP

2E50

1E45

100p
100p

2E51

3E25

100p

2E70

1E47

100p

2E82

1E48

RES 6E14

CDS4C12GTA
12V

100p

2E16

1E49

CDS4C12GTA
12V

RES 6E24

100p

2E33

1E56

12V

100p

2E17

CDS4C12GTA
12V

1E57

100p

2E19

1E52

RES 6E35

20

IE51

AV2-BLK

100n 16V

2E13

RES
3E48

1E01-2

68R

75R

RES 6E36

MRC-021V-29 PC

7E09-2
PUMH7

FE76
100p

CVBS-OUT-SC1

68R

MTJ-505H-01 NI LF

RES 2E77

3E45

3E61

FE85

CDS4C12GTA

RES 6E02

4K7

RES 6E34

2E93

150p
150p

2E95

150p

2E96
IE92

7E05
BC847BW

19

FE79

IE91

20

18

21

470R

19

17

+3V3

4K7

1 3EB6-1 8

15

3E37-2
2 100R 7
3E37-3

MT
FE78

3EB9-1

100p

RES 2E78

1E24

CDS4C12GTA
12V

RES 6E31

68R

10

11

12

470R
2 3EB9-2 7

1X02
REF EMC HOLE

470R
3EB6-3

3E63-2
100R
3E63-3

1K0
3E11-3
1K0

470R
3 3EB9-3 6

100R
3E11-2

100p

RES 2E76

2 3EB6-2 7

3 470R 6
2

68R

1K0

2 470R 7
3EA7-3

1K0

3EA7-2
FE77

3E52

RES
3E49
1E23

CDS4C12GTA
12V

470R

4 3EB9-4 5

100p

2E44

1E25

CDS4C12GTA
12V

RES 6E32
CVBS-OUT-SC1
RES 6E30

IE93

100R
3E07-2

3E07-3
3

470R
7E04
BC847BW

100p

100n

RES 6E37

IE94

2E41

3E39
27R

2E73

3E62

IE62

1E27

100p

RES 2E75

MRC-021V-29 PC

CDS4C12GTA
12V

+5V

22

AV2-CVBS
1E22

CDS4C12GTA
12V

RES 6E29

75R

23

1EP2

3E86

3E73

IE96

18

FE67

16

18R

1u8

14

18R

17

4 3EB6-4 5

9E06

BEC2

12
11
10
9
8
7
6
5
4
3
2
1

11

13

100n

2E74

16

CDS4C12GTA
12V

RES 6E12

100p

2E32

100p

2E31
150p

2E92

150p

2E89

150p

2E94

18p

39p

2E98

18K

2E97

1
2
1

3E19

3E17

39K

1u0

3E18 2

2EB3

330R

18R

5E79

8
9
10

FE66

3E84

RES

IE57

FE64

12

RES

IE17

100n

2E24

4K7

BEC1

1u8

470R

100p

2E12

FE82
9E09

FE84

27R

5E78

IE56

AV4-Y

15

3E43
AV1-CVBS

CVBS-MON-OUT1

6
FE68

1E26

100p

2E14

FE81

IE52

10u

+5V

14

5E80

13

IE48

7E09-1
PUMH7

IE59

AV4-PR

21
3E44

9E02

1K0

3EA1

2EB1

9E01

100n

1 3EB3 2

100p

2E18

1E55

9E10

FE83

AV1-BLK

3E83 18R
5p6

12

9E07

1E19

150p

2E86

2E85

10

2E99

2u2

4
5

FE63

3E16 12K

11

+3V3

* EU

IE05

2E81

* EU

YPBPR2-SYNCIN2

IE14

3E79

RES

820R

9E05

18R

18R

3E85
1E18

CDS4C12GTA
12V

RES

6E26

BEC5

5E76
1u8

BC847BPN(COL)

AV2-STATUS

IE70

IE60
1
1 3EB1 2

9E08

18R

CDS4C12GTA
12V

IE55

IE16
3E78

AV1-R

3 BC847BPN(COL)

IE08

RES

7E06-1

1E02

3E82

RES

FE74
FE75

9E55

9E54

7E06-2
5

FE80

18R

AP

IE61

FE73

3E77

150p

2E84

150p

1u8

RES 6E28

YPBPR1-PR

150p

BEC4

5E74

IE54
2E83

AV1-G

CDS4C12GTA
12V

3E76 18R

1u8

BEC0

IE89

RES 6E22

9E53

5E77

IE13

4K7

3E32

AP
9E52

1R0

2E91

3E31
12K

FE55

(AV2)

CDS4C12GTA
12V

100p

2E90

1E53
1E54

100p
100p

* EU
IE18

YPBPR1-SYNCIN1

IE90

AV1-STATUS

1K0

1E01-1
2E15

150p

RES

AV4-PB

(AV1)

18R
2E80

150p

SCART1

SCART2

3E11-4

3E80 18R

+5V

1E12

1u8

IE21
4

3E75
CDS4C12GTA
12V

BEC3

RES 6E23

AV1-B

2E79

5E73

AUDIO-IN2-L

3EA2

3E74 18R

IE53

CDS4C12GTA
12V

9E51

A-PLOP

* EU

RES 6E09

2E04

9E50

100R

2K2

1K0 8

100p

YPBPR1-PB

CDS4C12GTA
12V

RES 6E07

100p

2E10
AUDIO-IN1-L

AP

3E24

FE62

3E63-4

10K

AP-SCART-OUT-L

FE72

3E07-1

FEC8
+3V3

4
PUMH7

1 100R 8

IE23

1E46

RES 6E08

CDS4C12GTA
12V

100p
100p

2E30

AP-SCART-OUT-R

1K0

CDS4C12GTA
12V

100p

2E88

AUDIO-OUT-R
1u0 16V

FE61

3E11-1
1

IE68

2EA5

CDS4C12GTA
12V

IEC2

5 470R 4
FEA1

7E01-2 3
1E31

RES 6E03

IE20

AUDIO-IN2-R

3E37-1

AP-SCART-OUT-L

FE71

100p

2E06

1K0

RES 6E10

100p

1E00

2E87

PUMH7

CDS4C12GTA
12V

AP-SCART-OUT-L

100R

IEC1

3E07-4

AUDIO-IN1-R

1u0 16V

2E29

8 470R 1
FEA0

7E01-1 6

IE67

2EA4

AUDIO-OUT-L

3EA7-4

IE22

CDS4C12GTA
12V

100p

RES 6E01

4 100R 5
2E01

IEC0

3EA7-1

FE60

3E63-1

AP-SCART-OUT-R
FE70

3E37-4

AP-SCART-OUT-R

13

470R

1E00 A4
1E01-1 D5
1E01-2 H5
1E02 C13
1E12 D4
1E18 F4
1E19 F4
1E22 H4
1E23 I4
1E24 I11
1E25 I4
1E26 G11
1E27 H11
1E31 B4
1E45 A11
1E46 B11
1E47 C11
1E48 C11
1E49 D11
1E52 F11
1E53 C4
1E54 D4
1E55 E4
1E56 E11
1E57 E11
1EP2 F13
2E01 A3
2E04 D3
2E06 B3
2E10 C3
2E12 F4
2E13 G11
2E14 F4
2E15 D4
2E16 D12
2E17 E12
2E18 E4
2E19 F12
2E24 G2
2E29 A10
2E30 B10
2E31 C10
2E32 C10
2E33 E12
2E41 H12
2E44 I4
2E50 A12
2E51 B12
2E70 C12
2E73 H7
2E74 F7
2E75 H4
2E76 I4
2E77 G12
2E78 I12
2E79 D1
2E80 D2
2E81 E7
2E82 C12
2E83 F1
2E84 F2
2E85 F1
2E86 F2
2E87 A4
2E88 B4
2E89 D9
2E90 C4
2E91 D4
2E92 D10
2E93 E10
2E94 E9
2E95 F10
2E96 F9
2E97 E8
2E98 E8
2E99 E8
2EA4 A7
2EA5 B7
2EB1 D6
2EB3 E7
3E07-1 C3
3E07-2 H13
3E07-3 H13
3E07-4 B3
3E11-1 B11
3E11-2 I13
3E11-3 I13
3E11-4 C11
3E16 D11
3E17 E10
3E18 E7
3E19 E7
3E24 C7
3E25 C13
3E31 E3
3E32 E3
3E37-1 C3
3E37-2 G13
3E37-3 H13
3E37-4 A3
3E39 H10
3E43 H2
3E44 G2
3E45 G7
3E48 G7
3E49 I7
3E52 H7
3E61 G11
3E62 H2
3E63-1 A11
3E63-2 I13
3E63-3 I13
3E63-4 B11
3E73 G10
3E74 D2
3E75 D2
3E76 E2
3E77 E2

3E78 F2
3E79 F2
3E80 C10
3E82 D10
3E83 E10
3E84 E10
3E85 F10
3E86 F10
3EA1 D6
3EA2 D6
3EA7-1 A7
3EA7-2 H13
3EA7-3 H13
3EA7-4 B7
3EB1 E6
3EB3 E6
3EB6-1 G6
3EB6-2 H13
3EB6-3 H13
3EB6-4 G6
3EB9-1 H6
3EB9-2 I13
3EB9-3 I13
3EB9-4 I6
5E73 D2
5E74 E2
5E76 F2
5E77 D10
5E78 E10
5E79 F10
5E80 E8
6E01 A3
6E02 E11
6E03 B3
6E07 C3
6E08 B11
6E09 D3
6E10 A11
6E12 C11
6E14 C11
6E22 E3
6E23 D3
6E24 D11
6E26 F3
6E28 F3
6E29 H3
6E30 I3
6E31 I11
6E32 I3
6E34 E11
6E35 F11
6E36 G11
6E37 H11
7E01-1 A6
7E01-2 B6
7E04 H6
7E05 G6
7E06-1 E7
7E06-2 E6
7E09-1 H2
7E09-2 G10
9E01 D6
9E02 D7
9E05 F4
9E06 G4
9E07 F4
9E08 F4
9E09 G4
9E10 F4
9E50 D1
9E51 D2
9E52 E1
9E53 E2
9E54 F1
9E55 F2
BEC0 D10
BEC1 E10
BEC2 F10
BEC3 D2
BEC4 E2
BEC5 F2
FE55 D9
FE60 A12
FE61 B12
FE62 B12
FE63 D12
FE64 D12
FE66 E12
FE67 E12
FE68 D12
FE70 A5
FE71 B4
FE72 C4
FE73 E4
FE74 E4
FE75 E4
FE76 G12
FE77 H12
FE78 H12
FE79 F13
FE80 E4
FE81 F4
FE82 F4
FE83 G4
FE84 G4
FE85 G5
FEA0 A7
FEA1 B7
FEC8 B13
IE05 D10
IE08 E5
IE13 D6
IE14 F5
IE16 F5
IE17 G5
IE18 E3
IE20 B10
IE21 C10

IE22 B2
IE23 C2
IE48 G2
IE51 G10
IE52 H2
IE53 D1
IE54 E1
IE55 F1
IE56 E9
IE57 F9
IE59 E8
IE60 E6
IE61 E6
IE62 H10
IE67 A8
IE68 B8
IE70 E7
IE89 D7
IE90 D7
IE91 G6
IE92 G7
IE93 H7
IE94 H6
IE96 G6
IEC0 A7
IEC1 A6
IEC2 B7

CLASS D

2009-10-22

8204 000 8952


18770_528_100118.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 108

Analogue Externals B

B04B
1

Analogue Externals B
2

B04B
4

10

12

11

13

14

A
SPDIF out
YPBPR

FE42

5E06

CDS4C12GTA
12V

3E89

IE76

9E58

3E90

RES 6E46

10p

AV2-CVBS

IE75

1E07
CON_JACK

FE59

30R

CDS4C12GTA
12V

SPDIF-OUT

YPBPR1-SYNCIN1
IE73

1
2 YKB11-0946V
FE41

AV3-PB

18R

YPBPR1-PB

IE77

AV3-PR

18R

CDS4C12GTA
12V

RES 6E52

1E39

100p

2E68

IE74

9E57

EU

1E04

AV3-Y

27R

FE48

MTJ-032-21B-41 NI FE
2

3E88

9E04

EU
RES 6E51

1E28

100p

2E67

IE15

IE72

1E44

AP

FE51

MTJ-032-21B-41 NI FE
2
1E03

3E87

2E22

RES 6E40

IE71

9E29

18R

CDS4C12GTA
12V

1E43

100p

1
YELLOW

EU

FE54

YKC21-5598
2
2E27

1E08-1

YPBPR1-PR

YPBPR AUDIO

FE49
CDS4C12GTA
12V

100p

2E72

IE29

3E96

RES 6E38

1E42

100p

3
WHITE

2E40

YKC21-5598
4

AUDIO-IN3-L

1K0
100p

FE43

AUDIO-IN3-R
IE31

1K0

2E71

100p

RED

RES 6E06

FE50

1E08-2

CDS4C12GTA
12V

3E97

YKC21-5598
6
1E29

1E08-3

2E39

VGA ( OR DVI ) AUDIO

IE09
AUDIO-IN4-L

1K0

100p

6E19

3E21
CDS4C12GTA
12V

1n0
1E37

2E36

V_NOM

FE02

3
7
MSJ-035-10A B AG PPO 8
1

2E35

5
4
2

1E09

FE01

AUDIO-IN4-R

100p

1K0
2E38

6E20

CDS4C12GTA
12V

1n0
1E38

V_NOM

2E37

IE10

3E20

FE03

SVHS IN

H
3E15

CDS4C12GTA
12V

RES 6E16

BE22

1E76

FE46

2E21

100p

MDC-066H-A LF
1ECB

C-SVHS

18R

BE21

FE45

3
1

3E14

CDS4C12GTA
12V

2
4

BE20

RES 6E15

1E75

2E20

100p

FE44

Y-SVHS

27R

10

11

12

13

1E03 B3
1E04 C3
1E07 A12
1E08-1 B3
1E08-2 E3
1E08-3 D3
1E09 F3
1E28 B4
1E29 D4
1E37 F4
1E38 G4
1E39 C4
1E42 E4
1E43 B4
1E44 B10
1E75 H5
1E76 I5
1ECB I4
2E20 H4
2E21 I4
2E22 B9
2E27 B4
2E35 F6
2E36 F4
2E37 G4
2E38 G6
2E39 D4
2E40 E4
2E67 B4
2E68 C4
2E71 E5
2E72 D5
3E14 H6
3E15 H6
3E20 G5
3E21 F5
3E87 B6
3E88 B6
3E89 B6
3E90 C6
3E96 E5
3E97 D5
5E06 B9
6E06 D5
6E15 H5
6E16 I5
6E19 F5
6E20 G5
6E38 E5
6E40 B5
6E46 B11
6E51 B4
6E52 C4
9E04 B5
9E29 B5
9E57 B5
9E58 C5
BE20 H6
BE21 H6
BE22 I4
FE01 F4
FE02 F5
FE03 G5
FE41 B12
FE42 C4
FE43 D4
FE44 H5
FE45 H5
FE46 I4
FE48 C4
FE49 E4
FE50 D4
FE51 B4
FE54 B4
FE59 B10
IE09 F6
IE10 G6
IE15 B9
IE29 E6
IE31 D6
IE71 B6
IE72 B7
IE73 B7
IE74 B6
IE75 B7
IE76 C6
IE77 C7

14
4

ANALOG I/O

2009-10-22

8204 000 8952


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100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 109

Ethernet + Service

Ethernet + Service
2

10

12

13

14

+3V3-ET-ANA
IE49

2 3E53-2 7

47R
4 3E53-4 5

RXD1-MIPS

6E43
IE38

IE32
3E30

3E53-1
47R
3E53-3

FE56

1E06
3

FE57

2
3
1

47R

YKB21-5157V

UART
SERVICE
CONNECTOR

FE58

10u

2E48

100n

2E49

4n7

2E52

100n
2E53

IE33

1M0
1E70
NX3225GA

+3V3

IE06

BZX384-C5V1

47R

+3V3

+3V3-ET-ANA

IE50

1E86

TXD1-MIPS

1E85

100n

100n
2E66

2E62

10u
2E63

30R

11

IE07

5E08
+3V3

6E44

B04C

BZX384-C5V1

B04C

19

ETH-COL

15
3E71
RES

9E43

21

ETH-TXD(0)
ETH-TXD(1)
ETH-TXD(2)

22
23
24
25
18

ETH-TXD(3)
ETH-TXER

1K5

12

RXER
RXD4
0
PHYAD
1
RXCLK

0
1
2 TXD
3
4
INT
TXER

REGOFF
1
LED
2
INTSEL
CRS
RBIAS

31
30

ETH-RXP
ETH-RXN

29
28

ETH-TXP
ETH-TXN

20

ETH-TXCLK

26

ETH-RXDV

IE63

13

10K

+3V3

RES

ETH-RXCLK

10K

3E65

+3V3

RES

3
10K

3E34

10K

3E72

14

3E68
RES
3E35
RES

ETH-REGOFF

10K

+3V3
ETH-INTSEL

10K

+3V3

9E42

ETH-CRS

32
IE39

MDC
MDIO

ETH-RXER

3E64
IE64

VSS

+3V3

33

3E51

P
N

RXDV

TXEN

17
16

ETH-MDC
ETH-MDIO

P
N

TXCLK

COL
CRS_DV
MODE2

10K

ETH-TXEN

TX

0
MODE
1
RMIISEL
PHYAD2
RXD<0:3>

10K

3E69
RES
10K

3E70
RES

RX

RST

11
10
9
8

ETH-RXD(0)
ETH-RXD(1)
ETH-RXD(2)
ETH-RXD(3)

IO

12K1
1%

IE26

1A 2A
VDD

3E40

27

CR
CLKIN
1
XTAL
2

5
4
RESET-ETHERNETn

10p

2E54

10p

7E10-1
LAN8710A-EZK

2E55

10K

10K

3E33

10K
3E67 RES

3E66 RES

25M

7E10-2
LAN8710A-EZK
34
35

36
37

VIA

+3V3-ET-ANA

F
22R

3E98

22R

3E26

CONFIGURATION RESISTOR SETTINGS

6E50
RES

NUP1301ML3

3E95-4

5 100R 4

6 100R 3

6E49
RES

NUP1301ML3

3E95-3

7 100R 2

3E95-1
NUP1301ML3

6E48
RES

8 100R 1
3E95-2

2 100R 7

1 100R 8
3E22-2

6E47
RES 3E22-1

4 100R 5
NUP1301ML3

3E22-3

3 100R 6
3E22-4

EMPTY

POP

Resistor

ETHERNET CONNECTOR

1N00
FE27

ETH-TXP
ETH-TXN
ETH-RXP

FE29
FE30
FE31

22n

2E60

15p

2E59

BE03

3E64 (RES)

1
2
3
4
5
6
7
8
1551151-1

RES

15p

2E58
RES

15p

RES 2E57

15p

RES 2E56

ETH-RXN

BE00
BE01
BE02

FE28

FE34

PHYADD(0) = 1

PHYADD(0) = 0

3E65 (RES)

PHYADD(1) = 1

PHYADD(1) = 0

3E66 (RES)

PHYADD(2) = 1

PHYADD(2) = 0

3E67 (RES)

RMII mode selected

MII mode selected

3E68 (RES)

Internal 1.2V reg. disabled

Internal 1.2V reg. enabled

3E69 (RES)

MODE(0) = 0

MODE(0) = 1

3E70 (RES)

MODE(1) = 0

MODE(1) = 1

3E71 (RES)

MODE(2) = 0

MODE(2) = 1

3E72

INTERRUPT FUNCTION

INTERRUPT FUNCTION

DISABLED ON

ENABLED ON

nINT/TXER/TXD4 SIGNAL

nINT/TXER/TXD4 SIGNAL

FE32

ETH-INTSEL
ETH-REGOFF

FE33

10

11

12

13

14

1E06 A13
1E70 B3
1E85 A11
1E86 A11
1N00 G7
2E48 B5
2E49 B5
2E52 B3
2E53 B4
2E54 B3
2E55 B3
2E56 H2
2E57 H2
2E58 H3
2E59 H4
2E60 H5
2E62 A3
2E63 A3
2E66 A3
3E22-1 F2
3E22-2 F3
3E22-3 F2
3E22-4 F2
3E26 F5
3E30 B3
3E33 B2
3E34 D6
3E35 D6
3E40 D5
3E51 E1
3E53-1 A10
3E53-2 A9
3E53-3 A10
3E53-4 A9
3E64 C6
3E65 D6
3E66 B2
3E67 B2
3E68 D6
3E69 C2
3E70 C1
3E71 C3
3E72 D6
3E95-1 F3
3E95-2 F3
3E95-3 F4
3E95-4 F4
3E98 F5
5E08 A3
6E43 A9
6E44 A10
6E47 G2
6E48 G3
6E49 G4
6E50 G5
7E10-1 B4
7E10-2 E4
9E42 D5
9E43 C3
BE00 G6
BE01 G6
BE02 G6
BE03 H6
FE27 G6
FE28 G6
FE29 G6
FE30 G6
FE31 H6
FE32 I5
FE33 I5
FE34 H6
FE56 A11
FE57 A11
FE58 A11
IE06 B4
IE07 A3
IE26 C2
IE32 B3
IE33 B3
IE38 B4
IE39 D5
IE49 A10
IE50 A9
IE63 C6
IE64 C6

ANALOG I/O

2009-10-22

8204 000 8952


18770_530_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 110

HDMI

B04D

HDMI

B04D

10

11

12

13

14

I2C Address

ARX1ARX0+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FECG 21

10K

3ECH

1u0

10u

100n

2EC0

2ECV

BRX2BRX1+

ARX1ARX1+

69
70

ARX2ARX2+

71
72

BIN-5V
BRX-HOTPLUG

BRX-DDC-SCL
BRX-DDC-SDA

FECE
FECF

BIN-5V

47K

BRXCPCEC-HDMI

BIN-5V

10R

BRX-DDC-SDA
BRX-DDC-SCL

7
100K
1u0

BRX-DDC-SCL
BRX-DDC-SDA

BRX-HOTPLUG

CIN-5V
CRX2+

2 3ECM-2 7

3
3ECN-3

10R

CRX-DDC-SDA
CRX-DDC-SCL

1u0

CRX2CRX1+
CRX1CRX0+

47K

CIN-5V
CRX-HOTPLUG

20
23 22

3E23
RES
7E02
BC847BW

PCEC-HDMI

100R

1u0

5EC2

eHDMI+

30R
ARC-eHDMI+

CIN-5V

IEC4

4
3ECN-4

10R

DRX-DDC-SDA
DRX-DDC-SCL

22K
RES

7EC0
BC847BW

3ECD

+3V3-STANDBY

DIN-5V

1 3ECM-1 8

2ECC

1
2

BRX0BRX0+

3
4

BRX1BRX1+

5
6

6
100K

7
8

IE44

41
42
39
40

2ECP

CRXCCRXC+

11
12

CRX0CRX0+

13
14

CRX1CRX1+

15
16

CRX2CRX2+

17
18

DRX-HOTPLUG

47K

FECM
FECN

CRX-DDC-SCL
CRX-DDC-SDA
3 3ECA-3 6

FECA

5 3ECA-4 4

CIN-5V

CRX0CRXC+

FECJ

33
34

BRX2BRX2+

HDMI CONNECTOR 1

FECK
FECL

2ECN

35
36

CRX-HOTPLUG

1P02

CRXCPCEC-HDMI
ARC-eHDMI+
CRX-DDC-SCL
CRX-DDC-SDA

IE43

BRXCBRXC+

20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FECP19
21

3 3ECM-3 6

2
3ECN-2

5
100K

IE45

2ECQ

45
46
43
44

DRXCDRXC+

19
20

DRX0DRX0+

21
22

DRX1DRX1+

23
24

DRX2DRX2+

25
26

CEC-HDMI

IEC5

100n

10u

RES 2ECW

3ECP-1 3ECP-3

N
R0XC
P

DSCL4
DSDA4

N
R0X0
P

CEC_D

49

10K

+5V-EDID

R4PWR5V

48
47

VGA-SCL-EDID-HDMI
VGA-SDA-EDID-HDMI

51

9EC2

CEC-HDMI

RES

N
R0X1
P
N
R0X2
P
TX2

(CBUS) HPD1
R1PWR5V
DSDA1
DSCL1
N
R1XC
P

N
P

TX1

N
P

TX0

N
P

TXC

N
R1X0
P

N
P

57
56

HDMIA-RX2HDMIA-RX2+

59
58

HDMIA-RX1HDMIA-RX1+

61
60

HDMIA-RX0HDMIA-RX0+

63
62

HDMIA-RXCHDMIA-RXC+
3ECJ RES

N
R1X1
P

TPWR_CI2CA

N
R1X2
P

CEC_A

(CBUS) HPD2
R2PWR5V

INT

4K7

55

50

52

IE12
FECR

RES
3ECK

MICOM-VCC33

4K7
9EC3
RES

FECY

PCEC-HDMI
3ECL RES

+3V3

4K7

DSDA2
DSCL2
N
R2XC
P

CSCL
CSDA

N
R2X0
P
RSVDL

N
R2X1
P

54
53 3EC3
3EC5

100R
100R

SCL-SSB
SDA-SSB

10
28

N
R2X2
P

(CBUS) HPD3
R3PWR5V
DSDA3
DSCL3
N
R3XC
P
VIA

N
R3X0
P
N
R3X1
P

IEC6
9EC0

38

37

DSDA0
DSCL0

SBVCC33

9
27
64
(CBUS) HPD0
R0PWR5V

10K

29
30

BRX2+

BRX0BRXC+

FECC
FECD

+3V3

30R

2ECM

31
32

MICOM_VCC33

IE42

67
68

BRX1BRX0+

100n

100n
2EC8

100n
2EC7

2EC6
8
100K

ARX0ARX0+

BIN-5V

1u0

AIN-5V

23 22

10R
ARX-DDC-SDA
ARX-DDC-SCL

10p

1
3ECN-1

65
66

47K

AIN-5V

3ECM-4

ARXCARXC+

HDMI CONNECTOR 2

1P03

3 3EC1-3 6

47K
47K

ARX-HOTPLUG

20
23 22

VCC33

ARX-HOTPLUG

8 3EC1-1 1

FEC5

7EC1
SII9287B

ARX-DDC-SCL
ARX-DDC-SDA

FEC4
AIN-5V

RES
5EC3

+3V3-HDMI

ARXCPCEC-HDMI
ARX-DDC-SCL
ARX-DDC-SDA

FEC7

AIN-5V

ARX0ARXC+

FEC1
FEC2

SII9187A = 0xB2

FECB

ARX2ARX1+

7 3ECA-2 2

30R

MICOM-VCC33

2EC3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FEC6 21

1 3ECA-1 8

ARX2+

220u 16V

RES 2EC1

+3V3

HDMI CONNECTOR 3
1P04

FEC3

FEC0

2EC2

5EC0

N
R3X2
P

74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89

1P02 E2
1P03 C2
1P04 A2
2EC0 A9
2EC1 A8
2EC2 A10
2EC3 B10
2EC6 B9
2EC7 B9
2EC8 B9
2ECC G8
2ECM B8
2ECN D8
2ECP E8
2ECQ F8
2ECU I3
2ECV A9
2ECW B10
3E23 F4
3EC1-1 B4
3EC1-3 B4
3EC3 E10
3EC5 E10
3ECA-1 D4
3ECA-2 D4
3ECA-3 F4
3ECA-4 F4
3ECD G3
3ECE H3
3ECF I3
3ECG I3
3ECH A10
3ECJ D10
3ECK D11
3ECL E11
3ECM-1 F8
3ECM-2 E8
3ECM-3 D8
3ECM-4 B8
3ECN-1 B8
3ECN-2 D8
3ECN-3 E8
3ECN-4 F8
3ECP-1 B10
3ECP-3 B10
3ECU-2 I8
3ECU-4 I8

5EC0 A8
5EC2 F7
5EC3 A11
6EC1 H3
7E02 G3
7EC0 G3
7EC1 B9
9EC0 G4
9EC2 C11
9EC3 E11
FEC0 A9
FEC1 B2
FEC2 B2
FEC3 A10
FEC4 B2
FEC5 B2
FEC6 B2
FEC7 A10
FECA F3
FECB A10
FECC D2
FECD D2
FECE D2
FECF D2
FECG D2
FECJ F2
FECK F2
FECL F2
FECM F2
FECN F2
FECP F2
FECR E10
FECW H9
FECY E10
FECZ I3
IE11 I3
IE12 D10
IE42 B8
IE43 D8
IE44 E8
IE45 F8
IE65 I7
IE66 I7
IEC4 G3
IEC5 G3
IEC6 G4
IEC7 H3

73

EPAD

22K

3ECE

IEC7

7EC1

3ECN

NON-INSTAPORT

9187A

4X 3K3

3K3

INSTAPORT

9287B

4X 100K

100K

FECW
+3V3-STANDBY

H
6EC1

3ECF

+5V-VGA

+5V
BAT54

3ECF

4R7

3ECG

IE11

FECZ

100K

DDCA-SDA

DDCA-SCL

2ECU

IE65

2 3ECU-2 7

IE66

10K
4 3ECU-4 5

+3V3

10K
1u0

+5V-EDID

10

11

12

13

14
4

HDMI

2009-10-22

8204 000 8952


18770_531_100118.eps
100118

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 111

Headphone

B04E

Headphone

B04E
2

+3V3-STANDBY

4
PUMD12
7EE0-2
A-PLOP
3

B
6

A-STBY

FEE0
RESET-AUDIO

7EE0-1
PUMD12
1

C
2EE0

6
22K

22K

3EE1-3

3EE1-4

3EE1-2

22K

47p
3EE1-1

22K
2EE5

7EE1
TPA6111A2DGN

100n

2EE1

47p +3V3

ADAC(3)
IEE2
ADAC(4)

2EE3
1u0

IEE1
2EE4

3EE0-1
10K

IEE3
1

2
5

3EE0-4
10K

1u0

6
IEE4

5
2EE2

IEE6

AMPLIFIER

3EE0-3
10K

2EE6

IEE7

3EE2-2

FE36
7

VO

BYPASS

2EE7

IEE8

3EE2-3

FE35
6

AMP2

33R

4V 100u

10
11

AMP1

33R

4V 100u

SHUTDOWN

4
3

IN2

3EE2-1
33R

VIA
GND GND_HS

1u0

A-PLOP

VDD

3EE2-4

33R

IEE0

6
IEE5

2EE0 C5
2EE1 D5
2EE2 E4
2EE3 E2
2EE4 E3
2EE5 D5
2EE6 E6
2EE7 E6
3EE0-1 E3
3EE0-3 F3
3EE0-4 E3
3EE1-1 C5
3EE1-2 D8
3EE1-3 D8
3EE1-4 D5
3EE2-1 D7
3EE2-2 E7
3EE2-3 E7
3EE2-4 E7
7EE0-1 B5
7EE0-2 B6
7EE1 D4
FE35 E7
FE36 E7
FEE0 B4
IEE0 E2
IEE1 E2
IEE2 E2
IEE3 E3
IEE4 E3
IEE5 F3
IEE6 E4
IEE7 E6
IEE8 E6

9
4

AUDIO

2009-10-22

8204 000 8952


18770_532_100119.eps
100119

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 112

10-13 B05 820400089535 DDR


DDR

DDR

B05A
1

B05A
2

+1V8

10

11

+1V8

DDR2-VREF-DDR

13

12

DDR2-VREF-DDR

DDR2-CLK_P
DDR2-CLK_N

3B28

DDR2-CLK_P

240R

DDR2-CLK_N

G2
G3
G1

DDR2-BA2

DDR2-ODT
RES
240R

3B01
DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM2

F9
E8
F8
F2
G8
F7
G7
F3
B3

3B23

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
C23B02-4 4
D7
D33B02-2 2
D1
D93B00-4 4
B1
B9 3B00-1 1

NU|RDQS

2
5
33R 3
7
33R 1
5
33R
3
8
33R

B7
A8

3B00-2

2p2

7
33R
6 3B00-3
33R
8 3B02-1
33R
6 3B02-3
33R

3B12
33R

3B13
2B44
RES

0
1 BA
2

DDR2-D16
DDR2-D17
DDR2-D18
DDR2-D19
DDR2-D20
DDR2-D21
DDR2-D22
DDR2-D23

DDR2-DQS2_P
DDR2-DQS2_N

33R

A2

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

G2
G3
G1

DDR2-BA0
DDR2-BA1
DDR2-BA2

DDR2-ODT

ODT

3B03

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

L3
L7

NC

DDR2-A14

VSSQ

VSSDL

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM3

E7

F9
E8
F8
F2
G8
F7
G7
F3
B3

RES
240R

3B24
33R

2B17
100n
2B37
100p
VDD

VDDL

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B16

100n
2B15

100n
2B14

100n
2B13

100n
2B12

100n
2B11

100n
2B10

2B41

E2

E1

A3
E3
J1
K9

33R

47u
2B09

2B36
100p
2B08
100n

DDR2-BA0
DDR2-BA1

7B03
EDE1108AGBG-1J-F

VREF

VDDQ

VREF

VDDQ

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
3B05-3
C2
3B04-3
D7
D3
D1
D93B04-4
B1
B93B04-1

4
1

B7
A8

3B15
RES
2p2

2B45

0
1 BA
2

NU|RDQS

2 3B04-2 7
6
33R
6 33R
33R 2
33R
7 3B05-2
1
8 3B05-1
33R
5
5 3B05-4
4
33R
33R
8
33R

3
3

3B14
33R

DDR2-D24
DDR2-D25
DDR2-D26
DDR2-D27
DDR2-D28
DDR2-D29
DDR2-D30
DDR2-D31

DDR2-DQS3_P
DDR2-DQS3_N

33R

A2

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

L3
L7

DDR2-A14

VSSQ

VSSDL

A7
B2
B8
D2
D8

3B27
240R

VDDL

E7

DDR2-CLK_P
DDR2-CLK_N

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

A3
E3
J1
K9

3B22
240R

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

A7
B2
B8
D2
D8

AT T-POINT

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A1
E9
L1
H9

7B02
EDE1108AGBG-1J-F

A9
C1
C3
C7
C9

100n

100n
2B07

100n
2B06

100n
2B05

100n
2B04

100n
2B03

100n
2B02

100n
2B01

2B40

47u
2B00

E
+1V8

+1V8
DDR2-VREF-DDR

33R

B7
A8
2B46

0
1 BA
2

NU|RDQS

5
33R
7
33R
5
33R
8
33R

3B17
RES
2p2

2 3B07-2 7
33R
3
6 3B07-3
33R
1
8 3B08-1
33R
3
6 3B08-3
33R

3B16
33R

DDR2-D0
DDR2-D1
DDR2-D3
DDR2-D2
DDR2-D4
DDR2-D5
DDR2-D6
DDR2-D7

DDR2-DQS0_P
DDR2-DQS0_N

33R

A2

DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

DDR2-BA0
DDR2-BA1

G2
G3
G1

DDR2-BA2

DDR2-ODT

ODT

3B09

CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

L3
L7

NC

VSSDL

DDR2-A14

VSSQ

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM1

RES
240R

3B26
33R

F9
E8
F8
F2
G8
F7
G7
F3
B3

2B35
100n
2B39
100p
VDD

VDDL

VDDQ

E2

A9
C1
C3
C7
C9

E1

A1
E9
L1
H9

100n

100n
2B34

100n
2B33

100n
2B32

100n
2B31

100n
2B30

100n
2B29

100n
2B28

47u
2B27

E2

E1

DQS

C8
C23B08-4 4
D7
D3 3B08-2 2
D1
D9 3B07-4 4
B1
B9 3B07-1 1

VREF

0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

SDRAM
DQ

0
1
2
3
4
5
6
7

DQS

C8
3B11-3 3
C2
D7
3B10-3 33R 3
D3
D1
D93B10-4 4
B1
B93B10-1 1

B7
A8
2B47

0
1 BA
2

NU|RDQS

2
6
6 33R
2
1
5 3B11-1
4
33R
8
33R

3B19
RES
2p2

3B10-2

7
33R

7 3B11-2
8 33R
33R
5 3B11-4
33R

3B18
33R

DDR2-D8
DDR2-D9
DDR2-D10
DDR2-D11
DDR2-D12
DDR2-D13
DDR2-D14
DDR2-D15

DDR2-DQS1_P
DDR2-DQS1_N

33R

A2

3B02-1 C7
3B02-2 B6
3B02-3 C7
3B02-4 B6
3B03 D9
3B04-1 C12
3B04-2 B13
3B04-3 B12
3B04-4 C12
3B05-1 C13
3B05-2 C13
3B05-3 B12
3B05-4 C13
3B06 H3
3B07-1 G6
3B07-2 G7
3B07-3 G7
3B07-4 G6
3B08-1 G7
3B08-2 G6
3B08-3 G7
3B08-4 G6
3B09 H9
3B10-1 G12
3B10-2 G13
3B10-3 G12
3B10-4 G12
3B11-1 G12
3B11-2 G13
3B11-3 G12
3B11-4 G13
3B12 C7
3B13 C6
3B14 C13
3B15 C12
3B16 H7
3B17 H7
3B18 H13
3B19 H12
3B20 H1
3B21 I1
3B22 B1
3B23 D3
3B24 D9
3B25 I3
3B26 I9
3B27 C1
3B28 C1
7B00 G4
7B01 G10
7B02 B4
7B03 B10
FB00 H1

ODT
CK
CKE
CS
RAS
CAS
WE
DM|RDQS
VSS

NC

VSSDL

L3
L7

DDR2-A14

VSSQ
A7
B2
B8
D2
D8

3B21

180R 1%

3B25

DQ

0
1
2
3
4
5
6
7

E7

FB00
DDR2-VREF-DDR

DDR2-CLK_P
DDR2-CLK_N
DDR2-CKE
DDR2-CS
DDR2-RAS
DDR2-CAS
DDR2-WE
DDR2-DQM0

F9
E8
F8
F2
G8
F7
G7
F3
B3

RES
240R

3B06

SDRAM

A3
E3
J1
K9

3B20

180R 1%

DDR2-ODT

7B01
EDE1108AGBG-1J-F

VREF

A3
E3
J1
K9

DDR2-BA2

VDDQ

2B43

2B26
100n
2B38
100p

DDR2-BA0
DDR2-BA1

G2
G3
G1

VDDL

A7
B2
B8
D2
D8

+1V8

VDD
0
1
2
3
4
5
6 A
7
8
9
10
11
12
13

E7

H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8

A1
E9
L1
H9

7B00
EDE1108AGBG-1J-F
DDR2-A0
DDR2-A1
DDR2-A2
DDR2-A3
DDR2-A4
DDR2-A5
DDR2-A6
DDR2-A7
DDR2-A8
DDR2-A9
DDR2-A10
DDR2-A11
DDR2-A12
DDR2-A13

A9
C1
C3
C7
C9

100n

100n
2B25

100n
2B24

100n
2B23

100n
2B22

100n
2B21

100n
2B20

100n
2B19

47u
2B18

2B42

DDR2-VREF-DDR

2B00 A2
2B01 A3
2B02 A3
2B03 A3
2B04 A3
2B05 A3
2B06 A4
2B07 A4
2B08 A6
2B09 B8
2B10 B8
2B11 B9
2B12 B9
2B13 B9
2B14 B9
2B15 B9
2B16 B10
2B17 A11
2B18 F2
2B19 F3
2B20 F3
2B21 F3
2B22 F3
2B23 F3
2B24 F4
2B25 F4
2B26 F6
2B27 F8
2B28 F8
2B29 F9
2B30 F9
2B31 F9
2B32 F9
2B33 F9
2B34 F10
2B35 F11
2B36 A6
2B37 A11
2B38 F6
2B39 F11
2B40 A2
2B41 B8
2B42 F2
2B43 F8
2B44 C6
2B45 C12
2B46 H6
2B47 H12
3B00-1 C6
3B00-2 B7
3B00-3 B7
3B00-4 C6
3B01 C3

10

11

12

13
5

DDR 4

2009-12-07

8204 000 8953


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2010-Apr-02 back to

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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 113

10-14 B06 820400089572 LVDS Non DVBS


Display Interfacing - VDisp

B06A

Display Interfacing - VDisp

B06A
4

1G03

1G00 C4
1G03 B4
2G43 C4
2G44 C3
3G28 C5
5G01 C3
5G02 C3
6G00 C6
FG0H C5
IG11 C5

T 3.0A 32V

FG0H

1G00 RES
T 3.0A 32V

5G02

+VDISP

100n

30R RES

2G43

5G01
+VDISP-INT

30R RES

22u
RES

2G44

3G28

IG11

2K2

6G00
LTST-C190KGKT

8
2

LVDS Non DVBS

2009-10-22

8204 000 8957


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Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 114

Video Out - LVDS

B06B

Video Out - LVDS


2

B06B
3

10

11

12

13

+3V3

10p

10p

10p

10p

100p

100p

10p

100p

FG34

3G32
100R
3G2W
FG2H
100R
3G2Y
FG2G
100R
3G2Z
RES
FG2K
BACKLIGHT-PWM_BL-VS
3G37 RES
100R
BACKLIGHT-BOOST
100R
BACKLIGHT-PWM-ANA-DISP 3G36
100R RES
FG04
3G30
CTRL-DISP
3G31 RES
100R
CTRL-DISP
CTRL-DISP

RES
10p
RES
10p
RES
10p
RES
10p

RES
10p
RES
10p

2G92
2G93

FG2J

2G94

2G96
RES
10p

RES
10p
2G97

2G98
FG1C

PX3APX3A+
PX3BPX3B+
PX3CPX3C+

FG1D
FG1E
FG1F
FG1G
FG1H
FG11

PX3CLKPX3CLK+

FG1J
FG1K
FG1L
FG1M
FG1N

PX3DPX3D+
PX3EPX3E+

FG12
FG13
FG14

PX4APX4A+
PX4BPX4B+
PX4CPX4C+

41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2G99

FG15
FG16
FG17
FG18

PX4CLKPX4CLK+

FG19
FG1A
FG1B
FG1Q
FG1P

PX4DPX4D+
PX4EPX4E+

60 61
58 59
56 57
54 55
52 53

SDA-DISP
SCL-DISP

FI-RE41S-HF
50
51
48
49
46
47
45
44
42
43

FG30
FG31
FG32
FG33

2G95

FI-RE51S-HF

2G78
RES
2G79
RES
2G7A
RES
2G24
RES
2G25
RES
2G26
RES
2G27
RES

2G76

10K

100p
10p

RES
3G35

10K

RES

RES
2G77
2G75

1
2
3
4

3G33

9G0K-1
9G0K-2
9G0K-3
9G0K-4

8
7
6
5

RES

3G34

RES

10K

RES

+VDISP

FG2M

100R RES

PX1APX1A+
PX1BPX1B+
PX1CPX1C+

FG2R

FG2L

FG2E
FG2F
FG1Y
FG1Z
FG20
FG21
FG22

PX1CLKPX1CLK+

FG23
FG24

PX1DPX1D+
PX1EPX1E+

FG25
FG26
FG27

10p

FG28

PX2APX2A+
PX2BPX2B+
PX2CPX2C+

10p 2G28
2G29

FG29
FG2A
FG2B
FG2C
FG2D
FG1R

PX2CLKPX2CLK+

FG1S
FG1T

PX2DPX2D+
PX2EPX2E+

FG1U
FG1W
FG1V
FG2P

+VDISP

RES 9G0G

FG2N

1G50

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1G51

TO DISPLAY

TO DISPLAY
1X05
EMC HOLE

10

11

12

1G50 G5
1G51 G11
1X05 G1
2G24 C10
2G25 C11
2G26 C11
2G27 C11
2G28 E11
2G29 E11
2G75 C10
2G76 C10
2G77 C10
2G78 C10
2G79 C10
2G7A C10
2G92 C4
2G93 C4
2G94 D4
2G95 D4
2G96 D4
2G97 D4
2G98 D4
2G99 D4
3G2W C8
3G2Y C8
3G2Z D8
3G30 D9
3G31 D8
3G32 C8
3G33 C9
3G34 B9
3G35 C9
3G36 D8
3G37 D9
9G0G G11
9G0K-1 C4
9G0K-2 C4
9G0K-3 C4
9G0K-4 C4
FG04 D8
FG11 E4
FG12 F4
FG13 F4
FG14 F4
FG15 F4
FG16 F4
FG17 F4
FG18 F4
FG19 F4
FG1A F4
FG1B F4

FG1C D4
FG1D D4
FG1E E4
FG1F E4
FG1G E4
FG1H E4
FG1J E4
FG1K E4
FG1L E4
FG1M E4
FG1N E4
FG1P F4
FG1Q F4
FG1R F9
FG1S F9
FG1T F9
FG1U F9
FG1V F9
FG1W F9
FG1Y D9
FG1Z D9
FG20 D9
FG21 D9
FG22 E9
FG23 E9
FG24 E9
FG25 E9
FG26 E9
FG27 E9
FG28 E9
FG29 E9
FG2A E9
FG2B E9
FG2C E9
FG2D F9
FG2E D9
FG2F D9
FG2G C9
FG2H C9
FG2J D5
FG2K D9
FG2L D10
FG2M D10
FG2N G11
FG2P F11
FG2R D11
FG30 D5
FG31 D5
FG32 D5
FG33 D5
FG34 C11

13

LVDS Non DVBS

2009-10-22

8204 000 8957


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100125

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 115

AmbiLight CPLD

B06C
1G35 G2
1G36 G2
1G37 B13

AmbiLight CPLD

2G10 F3
2G11 F3
2G12 F3

B06C
2G19 F9
2GA0 B3
2GA1 B4

2G16 F8
2G17 F8
2G18 F9

2G13 F7
2G14 F8
2G15 F8

3G10-3 E6
3G10-4 E7
3G11-1 E6

2GA5 B3
3G10-1 E6
3G10-2 E7

2GA2 B4
2GA3 B3
2GA4 G3

3G11-2 E3
3G11-4 E4
3G12 E6

3G13 E7
3G14 E4
3G15 E2

3GA1 E6
3GA2-1 G3
3GA2-2 G3

3GA2-3 G3
3GA2-4 G3
3GA5-1 B12

3GA5-2 B12
3GA5-3 B12
3GA5-4 B12

3GA6-1 F13
3GA6-2 F13
3GA6-3 F12

3GA6-4 F12
5GA0 A3
5GA1 B2

6GA0 F12
6GA1 F12
6GA2 F13

10

6GA3 F13
7GA0 D5
7GA1-1 D13

7GA1-2 D13
7GA2-1 E12
7GA2-2 E12

11

FGA1 B4
FGA2 G3
FGA3 G5

9GA0 H5
9GA1 D7
FGA0 A5

12

13

FGA4 G4
FGA5 G5
FGA6 G4

14

IGA0 C11
IGA1 C11
IGA2 C11

IGA3 C11

15

DEBUG ONLY
5GA0

FGA0

+3V3

VINT
100n

100n
2GA2

2GA1

1u0

2GA0

30R

1G37

B
FGA1

100n

1u0

2GA5

30R
2GA3

3GA5-4
3GA5-3
3GA5-2
3GA5-1

GCK3
GTS1
GTS2
GSR

VIO

4
3
2
1

1
2
3
4
5
6

+3V3
5GA1
+3V3

5
6 100R
7 100R
8 100R
100R

SD51022
IGA0
CPLED1
IGA1
CPLED2

IGA2
CPLED3
VINT

VIO

IGA3
GCK2

3
5

+3V3

6
2

15
35

6GA3

LTST-C190KGKT

6GA2

LTST-C190KGKT

6GA1

LTST-C190KGKT

6GA0

LTST-C190KGKT

4
17
25

3GA6-1

7GA2-1
BC847BS(COL)
1
8 330R 1

GSR

GND

7GA2-2
BC847BS(COL)
4

3GA6-2

100R
5
100R

GTS2

7 330R 2

3G13
4
3G10-4

AMBI-PROG_B1
AMBI-BLANK_R1
AMBI-SPI-CS-EXTLAMPSn
AMBI-SPI-CLK-OUT
AMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUT
AMBI-LATCH2_DIS

3GA6-3

10R
1
100R

7
100R

6 330R 3

3G12
8
3G11-1

2
3G10-2

7GA1-1
BC847BS(COL)
1

+3V3

3GA6-4

6
100R
8
100R

5 330R 4

3
3G10-3
1
3G10-1

GTS1

10p

19
20
21
22
23
27
28

TCK
TDI
TDO
TMS

+3V3

7GA1-2
BC847BS(COL)
4

CPLED1
BL-SPI-SDO
BL-SPI-SDI
BL-SPI-CSn
BACKLIGHT-PWM_BL-VS
BL-SPI-CLK

10p
2G19 RES

11
9
24
10

IXO2_29
IXO2_30
IXO2_31
IXO2_32
IXO2_37
IXO2_38

47R

10p
2G18 RES

100R
5
100R

3GA1

10p
2G17 RES

3G14
4
3G11-4

IXO4_19
IXO4_20
IXO4_21
IXO4_22
IXO4_23
IXO4_27
IXO4_28

PNX-SPI-CSBn
BACKLIGHT-PWM

9GA1

10p
2G16 RES

7
100R

10p

10p
2G12 RES

10K

2G10

RES

2
3G11-2

29
30
31
32
37
38

IXO2_36|GTS1
IXO2_34|GTS2
IXO2_33|GSR

5
6
7
8
12
13
14
16
18

10p
2G15 RES

36
34
33

IXO3_5
IXO3_6
IXO3_7
IXO3_8
IXO3_12
IXO3_13
IXO3_14
IXO3_16
IXO3_18

GCK3

+3V3

RES

GTS1
GTS2
GSR
AMBI-SPI-CS-OUTn_R2-R
AMBI-PWM-CLK_B2
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2
AMBI-TEMP
CPLED3
CPLED2

IXO1_2
IXO1_3
IXO1_39
IXO1_40
IXO1_41
IXO1_42

AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R

10p
2G14 RES

2
3
39
40
41
42

3G15

PNX-SPI-CS-AMBIn
PNX-SPI-CS-BLn
PNX-SPI-SDO
PNX-SPI-SDI
PNX-SPI-CLK

10p
2G11 RES

VCCINT VCCIO
IXO1_43|GCK1
IXO1_44|GCK2
IXO1_1|GCK3

2G13

43
44
1

PXCLK54
GCK2
GCK3

26

+3V3
7GA0
XC9572XL-10VQG44C0100

DEBUG ONLY
1G35
1
2
3
4
5
6

1
2
3
4
5
6
7
SD51022

8
2GA4

3GA2-1
3GA2-2
3GA2-3
3GA2-4
FGA2

1
2
3
4

8
7
6
5

100R
100R
100R
100R

FGA6
FGA4
FGA5
FGA3

+3V3

100n RES

1G36

BACKLIGHT-PWM

9GA0

BACKLIGHT-PWM_BL-VS

10

11

12

13

14

15
2

LVDS Non DVBS

2009-10-22

8204 000 8957


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100125

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 116

SPI-Buffer

B06D

SPI-Buffer

B06D

+3V3
+3V3

3EN1
3EN2
G3
18

PNX-SPI-CLK

IGE0

19
2

3GE0-3
47R

3
4
5
6
7
8
9

3GE1-3 6

3GE4

3
47R RES
3GE3
47R

BL-SPI-CLK
1

3GE0-1

8
47R
4 3GE1-4
47R RES

BL-SPI-SDO
AMBI-SPI-CLK-OUT-R
AMBI-SPI-SDO-OUT-R
PNX-SPI-SDI

RES

47R

10

AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDI

PNX-SPI-CSBn

7GE0
74LVC245A
1

17
16
15
14
13
12
11

PNX-SPI-SDO

7GE1
PDTC114EU

10K

3GE2
20

100n

2GE0

2GE0 A2
3GE0-1 B4
3GE0-3 B4
3GE1-3 B4
3GE1-4 B3
3GE2 A4
3GE3 B4
3GE4 B3
7GE0 B3
7GE1 A4
9GE0-1 C3
9GE0-2 C3
9GE0-3 D3
9GE1 C3
9GE2 D3
9GE3 D3
IGE0 B3
IGE1 D2

PNX-SPI-CLK

PNX-SPI-SDO

9GE0-2

9GE0-3

BL-SPI-CLK

9GE2
IGE1

PNX-SPI-CS-BLn

5 9GE0-4

PNX-SPI-SDI

*
**

BL-SPI-CSn

9GE3

PNX-SPI-CS-AMBIn

BL-SPI-SDO

9GE1

BL-SPI-SDI

AMBI-SPI-CS-OUTn_R2-R

Buffer

*
**

Direct

6
2

LVDS Non DVBS

2009-10-22

8204 000 8957


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100125

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 117

10-15 B09 820400089812 Non DVBS Con.


Non DVBS Connector Board

B09A

Non DVBS Connector Board

B09A
3

+3V3

FT74

AMBI-SPI-CS-OUTn_R2
AMBI-LATCH1_G2

V-AMBI
FT75

AMBI-PROG_B1
AMBI-BLANK_R1

FT76

AMBI-LATCH2_DIS
AMBI-SPI-CS-EXTLAMPSn
AMBI-TEMP

FT78

FT77
V-AMBI
FT80
FT79

3T70

2T70

100n

100R

FT81

FC83

FT82

1T86

+24V
T 2.0A 63V

2T76
FT87
LIGHT-SENSOR

IT73
RC

100p

100R

2T77

3T76

100p

100R

2T78

3T77

100p

TO
LED PANEL

FT90
FT91
FT92

+3V3-STANDBY
FT93

2T79
IT75

3T78

100p

100R

2T80

FT94
+5V

100p
KEYBOARD

FT95

1
2
3
4
5
6
7
8

FT89

100R

LED-1

1M20

FT88

IT74

LED-2

3T75

2T81

FT73

3T74

AMBI-PWM-CLK_B2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

FT72

100K

FT71

100n

1M59

FT70

AMBI-SPI-CLK-OUT
AMBI-SPI-SDO-OUT
AMBI-SPI-SDI-OUT_G1

3T79
10R

FH12-25S-0.5SH(55)

100p
2T82

3T84

BL-SPI-SDO

3T80

SCL-BL

FT97

FT98

100R

FAN-CTRL2

+3V3

3T93

3T92

100p

2T83

RES 3T83

100p
2T84

100R
SDA-BL

FT53
FT54
FT55
FT56

1
2
3
4

BL-SPI-SDI

3T88-2

FT57

100R

1735446-4

FT58
FT60

TEMPERATURE
SENSOR

RES

100R

RES

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

1M71

FT96

3T82 100R

FT69

3T88-1
100R

100R
RES 3T81

TACH02

10p

RES

100R
FT68

D
1F53

FT52

2T89

3T91

10p

FAN-CTRL1

TACH01

2T86

RES

10K

10p

100R

2T90

3T90

3T86

BL-SPI-CLK
502382-0470

FT61

3T71

BACKLIGHT-PWM-ANA-DISP

FT64

100R

9T50

+3V3

2T87

* HOTEL TV

3T85
100R

10p

+24V

FT51

SCL-BL

1
2
3
4

10p

100R

1M09

10K
FAN-DRV

E
16

502386-1470

FT99

5T53
+12V

BACKLIGHT-PWM_BL-VS

FT59

IT78

10p

2T91

3T87
100R

30R RES

3T88-4

2T92

1T85

100R

T 1.0A 63V

30R RES

BL-SPI-CSn

1u0

2T85

5T54
+3V3

5T54 F3
9T50 E7
FC83 B4
FT50 C7
FT51 C7
FT52 D8
FT53 D8
FT54 D8
FT55 D8
FT56 E8
FT57 E8
FT58 E8
FT59 F7
FT60 E8
FT61 E8
FT64 E7
FT68 D3
FT69 E3
FT70 A5
FT71 A4
FT72 A5
FT73 A4
FT74 A4
FT75 A5
FT76 B4
FT77 B5
FT78 B4
FT79 B4
FT80 B5
FT81 B5
FT82 B5
FT87 A7
FT88 B9
FT89 B9
FT90 B9
FT91 B9
FT92 B9
FT93 B9
FT94 B9
FT95 C7
FT96 E4
FT97 E4
FT98 E5
FT99 F5
IT73 A7
IT74 B7
IT75 B7
IT78 F4
1X03
REF EMC HOLE

10p

FT50

SDA-BL

2T88

1F53 D9
1M09 C5
1M20 B9
1M59 A5
1M71 E5
1T85 F4
1T86 B4
2T70 B3
2T76 A7
2T77 A7
2T78 B7
2T79 B7
2T80 B7
2T81 B9
2T82 C7
2T83 E4
2T84 E4
2T85 F5
2T86 C7
2T87 D7
2T88 D7
2T89 D7
2T90 E7
2T91 F7
2T92 F7
3T70 B2
3T71 E7
3T74 A6
3T75 A7
3T76 A7
3T77 B7
3T78 B7
3T79 C7
3T80 D4
3T81 E4
3T82 E4
3T83 E4
3T84 C7
3T85 C7
3T86 D7
3T87 F7
3T88-1 D7
3T88-2 E7
3T88-4 F7
3T90 D3
3T91 D4
3T92 E4
3T93 E3
5T53 F3

9
2

Non DVBS
CONNECTOR BOARD

2009-10-22

8204 000 8981


18770_569_100125.eps
100218

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 118

10-16 310431363643 SSB Layout


Overview top side

3B11

2U09

1G37

2G97

2G96

1F24

2G18

3GA1

9GA0

2GA4

7GA1

3S28
3S24
3S29
3S23

2G14

3S43
3S44

1E12

1E22
1E18

1E01

1E19

7F25

5F73

2F88

1P07

3F65

3F64

9F71

1F51

2E20

1FD2

1329

6E15

1F52
3F623F63

2ECN
2F60

6FC7

2ECM

6FC5
3ECM
2E37

6E20

IE10

3FC4

7EC1

BE20

3E20
2E38

3FC3

1FC6

1P04

1P03

1P02

1E09

6FC2
6FC1

3FC5

3FC6
2FC6

2FC1

2FC2

2FC4

9FC5

3FC7
2FC3

9FC6
2FC5

9FC4

9FC3

2E36

2FC7

2ECC

6E19

5EC2

1E37

1E44

9EC3

1P05

6FC3
6FC4

IEE3

6FC6
3FC1

7EE1

6FD3

1E75

1E76

2E21
6E16

3ECN IE42

2EC1

6FD2

3ECG
3ECF

3ECP

3EC5

BE21

2EE2

1FD3

3EC3

2ECP

IEE5

1328

2ECU

IEE6

2EE5

3EE0

2EE4
2EE0

IEE4

3EE1

2EE3

1T01

2F32

9F04

1F25
2F35 3F28 2F34

2F81

2E723E97

1ECB

6EC1

1E38

1E25
1E23

2F29

2F86
3F75

5F72 2F93

9F27
IE11

1E29
6E06

2E39

2E713E96

2E40

2E27

6E40

9E29
3E87
9E52

1E42

1E43

1E08
3E889E04

3E89

9E50
2E67

6E51

1E85

1E39

2E68

6E52

9E57

3E15 3E14

1E86

1E28

1P08

3F26

9F28

1F10

BS13

2S4M

9F01 9F00

9F05 9F06

BS10 BS09

3S84
3S83

9E06 9E09

1E55

2F33

6FC8
2FC8

1FC3 1FC4 1FC2 1FC1

3E21
2E35
IE09

1FC5

1E54
1E53

3F31

3S3W
2S7N
3S4R

3S592S87

2S7U

2S8G

3S4W

3S5L

2S7P

3S4J 2S7J

2S7E

2S7R

2S7L

3S4U

3S4T

3S4G

3S4P

2S7H

2S7M

2S77
2S78

BE22

1E07

1E31

5F70
IF86

3FC2

1E00

2F01

2F91
3F72
IF89

6E43

2EE6

7F70

3S3M

2S2Z
2S2Y
2S7K

3S4K

2S7Q

3S4L

2S30

2S33

2S2W
2S2V

2S32

3S14
2S2S

2S31

3S3U

3S3H

9S06 DBS8

3S00

9S15
9S14

3S6H

3S13

6E38

3E53

2EE1

3EE2

6E46

3E62

2E22

2EE7

2E98

2EB1

3EA2

6E32

5E06

3E18
3E19

2E97
2E99

3EB3
3EB1

7E06

9E02
9E01

3E45
3EB6 2E76
3E48

2EB3

2E742E73

2E81

2E44

7E05 7E04

3EB9

5E80

3EA1

6E37

2E78
3E49
2E41

3E52

2E77

6E31
3E73 2E13

2E75

6E30

7E09 3E61

6E36

3E43

3S6J 3S26

2S41

1E06 1E04 1E03


3E39

IS13

2S34

3S12

7EE0

3S2M

3S3G

3S53

1E70
3E30

2S2R
2S2T

7S08

3E69
3E70
3E66
3E65

3B04

3E40
BE02

2E49

3B24
3B14
3B15

1S02

3S81
3S80
3S52
3S54
3S50

3F36

DS50

3S42

3S3F

BS15

2S4F

2F40

1F75
2F92 2F94
2F90 3F71

3F58

3F59
3F60

2F58

3S1L

3S6K

7F58

3S1E

3S02 3S01 3S04

3S3Q

2S4D

3S2A

3S3R

3S1B

3S1C

3B05

7B03

3E64

7E10

BE03

1E27

6E29

2E24 3E44
6E28

2E12

3E78
9E55
3E79

2E86

6E35

3E86
2E95
2E19

2E96
3E85

2E85

5E76
9E07

9E53
3E77
2E84

2E14
9E05
9E10

9E08

BEC2

BEC5

2E17

2E94
3E83
3E84
2E93
BEC4

BEC1

6E34

2E16

6E24

2E82

6E14

6E02

BEC0

6E22

3E32
3E31
2E18

6E26

2E833E76

IF62
IF61

3S1K

3S3T
3S3N

2B45

2E66

BE01

3E95 3E22

2E58 2E59 2E56 2E57 2E60

BE00

1E24
1E26

5E79

5E78

2E89
3E80
3E82
2E92

5E77

3S62
3S21
3S3S

3S1J

3S27

3E71
9E43
9E42

3E90 9E58
9E54

5E74

3S03

2S4E

2D09
1E52

1E57

1E56

2E33
3E16
3E17

2G98

2G99

3G28

2G28

2G29

2G24

2G27

2G26

2G76

2G7A
2G15

3G13

2G17

3G12

3G15

2G11

3B08
2B46

3B07
3B02

7S00

3B23
3B12
3B13

3S3Y

3B00

2D08

7F20
9S00

CD10

3E98
3E26

IE07

2E79
3E74
9E51
3E75
6E23
2E80
2E15
6E09

3E07

3B25
3B16
3B17

2S4G

1E02

1P00
1P09

IGA1

6F72 3F78

2E62

2E91

2E06
2E04

6E03

6E07

2E88

6E01

2E90

2E87

2E31

6E08

2E30

2E51

2E50

2E70

6E12

6E10

3E25
3E24

3E11

5E73

3E37

1G36

3S3L

IE39

1E49

BEC3

2E01

2B47

3B10

2UU0

3UU3

2U11

7B02

1N00

1E48

2E10

1G35

IU18

1EP2
7E01

6GA2

3GA5

2U15

5U01

7B00

2D10 2D06

1E47

1E46

2E32

2G75

3T81
3T80
3T91

2U16

6E44

3E63

6GA1

7D10

2D05

2E29

7GA0
IGA2

2D07

2D16

5D07

1E45

6GA0

7GA2
IGA0

2B44

IU57

2D20

2T84
3T82
3T92 3T83
2T83

2T85

3T74

7UU1

IUT2

3UU0

7US2

2US3

7US1

2U24

3U71

5D05

3G14

3U29

2U23

7U05

5D04

2G13

3G10

IGA3

6U00

2UD8 2UD9
2UE1

3UD3

5UD3

2U25

2UE4

2U27

5D08

2G16

6GA3

5U00

IU17

3U07

IUD2

2U20

2U28

2UD3

5UD0

3UD1

5U02

5E08 2E63
3E72
2E48
3E35

1D38

1D52

3UD0

2UD7

IUS5

5U03

2UE8

5D02 5D01

1D50

3UD2

2D122D11 2D19

1735

2U49

IUD1

3U06

1M95
2U48

2UE0

IUD0

3UD4

IUD4

2UD1

3UD5

7UD0

7UD1

2UD0

2UD2

1UM0

5UM0

2U51
3U67
2U72
3U84

3US4

3US6

3U26

3U66

2G19

3G11

3B26
3B18
3B19

2U18

3E33

2U52

IU15

2U17

2E55

3U65

IG11

IU23
3U23

3U24

3U64

9UU0 9UU1

2E54

2U53

7UU2

7U01 7U04 7U02

3U56

7B01

7UU3

3UU2

9G0K

2G79

2G25

6G00

2UU1

2U19

3U44

2G78

9US0

7US3

2U43

2G77

1M09

2G10

7UU0

1G50

2T70 3T70

3UU1

IUT1

IUS9

3U43

IUS6

1G51
2G12

3US7

3US5

3US9

2U44

2UE6

3U42

2UE3

2U45

1T86

3US2
3US3

IUS4

2UE2

3U81

IT74

IUS3

2UE9

3U45

2UD4

2U46

2UD6

5UD2

1M99

2U41

5UM1

2UD5

2U42

5UD1 6UD0

IT75

1T85

5T54

3T90
3T93

1M59

1F53

1M71
5T53

2T81
3T79
2T82
3T78
2T80
2T79
3T77
2T78
3T76
2T77
2T76
3T75

1M20

1E05

3104 313 6364.3


18770_580_100216.eps
100219

2010-Apr-02 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.1A LA

10.

EN 119

Overview bottom side

FG1V

FG1U

FG1R

FG2D

FG2B

FG29

FG27

FG25

FG1W

3T88

FT81

3T87

FT92

FT93

FT94

FT95

FT89

5FE0

5FE7

2FH7

2T87

ID33

5UA0

2U54

FU58

2U47

6U40

2U50
FU65
FU63

ID11

FD07

FU67

ID13

2D02

ID27

FU62

3U76

FU68

2B09
ID39

3D15
FU66

3D04
ID31

7D13

ID35

2D03

7D11

ID34

FE30

2B36
2B08

2B04

3S51

IE63

2B41

3E51

2D14

FD06

ID09

3D10

3S72

IS03

IS07

2B01

6E47

2D21
2B02
2B03

FD05

2D13

FE34

2D01

3D01

C001

6E48
FE28

2D27

ID05

ID07

IS12

2B06
FE27

FS03

2B07

3B03

ID10

3E67

2B00
IE06

FE31

FD02

FE32
FE29

3S38

FE33

2E52
2E53

2D22

3E34

6E50

IS1D

IE32

FS57

ID06

IE38

3D14

IE64

3E68

2S3A

2S3C

3U68

FU50

3U13

3U59

3U53

3U74

1U40

ID19

ID38

ID32

3S0Z

3U75

3U41
IU44

6UD1
IU52

FD14

3D06

3D09

ID29

ID28

ID30

ID14

2D17

3D02

ID37

FU61

FU64

ID18
2D24

2D28

FD01

FU72
2D23

7D15

7U40

7D03

ID15

2D29

FD03

FU59

IU51

6D01

3B22

IU48
3U80

FU01

2B12

3U62

FU73

3U60

3U61

IU61

2U55
IU49

IS1N

2S2H

3U73

3U72

7U41

3B27

3S39

2UB6

3UA5

2UA4

IU22

IU62

5D03

2S3F

2UB5

FUA1

2UA6

FUA0

2UA5
3U01

7U48

2U02

3U21

2U29

IU41

IE26

3S36

7UA6

IUS0
3UA1
3UA4

7U00

3U22

2U03

3U10
3U19

2U07

3U17

IU63
IU50
2U71

3U83

3U14

2U68

IU06

3U82

IU14

3UA2

3UA3

7UA1
3UA8
2U21

2U01
3U09

2U05

7U03

3U03

2U04
IU01
3U20

2U122U13

2U10

2U14

IU27

IU28

IU13

2B13

3B01

FU60

FUD3

IU40

2B11

2S4Q

IU64

3U00
IUD6

2B10

2B15

2B16

2S29

2S68

2S4R

FU57

7UD3

IU03

FU00

2B37
2B17 2B14

FU56

FU74

IU20

IU07

3U05

IU55

IUD3

2UE7

2U06

CU00

IUB0

2UA3

2B38

2B19

3U18

2B24

2B26

2B25
2S4P

3B21
3B20
2B20

2U08

3UB3

IUU2
3UB0

2UA9

2UA8

3UA9

2UB0

3UB1

5GA1

2GA5
2GE0

5GA0
2GA0

IUA5

7UA3

3UB5

2B29

2B28

2GA3

7GE0
3S07
3S06

2S25

2S63

IU04

2S3E

2S3H

IS1B

2S3B

2S8A
IS02

2S2G

IS0R

7UA5

3U27

FU05

FU54

IUB3

3U08

IU08

FU06

FU53

FU55

IUB1

IU24

IU12

IS1S

9S17

3S3P

3S5E

IU25

3U02

7UA2

IU05

IU16

3UB6

IUB5

IUD7

2UB7

IS50

7S05

C000
FS53

2U00

3U28

IU56

3UB7

ID36

IS19

2S3J

3S16 3S17
IS0V

IU10

FU51

FU52

IUB2

2UB8

IUS7

2S36

IS3E

IS11

2B18

IU21

3S6Q

3S30
3S33

2S4S
2S45
2S3G

IS1A

3S6L
3S37
3S34
3S32
2S2J

2S2K

3S05
2S22

3S47

FS02

IS06

IS20
FS44

IF16

3U11
FU02
IU02

3B06

IUB4

3U25

FU07

IUA1

3UA7

3U04

7U06
IU30

IUA4
3UA0

FU48

IU26

3U12
IUB6

FUD2
IUS8

7UA0

7U43

7U42

2UA7

IUA7

2UA1

IUA2

IUA9

2B40

3S22
2S24
2S20

IS4V

IS5C

2UA2

FU04

FS08

3S5B

9S24

IS3F

IUA3

IU11

2B42

IS42

2S38
2S39

2S16

IS5G

FS49

3UB4

2UB3

IU09

2B21

FS01

3S20

2S65

2S40
3S08

IS5J

2UB4

3UA6

3S0V

2S6E

2S23

5S90

2S19

IS2Z

7UA4

IUA6

9U41

IU29

3U15

3U16

2U22

IS4W

2S2L 3S09

2S18

3S75

2S14

3S5V

IS5H

3S46

3S5T

2S3K

2S76
2S75

IUA8

2UA0

2B22

2B23

2B05

3FE6

3S25

3S6M

3F82
2F65

5F74

2F76
2F77
2F82 2F72
2F80 2F73

2S3M

2S3L
IS1L

3F79

FU03

FUA2

IU43

IE33

ID08

2D26

6E49

2FE4
DFE8

DFE7

BFE2
DFE6

BFE1

2FG8
2FG6

IF17

2FG4

IE50

DFE9

2FG7

IF18
DFF2

IE49

2FE8

5FA3

2FF4

3FE9

2FE3

DFF1
2FA3

FE56

2FA4

IF69

5FA4

2FF1

2FF9

FF61

2FG1

2FH4

2FH3

FE58

FFAF

5FE9

2FF8
IF68

FF63

2FH2

7FE3

FF62

3FE8

IF67

FF03

5FE8

5FE5

FF81

2FG0

IF49

2FF7
2FF2

2F84 3F76

IS44

3S18

9U42

IU45

IUM0

3UB2

IU19

IF29

7FE0

BFE5

BFE4

BFE3

2FE6

IS1E

FGA0

FS52

2FH5

5FE3

2FH6

3FG2

IS1G

3S19

3S2L

3S1H

3FG7

FF82

2FG9

IS1K

IS5D

3S1G

3S2S

2FF5
2FF0

2FE0

IF65

2F62
2F70

2S3Q

FS10

FS11

3S49

2FG3

FF64

IF63

IF48
IF88

7S09

IS5E
3S5S

3S76

3S10

IS3B

2UE5

FUA4

CUA0

2UB1

3S6P

2S6D

2S3D

2S13

9S0D

2S10

FS45

IS3D

7UC0 7UD2

FUU0

IUU6
2UB2

2S26

2S46

3FG6

5FE4
FF00

FEE0

2FDD
2FDC

FFDB

FE54

IE29

IE73

FECW

FFC8

FE67
IE48

IE70

IEC6

IEC5

FE60

IE91

IE16

2EA5

FE74
FE84

IE92

IE96

FE82

FE81

IE14

IE08

FE80

2EA4

IEC0

IE54

IE51

IE18

FE59

FEA0

FE75

FE73

IE23

IE22

FE71

FE72

IEC1

FE70

FEC2

FEC4
FEC5

FEC1

3ECA
FECF

FE62

FE41
FECJ

FECE

FE61

3ECE

7EC0 7E02 3E23


3ECD

9EC0

IE20

IE68

IE17

IE89

FE83
FE35
IEC7

IE21

IE53

IE90

3ECU

FFC6

FECM

FE68

IE67

IE13

FE85
IEE8

IE65

IE66

IEC4

2EC0

2EC6
FEC0

FE63

5EC0

FECA

FFC1

IE05

FE55
IE55

IEE7

2ECV

9FC1

2EC8

IE60

IE61

IEE0
IEE2

FFC4
FFC7

FFC2

FE64

FEC8

9EC2

IE15

FE36
FFC3
FFC5

FE66
IE57

IE56

IE12

FFB2
FFB3

FE79

FE76

IE52

IE62

FE77

IE77

IE93

IE76

FE51

IE71

FEA1

FE49

3EA7

FE43

IEC2

IE31

IE94

FE50

FE78

FE48

5EC3

3ECK

FE57

FE42

IE45
FEC3

FECR

3ECJ

IE43

FECY

2EC7

FE45

IE72

2EC3
3ECL

FE46

2EC2

FE44

2ECW

FE02

3ECH

7FA3

FE01

FEC7

IE59

FFC9

FECB

IEE1

3FBF

FF74

IE75

IE74

IE44

2ECQ

2FA2

FF76

FFA2

2F59

2F61

FECZ

FFB6

9FC2

FT91

IUD5

IUU0

2GA1

2S6G

BS17

FS50

2S85
2S86
2S84

FGA1

2S17

5S93 2S602S64

2S5J
2S4Z

2S15

IS3L

IS5F

IS4Z

3B09

3B28

2S6N

2S51

3S1D

IF66

AF73

1FE0

2FF6

5F71

3FG4

IF64

IF32

IF33

FFB4

IT73

FT90

FU49

FUA3

2SHW

5S84

3S55

7S20

2S4K
IS2U

9S0E

3S2V

2S4U
DS52

3S40

3S41
3S1P

AF72

IF80

IF82

5S95

2S50

IS05

3S2K

3S1F

IF59

2S5P

5S88
2S6C

2S5G
2S5K

2S53

2S6A

2S6B

2S21

5S83

2S52

2S6M

2S59
2S5B

IS10

2S4Y

2S43

2S6K

2S6H

2S2E

3S0W

FS64

3S64

2S27

5S94

2S4W

5S87

2S6P

2S5H

2S6F

5S92

5S80

2S55 2S58 2S5A


2S11 2S56 2S28
2S37 5S04
5S81 5S89

2S6L

2S57

IS3Q

2S4V

IS3S

2S5C

5S82

2S5D

3S1T

3S1S

3S1U

3S1R

FF29

3S45

3F51
FF57

2S67

3S15

3S66

9S10

3S68
IS2V

3S6C
3S6V

3S6A

3S2G

3S2F

5S85

2S62

IS3K

2S5M

2S4T

IF27

5FG0

5FG2

AF70

2F28

3S56

IS01

5F76

3FE5

2FE5

IF28

3F77

2FF3

2F66

5F66

3F35

2F30

2F79

3F80
3F81

IF14

IF42

FFDC

IS25

IF54

3S11

IF74

IF78

2F63
2F64

2FG2

IF44

3S57

IS04

IF76

2F75

IF12

IF15

2FH8

FF65

3S5Y

3S82

IF73

3FE7

9F03
9F02

IF13
IF40

FF66

3S58

IS58

2F71

FF01
IF10

IF11
AF71

2F78
2F74

IF77

7F75

2F27
2F26
IF43

FF34

FT87

3U69

IUU5

2S12

IF50

3F06
FF04

7F52

FF45

FF71

IF34

3S673S65 FS2W 9S11

3F52

2F52

3F25
3F32

FF75

IF39

FF35

IS26

FS51

2F85

3F30
2F25

FT88

IU47

2B27

3GE2

2S66
2S61

3S6F

3S5W

FS0Z

IF37

IF41

3S61
3S60

3S5Z

FS31

FF56

3F42

IF81

IF31

IT78

FT99

FT69

IUU3

2S4N

3S69

IF75

9F21

9S08
3S6G

3S6W

2F21

IF58

IF90

9F20

9GE2

9GA1

3F07
3F44 3F43

FS2Y
FF55

3S2H

9F25
FF36 9F26

7S01

2S89
IS40

FF44

IF52

IF30

IS00

3S6E

3S6D

FF33

FF37

IS09

9S12

IF87

3F21

IF79

2F31

9S13

IS08

IF72

IF36

FT97

FUM0

3GE4

3GE3

3F24
3F23

9GE1

3F20

IF45

IF35

IGE1

9GE3

IF51

IF53

3F12

FF50

3F40

3F34

9GE0

IGE0

2F20 3F22

FF32

FF40

FGA4

FF58

IF22

3F67

IF21

IF46

3F41

FT98

2B32 2B39

IUU4

FGA3

2F03

3F05

FT96

2B31
2B35 2B34

3GE0

FGA5

3GA2

3F45

IF07

3FDG

3GE1

FGA6

3F66

3F53

7F53

IF55

FF41

FF43

FC83

3U70

FF31

3S6B

FF47

FT78

FB00

FF48

FF42

FT77

5G01

3F03

FF49

FT74

FT70

FG34

FT68

7GE1

9CH0

FF39

FF30

3F54

IF03

3F02

3F01

FF46

FG2K

FG2E

2B43

IF23

7F02

IF06

2F02

7F01

3F10

IF47

FFB1

FG2F

FG1Y

5G02

3GA6

IF56

7F54

3F69
2F53

7F00

IF02

IF01

FFDA

FG20

FG22

FG2M

3F19

2F05
2F00

3F11

7F05

2F06

3F68

FF38

IF08

FFB5

FG23

FG24

2GA2

IF57

3F04

FG26

FT61

9T50

IUU1

IF04

IF05

FG28

FG2A

FT60

FT59
FT82

2B30

3F08

3F09

FG2C

2T902T91 2T92

FT58

7UA7

FGA2

FG1S

2S42

IFD3

1G03

7F03

2FD1

2G44

2F04

7F04

IFD1

3FD6

3FD4

3FD3

IFD2

9FD1

6FD1
3FD1

9FD5

3FD2

3FD7

IFD5

9FD2

7FD1

IFD4

FG1T

2B33

FG1D

FG1E

FT57

3G35

FG1G

FG1H

3G33

FG1J

FG1K

3G34

FG1M

FG13

1G00

FG15

FG17

2T89

FT56

FT64
FT73

FG18

FT55

FG0H

FG30

FG1P
FG1B

3T86
2T88

3G37

FG2R

3G2W

3G31

3G32

3G2Y

3G30

FG21

FT53

ID12

2G43

FT52

3D16

FG1C

FT80

3U63

FG1F

FT75

3T71

FG11

FG2H

FT79

FG1L

FG2G

FT76

FG12

FG1Z

FT72

FG16

FT54
FT71

9G0G
FG2L

FG1A

2G93

FG1Q

FG31

2G94

2G92

FG1N

2G95

FG14

FG2P

FG2N

FG32

3T85

FT50

FT51
3G36

FG33

FG19

2T86
3T84

3G2Z

FG04
FG2J

FEC6

FECD

3EC1

FE03
FECK
FECL

FECP

FECC

FECG

FECN

3104 313 6364.3


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Styling Sheets

Q552.1A LA

11.

EN 120

11. Styling Sheets


11-1 Matisse 32" - 46"

MATISSE 32"- 46"

0010

0021

0024

0010

0029
0018
Pos Nbr

0004
0260

Description

0004

Front Cabinet

0010

Rear Cover (with left & right diffuser)

0018

Leading edge cover

0021

I/O bracket side

0024

I/O bracket bottom

Remarks

0029

Switch bracket

0162

Mid High Speaker Interface bracket 32"

Not displayed. For screen size 32" only

0189

Front Cabinet Locking Bracket 40"

Not displayed. For screen size 40" only

0260

Stand

1085

Remote Control

1114

Keyboard assy

5213

Loudspeaker assy (left & right)

Not displayed

FOR ELECTRICAL PARTS SEE WIRING DIAGRAM CHAPTER 9


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