Chapter 3

AMBA Specification
In this chapter, we introduce an on-chip communication standard, called
Advanced Microcontroller Bus Architecture (AMBA) [15] . AMBA specification
defines three distinct bus architectures. Advanced high-performance bus (AHB) and
advanced-system bus (ASB) are both for high clock frequency module. But ASB is
hardly used in peripheral module in popular SOC system recently. The last bus
architecture is advanced peripheral bus (APB), which is mainly used for low-power
peripheral modules. Section 2.1 talks about the usage and functionalities of three
distinct bus architectures. The signal declaration and all kinds of transfer type are
discussed in section 2.2. The last section of this chapter shows the architecture of
AHB component, including master wrapper, slave wrapper and direct-memoryaccess (DMA) controller.

3.1 Introduction of AMBA

Well compare the three distinct bus architectures defined in AMBA
specification in aspect of usage and functionality.
The AHB is used as the backbone bus for high-performance system and
supports connection between embedded processor, on-chip and off-chip memory
interface or bridges to low-performance system where most of the peripheral
devices located. AHB is more complex and has more transfer functionalities than
ASB, which is the alternative choice for system bus. APB is optimized for minimal
power consumption and reduces complexity to peripheral devices integration. APB
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is usually used for interfacing peripheral devices with low bandwidth and do not
require high performance like pipeline architecture.
Table 1 shows the features that each bus architecture support. We choose AHB
as our system bus. All the IP integrated in this system must be AHB-compliant.
AHB data transfer will be detailed in next section.

AHB

ASB

APB

High performance

High performance

Low power

Pipelined operation

Pipelined operation

Latched address and control

Multiple bus masters

Multiple bus masters

Simple interface

Burst transfers

Burst transfer

Suitable for many peripherals

Split transactions
Wider data bus configuration
(64 and 128 bit)
Table 1. AMBA Features

Figure 5 illustrates a typical AMBA system. Several master or slave devices

are connected via AHB or ASB which are often used as system bus. The highperformance ARM processor which acts as system controller is the typical master
device in this system. The processor can load instructions from program memory
and execute them. The data transfer between each memory module and peripheral
devices also can be done by it. The processor can send control data via the method
to control the devices implemented in high-performance system like DMA bus
master.

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High-performance
ARM Processor

High-bandwidth
On-chip RAM
Uart

Expansion Memory
Interface

AHB or ASB

Bridge
AHB to APB Bridge
or
ASB to APB Bridge

DMA

Timer

APB

KeyPad

PIO

Figure 5. AMBA system

The bridge locates between system bus and peripheral bus. While transferring
data from processor to peripheral devices like UART, timer, peripheral I/O and
keyboard, the bridge convert the transferred signals from one type to another for
satisfying different performance and protocol.

3.2 AMBA AHB

The AMBA AHB bus protocol is designed to be used with a central
multiplexer interconnection scheme. All the master devices drive out the address
and control signals indicating the transfer they with to perform. The arbiter
determines which master devices has its address and control signals sending to all of
slave devices. A central decoder is required to control the read data and response
signal multiplexer, which selects appropriate signal from the slave involved in the
transfer. The slave devices passively wait for address and control signals from one
of the master devices. When the slave device is selected, it has to provide the
response signals indicating the transfer status to central decoder.

Figure 6 illustrates the structure required to be implemented in AHB system

with two master and three slave devices.
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Arbiter

HADDR
HWDATA
HADDR
HWDATA

Master #1

HRDATA

Address and
Control Mux

HRDATA

Slave #1

HADDR
HWDATA

HADDR

Master #2

HRDATA

HWDATA

Write Data Mux

HRDATA

Read Data Mux

Slave #2

HADDR
HWDATA
HRDATA

Slave #3

Decoder

Figure 6. AMBA AHB Structure

3.2.1 AMBA AHB Signal List

In order to design the wrapper, we must figure out the signal declarations for
AHB. Table 2 describes the signal declarations used in common AHB system.

3.2.2 AHB Transfer Type

The AHB transfer types consist of basic transfer and burst transfer.
Figure 7 shows the basic transfer on AHB. One data transfer can be separated
into two phases, one is address and the other is data. The master devices drive out
control and address signal at address phase. Data and appropriate response driven by
selected slave device are transferred at data phase. Address phase lasts only one
clock cycle, but data phase may require several clock cycles.

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Name

Width

Source

Destination

Description

HCLK

Global

All devices

System clock signal

HRESETn

Global

All devices

Negative reset signal

HBUSREQx

Masters

Arbiter

Master bus request signal

AHB supports at most 16 masters on a bus. There are at most 16 bus request lines in the system.
Arbiter will sample these requests to determine which master would be granted.
HLOCKx

Masters

Arbiter

Master transfer lock signal

There are 16 signal lines came from 16 masters in AHB. If the signal is high, it means that this
transfer should lock bus until transfer complete.
HADDR

32

Masters

Slaves and Arbiter

Address signal from one of

masters.

HTRANS

Master

Slave

Transfer type signal

AHB master transfer type, which can be IDLE, BUSY, NONSEQ or SEQ. This signal comes from
the granted master.
HBURST

Master

Slave

Burst type signal

This signal comes from the granted master. It indicates the type of burst transfer like SINGLE,
INCR, and WRAP.
HRESP

Slave

Master

Slave response signal

This signal which comes from the selected slave can be OKAY, ERROR, RETRY or SPLIT.
HREADY

Slave

Master

Slave response signal

This signal comes from the selected slave. When HREADY is equal to HIGH, it indicates that the
transfer has finished on the bus. Otherwise, it means the transfer should be extended or the
ERROR, RETRY and SPLIT may happen.
HGRANTx

Arbiter

Master

Master bus granted signal

These signals would connect to each relative master. When one of the HGRANT signal is HIGH, it
means that one of master has the bus ownership and the master can perform the transfer operation.
HMASTER

Arbiter

Split-capable slave

Master bus granted signal

This signal would show which master is granted on the bus. When a slave starts to do SPLIT
transaction, the slave needs to record the split master by storing this signal.
HMASTLOCK

Arbiter

Split-capable slave

Master bus granted signal

This signal shows that which master is granted for doing lock transfer. If the transaction are lock
transfer, the slave could not do SPLIT transaction.
HSELx

Decoder

Slaves

Slave selected signal

This signal would connect to each slave. When this signal to one slave is HIGH, it means that the
slave has been selected.
Table 2. AHB Signal List
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Address phase

Data phase

HCLK

HADDR[31:0

Control

Control

Data A

HWDATA[31:0

HREADY

Data A

HRDATA[31:0]

Figure 7. Basic Transfer

Slave device can insert wait cycles into transfer to have more time for
preparing valid data. When performing read operation, the slave device de-asserts
the HREADY signal until the read data is valid. When performing write operation,
the master device holds write data until the slave device asserts HREADY signal.
Figure 8 illustrates the waveform of basic transfer with wait cycle.
Address phase

Wait cycle

Data phase

HCLK

HADDR[31:0

Control

Control A

Data A

HWDATA[31:0

HREADY

Data A

HRDATA[31:0]

Figure 8. Basic Transfer with wait cycle

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AHB can support pipeline operation. The data phase of first transfer and the
address phase of second transfer can overlap to get better performance. The
waveform is illustrated in Figure 9. Transfer A and transfer C have no wait cycles,
but transfer B has one. The wait cycle extends the data phase of transfer B and the
master device holds the control signals of transfer C one more clock cycle.

HCLK
HADDR[31:0

Control

HWDATA[31:0

Control A

Control B

Control C

Data B

Data A

Data C

HREADY
HRDATA[31:0]

Data A

Data B

Data C

Figure 9. Pipelined Transfer

Burst transfer is sequential transfer. Before we talk about the burst transfer, we
must detail the transfer type encoding signal, HTRANS first. There are four
different types of HTRANS includes IDLE, BUSY, NONSEQ (non-sequential), and
SEQ (sequential).
IDLE indicates that no data transfer is required. In this state, its not going to
perform any data transfer. BUSY allows the master device inserting idle cycles
during burst transfer. This transfer type indicates that the master device wants to
continue the burst transfer, but the next transfer cant take place immediately. The
address and control signals be held during BUSY transfer type.

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NONSEQ indicates the first transfer of burst transfer or just a single transfer.
The address and control signals in this transfer type are not related to the previous
transfer. The followed transfer type in burst transfer is SEQ and the address and
control signals are related to the previous transfer. For incremental burst, the
followed address is equal to the address of the previous transfer plus the size of
transfer in byte. For wrapping burst, the address of the transfer wraps at the address
boundary equal to the size in bytes multiplied by the number of beats in the transfer.
Burst transfer must not exceed a 1KByte address boundary. Therefore it is
important that master device does not attempt to perform incremental or wrapping
burst transfer which crosses the address boundary. An incremental burst transfer can
be any length, but under the 1KByte address boundary constraint. Figure 10 shows
the waveform of burst transfer.

HCLK
HTRANS[1:0]

NONSEQ

BUSY

SEQ

SEQ

SEQ

HADDR[31:0]

0x20

0x24

0x24

0x28

0x2C

INCR

HBURST[2:0]

HWDATA[31:0

Data
0x20

Data
0x24

Data A

Data
0x24

Data
0x28

Data
0x2C

HREADY
HRDATA[31:0]

Data
0x2C

Data
0x2C

Figure 10. Burst Transfer

3.3 AHB Device Implementation

We only implement AHB master device, slave device and DMA controller
because of the arbiter and decoder has been in our platform. In this section, we
introduce the I/O interface and finite state machine of each device.

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3.3.1 AHB Slave Interface and FSM

After the master device has started the transfer, the slave device then
determines how the transfer should progress. The slave device receives HSEL signal
which comes from decoder to recognize it is chosen or not. Whenever a slave device
is chosen, it must provide the response which indicates the status of the transfer like
complete or error.
Figure 11 displays the I/O for an AHB slave device. If the slave device
supports SPLIT transfer, it must have additional ports include HMASTER,
HMASLOCK, and HSPLIT. We do not mention about this issue in this thesis.
CLOCK
HCLK

Select

RESET
HRESETn

HSELx

HADDR
Address HWRITE

HREADY
AHB

and HTRANS

HRESP

Slave
Device

Control HSIZE

Transfer
Response

HBURST
Data

HWDATA

HRDATA

HMASTER
HMASTLOCK

Split-capable
Slave

Data

HSPLITx

Figure 11. AHB Slave I/O

Lets consider the finite state machine of AHB slave device. It starts from idle
state. If the device is chosen, the state can move to address state then data state. The
two states map to the address phase and data phase of the transfer on AHB. We can
also define the error condition that leads the state to error state. In error state, the
response signal will be set to ERROR, RETRY, or SPLIT. Retry and split state
handle these two different conditions. Figure 12 illustrates the FSM of AHB slave
device. Wait state is to handle the wait cycle insertion.
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IDLE

ADDRESS

DATA

WAIT

SPLIT

RETRY

ERROR

Figure 12. AHB Slave FSM

3.3.2 AHB Master Interface and FSM

AHB master device has the most complex bus interface in AMBA system and
can perform data transfer. When performing transfer, the master device provides the
address and control signals and monitors the transfer response from slave device.
Only one master device gets bus ownership on AHB. Figure 13 displays the I/O for
an AHB master device.

CLOCK
HCLK

RESET
HRESETn

Arbiter HGRANT

HBUSREQ
HLOCKx

Transfer

HREADY

Response HRESP

Data

HRDATA

HTRANS
AHB
Master
Device

HADDR
HWRITE
HPRONT
HSIZE
HBURST

HWDATA

Figure 13. AHB Master I/O

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Arbiter
Transfer type
Address
and
Control

Data

The FSM of AHB master device also starts from the IDLE state. When the
master device attempts to perform data transfer, BUSREQ is asserted to arbiter for
bus ownership. After granting the bus, the master device can perform single or burst
transfer. The behavior maps to the NONSEQ and SEQ states. The device can also
insert wait cycles during transfer. It map to BUSY state. WAIT state reflects the
wait cycles inserted by slave device. Figure 14 illustrates the FSM of AHB master
device.

BUSY

IDLE

BUSREQ

NONSEQ

ERROR

SEQ

WAIT

Figure 14. AHB Master FSM

3.3.3 AHB DMA and FSM

DMA (Direct Memory Access) controller can transfer a mount of data between
every memory modules and peripherals. The processor doesnt have to waste clock
cycles to handle data transfer if there is a DMA controller in the system. In this
section, we introduce the control method and architecture of typical DMA controller
with AHB interface.
The DMA controller consist both AHB master and slave interface. The slave
interface receives the control information like source address, destination address or
the number of beats from processor. The master interface uses the information to

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perform data transfer from source address to destination address. The mechanism is
memory-mapped I/O. Table 3 lists the memory-mapped register description. Figure
15 shows the architecture of DMA controller.

Address offset

Name

Type Width

Description

0x00 [0]

DMA_Enable

r/w

If the DMA enable signal is

asserted, the DMA controller is
ready to be used.

0x00 [10:1]

DMA_Beat_Count

r/w

10

The number of beat count in

transfer. 1023 at most.

0x04

DMA_Source

r/w

32

DMA source address register

0x08

DMA_Destination

r/w

32

DMA destination address register

0x0C

DMA_Interrupt_Mask

r/w

When DMA complete transfer, the

interrupt signal is assert. Software
driver should close the interrupt and
run the sub-routine

Table 3. Register Description for DMA Controller

This is the DMA operation flow:

1. If the processor wants to use DMA controller, it has to check the
DMA_Enable register through AHB slave interface. If the signal is de-assert,
it means the DMA controller is working. Otherwise the device is ready to
use.
2. If the module is ready to use, processor transfer configuration data like
number of beat count, source and destination address to the registers of
DMA controller. The content of DMA_Enable must be de-asserted.

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3. The DMA controller starts to transfer data from source to destination address.
The performance is related to the number of buffer in controller.
4. If the transfer is complete, the DMA controller asserts the interrupt signal to
interrupt controller. Processor uses the DMA_Interrupt_Mask register to
disable the interrupt signal and then run interrupt subroutine.

Address and control

Slave

Response

Register

Interface

Read and write data

File

Read and write data

FIFO Buffer

Master
Interface

Address and control

Response

Central Controller
of DMA

Figure 15. Architecture of DMA Controller

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