University of San Carlos

Department of Electrical and Electronics Engineering

Name: Neil John Perez
Date Submitted: February
4, 2015
Subject&Schedule:EE426NL/1:30-4:30/W
Remarks:
Experiment #7
Shift Register Applications
I. Answers to Questions
1. Enumerate some other applications of shift register. Give at least two
applications and briefly explain their operation.
Keyboard Encoder
Earlier a simple keypad encoder circuit was discussed where, the
0 to 9
digit
keypad was connected
through a decade to BCD
encoder.
Pressing
any
keypad
key

enables
the

corresponding
input
of the encoder circuit
which encodes the
input as
a 4-bit BCD output.
Computer keyboards
which have more
keys employ a
keyboard encoder circuit that regularly scans the keyboard to check
for any key press. Figure 35.3. The scanning is done by organizing the
keys in the form of rows and columns. With the help of a shift register
based ring counter one row is selected at a time. The two counters
are connected as an 8-bit Ring counter which sequences through a

bit pattern having all 1's and a single 0. The 8 state sequence selects
one row at a time by setting it to logic 0. If a key is pressed, the
corresponding column also becomes logic 0 as it connected to the
selected row. The row and column which are selected are encoded by
the row and column encoders. When a key is pressed, the selected
column which is set to logic 0 sets the output of the NAND gate to
logic 1 which triggers two One Shots. The first One Shot inhibits the
clock signal to the ring counters for a short interval until the Key
Code is stored. The One Shot also triggers the second One- Shot that
sends a pulse to the clock input of the Key Code register. The Key
Code Register stores the key ID represented as 3-bit column and 3-bit
row code.

Serial-to-Parallel Converter

A
Serial to
Parallel converter circuit based on shift registers is shown. Figure
35.2. Theserial data is preceded by a logic low start bit which triggers
the J-K flip-flop. The output of theflip-flop is set to logic high which
enables the clock generator. The clock pulses generated
areconnected to the clock input of a Serial In/Parallel Out shift
register and also to the clock inputof an 8-bit counter. On each clock
transition, the Serial In/Parallel Out shift register shifts inone bit data.
When the 8-bit counter reaches its terminal count 111, the terminal
count output signal along with the clock signal trigger the One-Shot
and also allow the Parallel In/Parallel Out register to latch in the
Parallel data at the output of the Serial In/Parallel Out shift register.
The One-shot resets the J-K flip-flop output Q to logic 0 disabling the
clock generator and also clears the 8-bit counter to count 000.
2. Design an 8-bit sequential shift-register memory.