o~ ~ ~ ~ ~ ~ Te Complexity of Design is Growing Rapidly

f 11 l- =

AAlgorithmic Architectures

Verification of Complex
Analog Integrated Circuits

I_

A aarchitectures|

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~~Adaptive filtering

Etc.

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>10k transistors
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Operating modes
~~~~~~~~~*

Power manlagement modes

~~~~~~~~*

Ra_:

* Modes for specific customners

~~~~~~~~~~~* Test modesI
* Calibration

4DAC f fPA

_I I_i~~~~~~~~~~- These dlays, every resistor, capacitor,la0:

=i
and current source is adjustableI

> 250 settings

Numbers given are representative of what would be common for this type of circuit. 4
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l~ ~ ~ Crplogic

Functional Errors

Functional Errors

* Functional errors are often very simple errors

- Corrupt logicW

[2]

c[1 ]

5[0]

Functional errors are often very simple errors

..- . .

: ~~~~~~~~~~~~-

Flipped busses

7~~~~~~~~~~~~~~~~~~~~~~~~ 8

Functiona Eror

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Alternatives to Verification

What's Needed
* Systematic approachb to verifying design &
specification
~* Confidence that all flaws have been found
* Mlore ve=rificatio3n, earlier in design flow

Avoidl functional errors by

* LJimiting design choices, simplify circuits
- Often notpractical
- Creates new risks

* Extensive use of conventions

- epul u otsficet-Errors afre easier to fix & less disruptive

Hel
pefrac.vrfcto
* Exporting all control lines, fix bugs in firmware
0
e witlhDromnevrfcto
- Issues
* Accurate model of MS section
* Too many wires
14

* Too muc dependence of digital design group

,
* Hfarder to brivng up and test design
* Not suitable for all issues (ex. chicken & egg problem) 15

#(2*clnockPeriod);.

checkSupplyCurrent(); C ilout-= $dist_uniform(seed, -IM, IM)/2M

- Automated pass/fail tests (self-checking tests)

Model-based
verification
- Dramatically accelerates te simulation

- Moves it earlier in design cycle

11in-=out/IinGain;
C
~~~~~~~pup
= 1;
~~~~~~~~~~~~~~~~~~~~~~~(0*lckeiModLlae #svetlltlingT#(0-5flflPrime);
1rd
chcSplCret;
measGain
.
V(ot
fin
T~~~~~~~~~~~~~~~~~or (i - 0; < 654; i=i+1) begin
$diusplay("Gain IS %R",notmeasGain);

checkRtXgain();

Rersso

i,t19,f,g

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ht}.

R,e

-ltly1tLLLo11D VlbF

=measGain;
~~~~~~~~~~prevGain

|C~p~UoOzaiZt@'7D))

[.ge}

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Cu)

endtask.

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Sef-hckn Tes bec

Tetn

* ToXday, most designers test functionality at

most once, when first designed
- Redesign can blreak existing functionality
* In regression testing, we test all|
functionality every time tests are run
-Getlyredcsrsks with redsig

19

sd

~~~~~~~~~~~~$display("FAIL: gain not monotonic7');

~~~~~~~~~~~~~~else
$display("fpass: gain okay");

X
Cu)e
[)z gel d'

if (abs(V(pout,nout) -out) >50m)

$display("FAIL: gain out of range');
Jelse if (measGain < prevGain)

gain =i;

end

C'opyu @hf 200.7))()

rea
inee sed
beginlGan
$dsly'an sert %d"gi)
linGain - pow 1O0 (gain - 20)/20).

initializeDUTO);
pup =o0;

- C:heck evelry mode and every setting

16.

rrvan

initializeTestbenchO);

Exhiaustive regression testing

* Verification by visual inspection must be avoidedl

- Errors cJan be very subtle
- Too many tests, too many signals
- Too time consumuing, too error prone

=;

=='i'-!; (g|l s glEl(ll

Sina frequeOA2ncy
is

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20 IIXot

,,

Model-Based Verification

Mixed-Signal Simulation

* A systematic approach built on two

importantV concepts
- Mixed-signal simulation

* Combined logic and circuit simulation

* Based on VeSrilog-AMS or VHDL-AMS
* Verilog-AMS

* Allows efficient co-simulation of analog and-CobnsVrlgad

digital sections
- Mixed-level simulation

- PC
* VHDL-AMS

* D:ram:atically accielerates simulation

Addls analog; extensions to VHDL (there is no

~~~~~~~~~~~-

~VH4DL-A)

21

22

module flash( out, in, cik, bias, pwrdn, vdd);

'Ca hav bot loi an

inputin, cIk, bias, pwrdn, vdd;

electrical in, bias,

ots ddsrel
elanaeotrical

v-dd

vaue evn-die

* Relc

initial begin
end

/1 Vriog

portsclz7aceeaessmua

analog begin

endmnodule

tests to both

develolpmfent,

kernel

24

oliglt7)( [egl}'.C)fC,19/)g11 AlRg, <.ud

Tes Bec

Decompose mo1del into blocks.

Then perform mnixed-level simulation.

jM1

* Model must be 'pin accurate'.

* Model can be developed before schematic

M2

*Rpaeoeboka

S3

M4

iewt

M5 L

ceai

*5Generally takes too long to simulate with full schematic

Geyr<q}Dt>200 D>iga''GhdCalewshytl
ARlSnf

tc

__|_______________________________

ca eosre

- Schematic designed to match model

- Model becomes the 'specification' or target
- Naturally encourages; top-down design=

mode
m
l

- Model can be usedl for system level verification,

An*alog sections rnin the SPICEI

"'Connect Modules" (:special modules) aeutomatically inserted as >

needed to convert digital to analog signals and vice versa

Apply th sam

wit

vial

th evn:xorrt dlrivenr (digital) keornel

_____________
1/ Veri/og-A

cici

Verification can start b efore schematics are

~~~~~~~~~~~~~~-

Inta/Awy (Vrlg setosrni

Analo(:g sigals, varfiabes and events

end

trnito-ee

- Drpamatically acceleraes simulatio tn

...

23

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2
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* Milxed-level sim time for loopback test

Repeat the process recursively.

B3 Test Bench

Representation

B3 TesBenc

Tests Time

Verilog

~~~~~~~Verilog-AMS
@ xstr
~~~~~~~PGA
@ xstr
~~~~~~~~ADC
@ xstr
~~~~~~~~Bias

l ll ll l
I 11 11 1
I 11 11 1
I 11 11 1

.v.

HU

2Dr

ThS

Ai

28

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crewhlst

R}

To
~~~.*
reuedrto*frgeso

et
t_1.__Further1 patito blck so ___,,
as to reur
feXwer trnitr inX a mie-ee sim
* Cosis[1&
increase moelT dvelomen

Numbers given are representative of what would be common for this type of circuit.

CApy

Supp-les
Clc

ilnputs

Analo inputse

1. *~lF~

2h7.GFlIR
h1d
Ce

E
l

.whx
All R;,ght

Res
dT

77gg1

rX

Z}X

Wha Modele
is
rexplaemnatio

ostates

G~

RghtR2rI007,Dlxg

Moeln Pin (wit Assertions)

& holdonditions

11
Cp*
~

3 hours

- Ca ad mor fo pefomac if nede

heckingslpl

Assertibonks

1 lnralwayboel1tru
mustt
lpe
or monitorin .cne opues

Till

50

* Addtla
assertion foamre

Aneaserto irnisos
acnitin amoitoed-lpaslsivel tha
2Stp

77X7
f7b
sX/7-

* Ruin paale on mutil coptr

* Useful

25

6 min
6 hour
12 hours
1 hour

Fucioa moel ar geeal sipl

an eas to writ
* Moe requirementsZ
- Pin acurt - alow mixed-levelsimulatio

* Goa is toc completeo allerso

by
tests
monn
1.Futhr

250
150

* TIests can be run simultaneously

Tree compulters enough to verify overnight
-0E~~~~~~~

^
27

cyrltf
00

2 min

50O

* Each model must be pin-accurateDAC @ xstr

* irrcial decomposes vrification

250

31~~~~~~~~~~~~~~ 321

D|

Validateth-upl
ilo
s in te -expete range,ho
Models
expectedpowe consumptiond iontalrode
ttergtfeuny

hc

eu

odvoain

Verifyer tha th signal inutiswihicmpiacerag

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Verification Methodology

Example: Flash ADC

module flash_adc out, in, cik, bias, pwrdn, vdd );

input in, cik, bias, pwrdn, vdd;

output [15:0] out;

electrical in. bias.,vdd;

ICo declaratons

J-

integer i, level;

To verify specs

rg[15:0] d;

always @(posedge clk) begin

iaFulSrUt= (I(vdd,bias)> 6uU) 11 (I(vdd,bias) <e^14Su)

Assertions for powFer

andS bias -.

yor (i0; i<16; ii+l)

Functional model

pwrFault = (V(vdd) > 1.9)1 (V(vdd) <

leveli= I 6*(V(in)+0.5);

1.7);

d[i] - (i < level);

- Identify which blocks should be simulated together

* Create t-lv schematic admodels

oe fcba

1u: 500u, Moe poe cosupto

l Th.9t
UEl1 :00DI7E5 tle

AllRl

ht

* Perform mixed -level simulation

* Automate regression testing
Dd
Jd
|CUpy34 gxh,t2007 xlL,D
i,g 9wG
xCl.I All R;NghtR dm.l
d

* Verified design
.0 .
* Vlerified spec - important for large teams
* Verified top-le:vel: model- critical for jP
* Control of risks enables greater innovation
* Redulced needl for senior designers
* Encourages
* Encourages
top-down design
deslgn
* Aids reulse,tlest development
35

entify whic
evel
m1
7 odels need doping

- Id

to -e e n
]} Generatec te outu

V(vdd,bi)'<+ pwdn 0: 0.5 +20k*I(vdd,bia)'

I(vdd) <+ pwrdn? 1

J*Dvlpmodeling
adsmutinplans
Deeo
an
iulto

* May be more thtan one for each block<

//convertinput to aninteger

assign out - (pwrdn I pwrFault I biasFault) ? 16'bx d;

endrnodule
33

-To verify concewrns (brainstorm)

Intenal variabiles -

reg pwrFault, biasFault;

end

* Develop verification plan

CApyright 2007,Desge' Gtde Consltin

Inc.

All

Rihts

* "Sign-off" quality required

Digital verAification engineers used to Verilog models

~~~~~~~~~~~~-

Ibeing the implementation

- Digital methodology requ=ires trustworthy models
- Must match the functionality (all modes) exactly
- Delivering bad model worse than delivering no
motIdel at all;
* Generally
must beunwilling
Verilog toortake
VHDL
Digital designers
AMS models

~~-

Resrvd

Copyt

* Needs an adlaptor to fit into top-level testbench

- Top-level testbench written for AMS models

36

hU

2007

Desgne'

Gide Consltin

Inc. All Rihts Resre

ignes||ss2
Trrar-s
cannot givea
X Xw7s~~~~~~~~~~~~~~ Veiiato needs focu{s deTsor

consiasten witecrcusiontetn
*~~~~
Drve by~ veiicto enine

* Role

- Capturetoo deinnverification
pa

- Test bences verify ehavior of odelsWritemodelg&scitn

-~~~~~~~~~~~~~~~~~
Write,eve debug,ho
&sue runl test benhe
37~~~~~~~~~~~
38 - TRackbug
Cpnsisten Dig'Gtclrul
I~
i

lF

pt~~~C

lR

Verification Plan Example

* Must always be satisfied (assertions)

Writing the Model & Testbench

* Read spec, interview designer

- Power consumption okay

- Common-mode output voltage okay

- Determine basic function of each block &

- Correct supply voltages at all blocks

- May need to supplement or actually write,

- Correct bias voltages & currents at all blocks

- No setup/hold violations on control registers

description of each pin

specification

- Etc.

* Use verification plan to write model

- Do not over model

* Let's step through the process

* Must be satisfied in specific situations (tests)

Power consumption in power-down mode
No pop upon power-up
Gain monotonic and within tolerances
Etc.

39

- Give careful attention to needed assertions

40
.

lt. Th. AuTh ht R

C.pymght2OO7, Dg.'. G..k C. lt. Th..

Writing a Model Example

* Step 1: Capture basic behavior

* Ste 2: Ca ture in descri tions

Out

4'

.
Charge Pump

C.py. ht. 21107,D

G.d

it

AliR ht R

42

Writing a Model Example

0

Step ci: Identify assertions

-Vddl.8V10%
Ibias = 10 mA 5% when enabled

- Excerpts shown next

43

Pin
UP, UPb
ON, DNb
bias
enable
Iadj

in
in
in
in
in

Type
Pseudo-differential
Pseudo-differential
10 gA sink, 5%
Boolean, active high
4-bit binary

Description
Sources Icp to output
Sinks Icp from output
0.5 V @ 10 kQ nom.
Activates OP
Sets Icp; 0-500 gA

Cladj
R2adj
C2adj
out

in
in
In
out

4-bit binary
4-bit binary
4-bit binary
Analog voltage

Sets Cl; 0- 100 pF

Sets R2; 0 - 100 kQ
Sets 02; 0 - 100 pF
Rail to rail

pwr

1.8Vdc supply, 10%

Vdd, Gnd

Dir

&pyphU2007D

D'ig.''.Ghd C. lt. N.

end

always begin I/set output current value

Ion = 31 .25u * Iadj;
@(Iadi);
end

always begin /1 assertions

vddFault = (V(vdd) > vddmax)

(V(vdd) < vddmin);
ibiasFault = (V(Ibias) > ibiasmax) j
(V(Ibias) <ibiasmin);
@(UP or DN);

411fl

G dC.

it

1.2 mAmax.

AllRhtR

Writing a Model Example

end
assign fault = vddFault I ibiasFault;
etc
.

always @(UP or DN) begin I/model charge pump

if (UP && !DN) state = 1;
else if (!UP && DN) state = -1;
else state = 0;

Step .. Write the model

*
4.

Writing a Model Example

Down
bias
Enable

C2adj

All flght R

analog begin
II charge pump
state = state * (enable && fault);
(out) <+ Ioniransition(state, 0, tt);

//filter
(out) <+ ci * ddt(V(out));
V(out,int) <+ r2 * (outint);
(int) <+ c2 * ddt(V(int));
I/supply
I(vdd) <+ enable? 1.2m 0;

end

II bias input (norton equivalent)

(Ibias) <+ enable? (V(Ibias) - 0.4)/10k 0;

Cyi't..'. D"i.''. Gd.'C'. lt. N.

4llR.

Writinga Model Example

Analog VerificationEngineers

* Step 5: Write test bench for model

* Lead Verification Engineer

- Not shown (similar to earlier example)

- Peer to design lead
* Step 6: Perform mixed-levelsimulations
* Has ultimate reHsponsibility for.functional silicon
- Adjus testbnchtolrancesto fit
ircuit- Verification, simulation, & modeling plans
- Resolveany
remaining differences- Track bugs, track changes to spec, help manage TLS,
* If circuit correct: fix spec, model, testbench

maaemdl,
tsece

* Individual Verification Engineers

* If testbench correct: fix circuit

- Wrtes mod:els, test benches

* Repbeat for all modlels

* Repeat for top-level Verilog model

-0 Trop-level testbench must satisfy verif. plan
45
CUp 200.DI7l,D l,ge .GhC S lh c AllRl
ght

* Typically 1 VE needed for every 5 DE

-0 D:ependls strong;ly on number off modes in design
46
t2OO7
6
rL,D
i,g 9wG .lC~ All R;8ghtR....d1
|CUpvrx,y
J

i
XX

ht R

* Phase 1: Verificationr separate from design

* Verification does not require TDD flow
- Designeir's not dependent on models,
- Layer ov7er existing flows with little disturbance
sybtireaonhpwhTD
testbenches created by veSrification engineers*Fom
- Goal: build understanding, experience & trust;
minimize impact & risk on design

- Verification methodology provides models that

* Phase 2: Integrate verification & design

- lDesigners dlependent on mnodels, testbenches

aid TDD
- Modlels help to close gap between system

desigyn and circuilt design;

- TDD provide top-level schematic and clean
interfaces that smooth verification process

* N>atural wvith d:e:rivative designs

- Goal: maximize efficiency of design team

- Leads to top-down design
47

y
2007,DGdi
C0hbgr1t
iii

lh
'ilieel
Iy,l

AllRl,yht

f.v48
R

|-

* Analog circuits have changed

- Large complex & 1000s of modes common

di

yhUi2OO7D

GititdeCer

lh

Ix, llRc
htIRi,e5.rY d

* H. Chang & K. Kundert. "Verification of Complex

Analog and RF IC Designs." The Proceedings of the IEEE.

* Methodical verification of these circuits is possible

To be published in 2007.

* K. Kundert & H. Chang. "Verififcation of Complex

- And will soon be expected

* Model-=based verification iS only approachAnlgItraeCicts"IC06

Evrthn es i uc ooso
-~~
- Basedt on mixed-level simulation
*~~~.
Beeft fro veifcainngner
* Naturally
complements TDD

* K.fKundert & 0. Zinke. The D>esigner's Guide to VerilogAMS. 2004.

* Substantial ch:ange, tough to get startedX ................J

* K. Kundert. "Principles of top-down mixed-signal

design." www.designers-guide.org/Design.
A. Meyer. Principles ofFunctional
2003.

~~~~~*

Verlfication.

- Ca::ll me if you need help 0;.................5l

49

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