Allegro Design Preparation

Board Outlines: To successfully translate a board outline into Expedition PCB, this element in Allegro PCB must be contiguous. Ensure that
there are no gaps or opens on your board outline before beginning data translation.

Design Files: Typically your original Allegro PCB design file exists in a design tree location on your system along with multiple files that were
created during the original Allegro board design. Many of these files are very large and are not required by the translator.

To best prepare your Allegro design for translation, ensure that your source schematic and layout design are synchronized and archived,
then copy ONLY the Allegro design file (meaning the .brd file) to an empty directory (or container) on your system. This is the only file that
will be needed for the translation.

Allegro Translation Directory Structure

Your final Allegro translation directory structure should look as follows:

|-- Translations
|-- <current board name>
|-- board.brd

Related Topics
Copying the Allegro SKILL Scripts

Installing the AL2EXP Translator

The Allegro to Expedition translator is included as an option in the standard Expedition software install. The translator is free of charge but
must be obtained through SupportNet software download.

Prerequisites

You must have a SupportNet login to access software downloads.

Procedure
1.

Download Expedition Enterprise Flow EE 7.9.2 software.

2.

Unzip the downloaded file.

3.

Run setup.exe to launch the Mentor Graphics Installer.

4.

Enter your target file location for the software installation or use the Browse button to traverse your directory structure.

5.

Expand the Translators and 3rd Party Interfaces section and click the checkbox next to Allegro to Expedition Translator
to select the translator for installation as shown on Figure 1-1.

Figure 1-1.

Selecting Allegro to Expedition Translator

6.

Click Next>> to advance the installer, AGREE to the License Agreement and INSTALL to begin installation.

Results
The translator installs into the targeted directory and creates the translators directory (under SDD_HOME as shown in Figure 1-2) that
contains folders as follows:

skill_scripts - location of the 15 SKILL scripts used by the translator

template - location of internal files used in Expedition project creation

win32 - location of the al2exp.exe and the tech_translator.exe

Figure 1-2. Translators Installation Directory Structure

Related Topics
Setting Environment Variables (WINDOWS)

Setting Environment Variables (WINDOWS)

Environment variables are strings that contain information that point to your translator software location. System Environment Variables
must be set on the WINDOWS system where the Allegro SKILL scripts will be executed that point to your translator software location.

Prerequisites

Allegro to Expedition software must be loaded on a system as shown in Figure 1-2.

Procedure
1.

Open System in the Control Panel of your Windows system.

2.

Click the Advanced tab and then the Environment Variables button.

3.

Set the following environment variables:

AEX_BIN_ROOT=<install path>\SDD_HOME\translators\win32\bin

AEX_ENABLE_JOBPREFS_LAYER_FIX=1

ALLEGRO_LONG_PACKAGE_NAME=TRUE
Tip: Adjust the AEX_BIN_ROOT path as necessary if the translator was not loaded in the default location. The SKILL script
runs a program called tech_translator.exe which must be found in the folder referred to by the AEX_BIN_ROOT variable.

4.

Click OK to apply the environment variables and close the System Properties dialog box.

Related Topics

Installing the AL2EXP Translator

Windows Memory

Windows Memory
Due to Windows OS limitations, the translator cannot allocate more than 2GB of memory. If you plan to translate a very large design, the
translator may run out of memory and display an unable to allocate enough memory to translate current design message. Shoul d this
occur, the suggested action is to configure Windows to provide 3GB of virtual address space. To do this, refer to the Microsoft Articles at the
following locations:

http://msdn.microsoft.com/en-us/windows/hardware/gg487508.aspx or

http://www.microsoft.com/whdc/system/platform/server/PAE/PAEmem.mspx

Both of these locations describe how to add 3GB to the Windows boot.ini file.

After modifying the boot.ini file, you will need to reboot your computer for the allocation to take place.

Related Topics
Installing the AL2EXP Translator

Setting Environment Variables (WINDOWS)

Allegro Data Extraction

What is a SKILL Script?

SKILL is a programming language developed to be used with Cadence tool suites, similar to
the Mentor Graphics AMPLE language. This scripting method provides an interface with the tool suites to quickly extract and manipulate
data.

SKILL scripts are executed in the Allegro PCB CIW (Command Interpreter Window).

The SKILL scripts provided with the Allegro2Expedition translator are to be used only with Allegro PCB.

Related Topics
Copying the Allegro SKILL Scripts

Executing the Allegro SKILL Scripts

Copying the Allegro SKILL Scripts

Tip: The SKILL scripts are located at
<install path>\MentorGraphics\7.9.2EE\SDD_HOME\translators\skill_scripts
see Figure 1-2 for reference.

The SKILL script files must be copied to your Allegro system prior to running them on Allegro PCB.

Procedure

1.

Go to the <install path>\SDD_HOME\translators\skill_scripts directory.

2.

Group select all the *.il files.

3.

Use Ctrl-C or use the right-mouse menu Copy command.

4.

Paste the files in your $HOME\pcbenv directory.

Tip: The $HOME\pcbenv directory is the storage location for SKILL scripts for Cadence tools.

Executing the Allegro SKILL Scripts

SKILL scripts are run on the Allegro PCB system with the design active in the tool. This task creates the devices and <design name>_MGC
directories with the extracted data.

Prerequisites

You must complete the Installing the AL2EXP Translator, Copying the Allegro SKILL Scripts and Allegro Design
Preparation tasks before you can execute the SKILL scripts on your design.

Note
If your data extraction is taking place on two different WINDOWS systems, make sure that the Setting Environment Variables
(WINDOWS) task is complete prior to executing the SKILL scripts.

Procedure
1.

Open the Allegro layout (.brd) design file in the Allegro PCB Editor.

2.

In the Allegro CIW type the following commands:

skill load dfl_main.il

main out
Tip: The main out command initializes the Allegro to Expedition translation dialog box.

3.

When the Allegro to Expedition translation dialog appears, decide if you need to override any options. Should this be the case,

complete the Round Trip Options - Override Defaults or Overriding One Way Options tasks (refer to "Overriding Default Options" for full
information).

create_devices
The SKILL scripts use the Allegro create_devices command to export device files to the ...\devices folder in the design directory. This
command will fail when encountering one-pin components that are no-connects, encountering device names that contain an equals sign (=)
or encountering device names that exceed 32 characters. To complete the data export process, you must fix the design board to make the
create_devices command work.

Removing Components

To remove a geometry without leaving Allegro, use the SKILL command shown below. In this example the device with reference designator
LB1M1 will be removed.

skill axlDeleteObject (axlDBFindByName (refdes LB1M1) )

Resolving Device Names that Contain an Equals Sign

To resolve the problem created when the SKILL script encounters an Allegro device name containing an equals sign (=), you must do one
of the following:

Option 1: Edit the device name in the Allegro Concept HDL schematic and forward annotate it to the board.

Option 2: Remove the device from the Allegro PCB design.

Resolving Device Names that Exceed 32 Characters

Device names that are greater than 32 characters can be handled by setting the Allegro environment variable
ALLEGRO_LONG_PACKAGE_NAME to a value of TRUE.

After deleting geometries or resolving device names to clear your create_devices problems, save the Allegro PCB database, then re-execute
the SKILL scripts (as shown in "Executing the Allegro SKILL Scripts").

Overriding Default Options

Prior to launching data extraction, you can override/change the default translator settings for any of the output choices (Round Trip or One
Way) by selecting the Override defaults checkbox next to either setting as shown in Figure 2-1.

Figure 2-1. Override Checkbox in Allegro to Expedition Translator Dialog Box

Round Trip Options - Override Defaults

"Executing the Allegro SKILL Scripts" has the option to override the default settings for Round Trip use with Expedition PCB (DFL mode).
When the Allegro To Expedition translation dialog appears, perform the following steps to override these default settings.

Prerequisites

You must complete Installing the AL2EXP Translator, Copying the Allegro SKILL Scripts and Executing the Allegro SKILL
Scripts tasks before you can override/change the default translator settings.

Procedure
1.

In the Allegro to Expedition translation dialog box, check the Round Trip Override defaults checkbox.

2.

Click the Start Round Trip button.

3.

The Round Trip Options dialog appears as shown in Figure 2-2. Clear or set the appropriate options - using Table 2-1 as
a guide for your selection.

4.

Click Run to start translation or Close to close the selection box without applying changes (you will be returned to the
initial Allegro to Expedition translator dialog).

Table 2-1. Round Trip Translation Options

Option Name

Description

Keep modified net class

When checked, any modifications made to the Net Class rules in Expedition PCB (DFL mode) are used.

rules

Unselect this option to use the Net Class rules defined in Allegro PCB.

Keep modified net

When checked, the high speed rules defined in Expedition PCB (DFL mode) are used. Unselect this option

properties

to use the high speed rules defined in Allegro PCB.

Keep modified board items

When checked, opens the other_items.caf file which enables you to use all of the changes made in a
previous editing session of Expedition PCB (DFL mode). If this option is not checked, the other_items.caf
file is deleted.

Use B/B via settings for

Uses the Blind and Buried via settings in Allegro PCB as the clearances. Allegro has two sets of clearances,

clearances

however Expedition PCB (DFL mode) only supports one set.

Enable Swapping

Swapping within Expedition PCB (DFL mode) is allowed.

Treat plane shapes as

Within Expedition PCB (DFL mode) plane shapes as via obstructs are not supported. When set, the

Trace Obstructs

translation creates a via obstruct that matches the plane shape that meets the requirements for
Expedition PCB.

Keep modified net class

When checked, any modifications made to the Net Class rules in Expedition PCB (DFL mode) are used.

rules

Unselect this option to use the Net Class rules defined in Allegro PCB.

Ignore all voids

Void areas in planes defined in Allegro are ignored by a default to 400 mils (on a mil board) and are not
passed through to Expedition PCB (DFL mode). You have the option to designate a different value by
selecting the Ignore all Voids option and entering a new value in the Void Area Ignore Size field. This new
value overrides the 400 mil default setting.

Run DRC at invocation

Starts and runs the design rules checking when Expedition PCB (DFL mode) is invoked and highlights any
problems when the design is displayed. By using Select Highlighted Items, it is now possible to run the
Re-Route command and the system will automatically try to eliminate these DRC violations.

Find Via name file

Allows you to specify a padstack as an explicit via or fiducial. The default name for the text file is
ViaFiducial_ID.txt (this file can reside anywhere).

Void Area Ignore Size

Works with Ignore All Voids entry. Any entered value overrides the 400 mil default setting.

Virtual Pin Size

Defines the size of virtual pins within Expedition PCB (DFL mode).

Default Via

Allows you to select the default via.

Export Electrical

When checked, exports electrical constraints.

Constraints

Figure 2-2. Allegro To Expedition Settings Round Trip Options Box

Results
Round trip translation will commence with your settings in place for use with Expedition PCB (DFL mode). The translation creates a new
directory called <your_jobname>_MGC.

Related Topics
Overriding Default Options

Overriding One Way Options

You can override/change the default translator settings for the One Way Translation by selecting the Override defaults checkbox next to
your setting as shown in Figure 2-1. When this dialog appears, follow the procedure detailed below to select your specific one way
translation settings.

Prerequisites

You must complete Installing the AL2EXP Translator, Copying the Allegro SKILL Scripts and Executing the Allegro SKILL
Scripts tasks before you can override/change the default one way translator settings.

Procedure
1.

In the Allegro to Expedition translation dialog box, check the One Way Override defaults checkbox.

2.

Click the One Way translation button to dispaly the Allegro To Expedition One Way Settings dialog box.

Figure 2-3.

Allegro To Expedition One

Way Settings Dialog Box

3.

In the Allegro to Expedition One Way Settings dialog box, set/clear the appropriate options using Table 2-2 for guidance.

4.

Click Run to start translation or Close to close the selection box without applying changes (you will be returned to the
initial Allegro to Expedition translator dialog).

Table 2-2. One Way Translation Options

Option Name

Ignore all voids

Description

Void areas in planes defined in Allegro are ignored by a default to 400 mils (on a mil board) and
are not passed through to Expedition PCB (DFL mode). You have the option to designate a
different value by selecting this option and entering a new value in the Via Area Ignore size field.
This new value overrides the 400 mil default setting.

Find Via name file

Allows you to specify a padstack as an explicit via or viducial. the default name for the text file

is ViaFiducial_ID.txt (this file can reside anywhere). You may also use the Via Identification file
Select dialog Box.

Export Electrical Constraints

When checked, exports electrical constraints.

Results
One Way translation commences with your settings in place for use with Expedition PCB (DFL mode). The translation creates a new directory
called <your_jobname>_MGC.

Related Topics
Overriding Default Options

Adjusting Plane Obstructs

The Define / Adjust void Parameters in the DFL file (D-File) procedure describes recommended alterations to your LayoutDB.dfl file. Edit this
file with a standard text editor. As the Void Parameters contained in this file are not being set by the SKILL scripts that are run, this file
serves to define how plane obstructs of a defined size and lareger are to be read into Expedition PCB during the translation. This is a
manipulation of the design outside of the software. This may result in a larger file size, but will improve the retention of voids.

Define / Adjust void Parameters in the DFL file (D-File)

Edit the D-file to enable void handling and disable/enable plane route obstructs. The LayoutDB.dfl file appears as shown in Figure 2-4.

Figure 2-4. LayoutDB.dfl File

Prerequisites

You must complete the Executing the Allegro SKILL Scripts task before this file is available for editing.

Procedure
1.

Open the ...\<design_name>_MGC\Work\LayoutDB.dfl file with a standard ASCII text editor.

2.

To enable voids (plane holes) for processing, change Line #10 as follows:

From: 941 IGNORE_VOIDS 0 1

To: 941 IGNORE_VOIDS 0 0

3.

To re-define the void threshold, change Line #11 as follows:

From: 941 IGNORE_VOID_SIZE 0 50000

To: 941 IGNORE_VOID_SIZE 0 7500

Tip: To properly calculate the existing void size, use the following equation:
IGNORE_VOID_SIZE (line #11) divided by LCU (Line #7) = Void Size
[in UNIs* (line #6)]
* Line #6 value settings: If UNI = 1(mm), UNI=2(in), UNI=3(th)

* In the example file above, the IGNORE_VOID_SIZE equated to 500th (.500 in) before it was modified. 50000 divided by
100=500th

Remember the sum in the above equation determines the smallest void area and GREATER to be processed. A 500th void size
is very large in the PCB world. So in order that we may locate and process a much smaller void size, this area was modified
in the above example to be 75th (.075 in).

The bounding box (void) size you will use may vary per design. This value is an exclusion box, the smaller you define this
value, the greater the number of voids (plane obstructs) will be passed into the layout.

4.

Should you need to disable plane route obstructs entirely, change Line #8 as follows

From: 941 planes = route_obstruct 0 1

To: 941 planes=route_obstruct 0 0

5.

Save the D-file (LayoutDB.dfl).

6.

Exit your editor.

Results
Your updated D-file is available for use with the General Options tab of the Allegro to Expedition dialog.

Related Topics
Translator Interface

ViaFiducial_ID.txt
The Find Via name file option in Overriding One Way Options and Round Trip Options - Override Defaults allows you to specify a padstack
as an explicit Via or Fiducial using the default ViaFiducial_ID.txt (this file can reside anywhere).

The format of the file is as follows.

Format.
Via26r10 via ; default via

(explicit name)

Fid26 fid ; default fiducial (explicit name)

P26r12 via ; vias containing this string (ANY padstack with this string in
it will be converted to a via.

Related Topics
Overriding Default Options

SKILL Script Output

The SKILL script creates two sub-directories named ...\<design_file_name>_MGC and ...\devices in the design directory. For example, if
your Allegro design file is named demo_1.brd, then the subdirectory created is named demo_1_MGC. Under no circumstances should
the ...\devices subdirectory be moved or deleted as it contains all the electrical packaging data that is required to create the Expedition PCB
Parts Database (PDB) that is used in the second part of the translation process.

Caution
Any Allegro design file that requires the SKILL scripts execution should be located in a DIFFERENT root directory during
execution to ensure that only those devices for that specific Allegro design are in that designs ...\devices directory.
Generating the SKILL output files for two or more designs from the same root directory will cause part package information
for these designs to be merged and is not recommended.

Related Topics
Translation Process

Translation Process

The translation process takes the extracted Allegro data obtained through the SKILL Script Output
through the translator to import the design into Expedition PCB.

This is referred to as Netlist Flow as the Expedition PCB project is not associated to any schematic data at this time.

Cells, Padstacks and Part information is available as a by-product of the translation and can be edited using the Cell Editor and the PDB
Editor available as part of the Library Services in Expedition PCB.

Translator Interface
The Translator user interface consists of two dialog boxes that you use to target the input directory (created by the SKILL Script Output part
of the translation) and the output directory for your new Expedition project files. If the target for the output directory is left blank, the
translator will create a directory with the name <board file name>_EXP at the same directory level as the input directory (for example, if
your Allegro design file name is demo_1.brd, the default output directory is demo_1_EXP).

The translator interface contains three tabs as follows:

General Options

HKP Converters

Output Logs

General Options

To access: Click the General Tab on the Allegro to Expedition Translator dialog.

Use these options to control the translator behavior.

Figure 3-1. Default State of the General Options Tab

Field

Run D-File

Table 3-1. General Options Tab Contents

Description

Values

Invokes the AlToExp.exe executable as part of translation

Checkbox

Override default

Default template file location is <install path>\SDD_HOME\Template. This option will

Checkbox and Input

template directory

override this location to obtain the template files for the output Expedition project from

file path text box.

Translator

the specified directory.

Override default

Default executable directory is in the Expedition PCB install directory. This option will

Checkbox and Input

executable

override this location to obtain the HKP2*.exe executables from the directory specified

file path text box.

directory

in the corresponding edit box.

Add plane shapes

Creates a plane shape configuration file to optimize plane shapes that have a large

file

number of vectors (see Usage Notes).

Checkbox

Usage Notes

In Allegro PCB, during the implementation of plane shapes creates hundreds of vectors that can cause a performance hit
when the design is translated and opened with Expedition PCB. Creating the Plane Shape Configuration file (from the Add
plane shapes file option) optimizes the number of vectors in the Allegro process plane shapes dramatically. The
difference in the performance of an Expedition PCB design with this option versus without it, especially if there are a large
number of layers with planes, can be about 10 to 1 (depending on the complexity of these planes). It is highly
recommended to use plane shape vector optimization whenever possible.

Related Topics

Translator Interface
HKP Converters
Output Logs

HKP Converters
To access: Click the HKP Converters Tab on the Allegro to Expedition Translator dialog.
Use these options to control the element translation.

Figure 3-2. Default State of the HKP Converters Tab

Table 3-2. HKP Converters Tab Contents

Field

Padstacks

Description

Executes HKP2PadstackDB.exe to convert Padstack.hkp to

Values

Checkbox

PadstackDB.psk

Cells

Executes HKP2CellDB.exe to convert Cell.hkp to CellDB.cel

Checkbox

Parts

Executes HKP2PartsDB.exe to convert PDB.hkp to PartsDB.pdb

Checkbox

Job Preferences

Executes HKP2JobPrefsDB.exe to convert JobPrefs.hkp to

Checkbox

JobPrefsDB.jpf

Net Class

Executes HKP2NetClassDB.exe to convert NetClass.hkp to

Checkbox

NetClassDB.ncl

Net Properties

Executes HKP2NetPropsDB.exe to convert NetProps.hkp to

Checkbox

NetPropsDB.npr

Layout

Executes HKP2LayoutDB.exe to convert Layout.hkp to

Checkbox

LayoutDB.lyt

Usage Notes
As all output files with the exception of Padstack.hkp and Cell.hkp are created by the AlToExp.exe executable, you will need to run the D-file
translator the first time before you run the HKP translators. Separate options for each converter are available to accommodate times when
you want to change the contents of a particular output file manually, and to convert it to binary. This is useful if you are troubleshooting a
PDB, Cell or Padstack HKP file problem.

Related Topics
Translator Interface

Translation Troubleshooting

General Options

PDB/Cell Mismatch

Output Logs

Output Logs
To access: Click the Output Log Tab on the Allegro to Expedition Translator dialog.
As translation is underway the Expedition PCB project file generation process displays on the Output Log tab. You see the executable full
path as well as its command line parameters. If the command fails, the Output Logs Tab displays the message command_name finished
with error(s).
If all executed commands completed successfully, the Output Logs Tab displays the message Allegro to Expedition PCB translator
completed successfully as shown in Figure 3-3.

Figure 3-3. Running State of the Output Logs Tab

Running the Translator from the Command Line

You can invoke the translator in limited command line mode with the input directory (_MGC) path given as a command line parameter. All
other settings and options are set to default values.

E:\<installation path>\SDD_HOME\translators\win32
\bin\altoexp_ui.exe E:\al2exp\demo_MGC

When the translator is executed in command line mode all main window controls and buttons are disabled. See Figure 3-4 to observe the
translator interface appearance when running in Command Line mode.

Figure 3-4. Translator Interface Running in Command Line Mode

Opening the Translated Design

After translation completes, the Expedition PCB design has a keyin netlist and is not integrated with a schematic. In this task the translated
design is opened in Expedition PCB and forward annotated to verify that the design data is correct.

Prerequisites

The design must complete translation successfully in the Output Logs of the translator before you can open the translated
design in Expedition PCB.

Procedure
1.

Double-click to open the .._EXP\PCB\<allegro_design_name>.pcb Expedition PCB design file.

2.

A Back annotation disabled warning dialog appears due to the logic database (meaning schematic) for the Expedition
PCB job being unavailable. Click OK to dismiss the warning dialog.

3.

On the ECO menu, select Run the Forward Annotate to forward annotate the design.

4.

Using the File Viewer, review the ForwardAnnotation.txt file created from the above process. Look for any errors that
might have occurred (warnings are typically informational in nature and do not require corrective action).

5.

Select Display Control from the View menu.

6.

Use the Display Control dialog to verify that all the new pad and trace layers are displayed. You may want to possibly turn
the less critical display data off to help see the more important elements.

Results
Your Expedition PCB design is now available for use.

Related Topics
Translation Troubleshooting