D
D
D
D
D
D
D
D
1OUT
1IN
1IN +
GND
VDD
2OUT
2IN
2IN +
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
VDD
NC
NC
1IN
NC
1IN +
NC
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
2OUT
NC
2IN
NC
NC
GND
NC
2IN +
NC
D, JG, P, OR PW PACKAGE
(TOP VIEW)
NC No internal connection
description
The TLC272 and TLC277 precision dual
operational amplifiers combine a wide range of
input offset voltage grades with low offset voltage
drift, high input impedance, low noise, and speeds
approaching those of general-purpose BiFET
devices.
30
25
Percentage of Units %
These devices use Texas Instruments silicongate LinCMOS technology, which provides
offset voltage stability far exceeding the stability
available with conventional metal-gate processes.
DISTRIBUTION OF TLC277
INPUT OFFSET VOLTAGE
473 Units Tested From 2 Wafer Lots
VDD = 5 V
TA = 25C
P Package
20
15
10
0
800
400
0
400
VIO Input Offset Voltage V
800
description (continued)
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CHIP
FORM
(Y)
0C to 70c
500 V
2 mV
5 mV
10mV
TLC277CD
TLC272BCD
TLC272ACD
TLC272CD
TLC277CP
TLC272BCP
TLC272ACP
TLC272CP
TLC272CPW
TLC272Y
40C to 85C
500 V
2 mV
5 mV
10 mV
TLC277ID
TLC272BID
TLC272AID
TLC272ID
TLC277IP
TLC272BIP
TLC272AIP
TLC272IP
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC277CDR).
In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC272 and
TLC277. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote
and inaccessible battery-powered applications. The common-mode input voltage range includes the negative
rail.
A wide range of packaging options is available, including small-outline and chip carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand 100-mA surge currents without sustaining latch-up.
The TLC272 and TLC277 incorporate internal ESD-protection circuits that prevent functional failures at voltages
up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling
these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized
for operation from 40C to 85C. The M-suffix devices are characterized for operation over the full military
temperature range of 55C to 125C.
P4
R6
R1
N5
R2
IN
P5
P1
P6
P2
IN +
R5
C1
OUT
N3
N1
R3
N2
D1
N4
R4
D2
N6
N7
R7
GND
1IN +
(3)
(2)
1IN
2OUT
VDD
(8)
+
(1)
(7)
60
1OUT
(5)
(6)
2IN +
2IN
(4)
GND
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 4 MINIMUM
TJmax = 150C
TOLERANCES ARE 10%.
ALL DIMENSIONS ARE IN MILS.
73
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN .
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA 25C
POWER RATING
DERATING FACTOR
ABOVE TA = 25C
TA = 70C
POWER RATING
TA = 85C
POWER RATING
TA = 125C
POWER RATING
725 mW
5.8 mW/C
464 mW
377 mW
N/A
FK
1375 mW
11 mW/C
880 mW
715 mW
275 mW
JG
1050 mW
8.4 mW/C
672 mW
546 mW
210 mW
1000 mW
8.0 mW/C
640 mW
520 mW
N/A
PW
525 mW
4.2 mW/C
336 mW
N/A
N/A
VDD = 5 V
VDD = 10 V
C SUFFIX
I SUFFIX
M SUFFIX
MIN
MAX
MIN
MAX
MIN
MAX
16
16
16
0.2
3.5
0.2
3.5
3.5
0.2
8.5
0.2
8.5
8.5
70
40
85
55
125
UNIT
V
V
C
TEST CONDITIONS
TA
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIO
TLC272C
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
TLC272AC
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VIO
IIO
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
2 5 V,
V
VO = 2.5
IIB
VICR
VOH
VOL
AVD
CMRR
kSVR
IDD
25V
VIC = 2.5
25C
Low-level
Low
level out
output
ut voltage
VID = 100
100 mV,
Large-signal
Large
signal differential voltage am
amplification
lification
Common-mode
Common
mode rejection ratio
VO = 0.25 V to 2 V,
RL = 10 k
IOL = 0
RL = 10 k
VIC = VICRmin
Supply-voltage
S
l
lt
rejection
j ti ratio
ti
(VDD /VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 2.5
2 5 V,
V
No load
VO = 1.4 V
VIC = 2.5
2 5 V,
V
MAX
1.1
10
Full range
UNIT
12
25C
0.9
230
2000
Full range
mV
6.5
25C
Full range
3000
25C
200
Full range
500
V
V
1500
25C to
70C
1.8
25C
0.1
60
70C
300
25C
0.6
60
70C
40
600
25C
0.2
to
4
Full range
0.2
to
3.5
25C
3.2
3.8
0C
3.8
70C
3.8
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
output
High
level out
ut voltage
TYP
V/C
0.3
to
4.2
pA
pA
25C
50
0C
50
70C
50
25C
23
0C
27
70C
20
25C
65
80
0C
60
84
70C
60
85
25C
65
95
0C
60
94
70C
60
96
mV
V/mV
dB
dB
25C
1.4
3.2
0C
1.6
3.6
70C
1.2
2.6
mA
TEST CONDITIONS
TA
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIO
TLC272C
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
TLC272AC
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VIO
IIO
VO = 1.4 V,
RS = 50 ,
VO = 1.4 V,
RS = 50 ,
VICR
VOH
VOL
AVD
CMRR
kSVR
IDD
VIC = 0,
RL = 10 k
VIC = 5 V
Low-level
Low
level out
output
ut voltage
VID = 100
100 mV,
Large-signal
Large
signal differential voltage am
amplification
lification
Common-mode
Common
mode rejection ratio
VO = 1 V to 6 V,
RL = 10 k
IOL = 0
RL = 10 k
VIC = VICRmin
Supply-voltage
S
l
lt
rejection
j ti ratio
ti
(VDD /VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 5 V,
V
No load
VO = 1.4 V
VIC = 5 V,
V
1.1
10
0.9
290
2000
Full range
mV
6.5
25C
Full range
3000
25C
250
Full range
800
V
V
1900
V/C
25C
0.1
60
70C
300
25C
0.7
60
70C
50
600
25C
0.2
to
9
Full range
0.2
to
8.5
0.3
to
9.2
pA
pA
25C
8.5
0C
7.8
8.5
70C
7.8
8.4
25C
50
0C
50
70C
50
25C
10
36
0C
7.5
42
70C
7.5
32
25C
65
85
0C
60
88
70C
60
88
25C
65
95
0C
60
94
70C
60
96
mV
V/mV
dB
dB
25C
1.9
0C
2.3
4.4
70C
1.6
3.4
UNIT
12
25C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
output
High
level out
ut voltage
MAX
Full range
25C to
70C
V
VO = 5 V,
IIB
VIC = 0,
RL = 10 k
25C
TYP
mA
TEST CONDITIONS
TA
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIO
TLC272I
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
TLC272AI
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VIO
IIO
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
2 5 V,
V
VO = 2.5
IIB
25V
VIC = 2.5
25C
VOL
AVD
CMRR
kSVR
Low-level
Low
level out
output
ut voltage
VID = 100
100 mV,
L
Large-signal
i
l differential
diff
ti l voltage
lt
amplification
lifi ti
Common-mode
Common
mode rejection ratio
VO = 1 V to 6 V,
RL = 10 k
IOL = 0
RL = 10 k
VIC = VICRmin
S
l
lt
j ti ratio
ti
Supply-voltage
rejection
(VDD /VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 2.5
2 5 V,
V
No load
VO = 1.4 V
10
0.9
230
2000
Full range
Full range
3500
200
25C
Full range
500
25C to
85C
1.8
25C
0.1
60
85C
24
15
25C
0.6
60
85C
200
35
0.2
to
4
V/C
0.3
to
4.2
0.2
to
3.5
25C
3.2
3.8
40C
3.8
85C
3.8
25C
50
40C
50
85C
50
25C
23
40C
3.5
32
85C
3.5
19
25C
65
80
40C
60
81
85C
60
86
25C
65
95
40C
60
92
85C
60
96
mV
V/mV
dB
dB
3.2
1.9
4.4
1.1
85C
Full range is 40C to 85C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
2.4
pA
1.4
pA
25C
VIC = 2.5
2 5 V,
V
V
V
2000
40C
IDD
mV
25C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
High
level out
output
ut voltage
1.1
UNIT
13
25C
Full range
VOH
MAX
Full range
25C
VICR
TYP
mA
TEST CONDITIONS
TA
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIO
TLC272I
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
TLC272AI
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VIO
IIO
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
VICR
VOH
VOL
AVD
CMRR
kSVR
VIC = 5 V
Low-level
Low
level out
output
ut voltage
VID = 100
100 mV,
Large-signal
amplification
Large
signal differential voltage am
lification
Common-mode
Common
mode rejection ratio
VO = 1 V to 6 V,
RL = 10 k
IOL = 0
RL = 10 k
VIC = VICRmin
S
l
lt
j ti ratio
ti
Supply-voltage
rejection
(VDD /VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 5 V,
V
No load
VO = 1.4 V
1.1
10
0.9
290
2000
Full range
Full range
3500
250
25C
Full range
800
V/C
25C
0.1
60
85C
26
1000
25C
0.7
60
85C
220
2000
25C
0.2
to
9
Full range
0.2
to
8.5
0.3
to
9.2
25C
8.5
40C
7.8
8.5
85C
7.8
8.5
25C
50
40C
50
85C
50
25C
10
36
40C
46
85C
31
25C
65
85
40C
60
87
85C
60
88
25C
65
95
40C
60
92
85C
60
96
mV
V/mV
dB
dB
4
5
1.5
85C
Full range is 40C to 85C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
3.2
pA
2.8
pA
1.4
V
V
2900
25C
VIC = 5 V,
V
mV
25C
40C
IDD
UNIT
13
25C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
High
level out
output
ut voltage
MAX
Full range
25C to
85C
V
VO = 5 V,
IIB
25C
TYP
mA
VIO
TEST CONDITIONS
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
Full range
TLC277M
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
Full range
IIO
VIC = 2.5
25V
VOL
AVD
CMRR
kSVR
Low-level
Low
level out
output
ut voltage
Large-signal
Large
signal differential voltage am
amplification
lification
Common-mode
Common
mode rejection ratio
Supply-voltage
S
l
lt
rejection
j ti ratio
ti
(VDD /VIO)
VO = 0.25 V to 2 V
RL = 10 k
IOL = 0
RL = 10 k
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 1.4 V
1.1
10
200
500
3750
2.1
0.1
60
pA
1.4
15
nA
25C
0.6
60
pA
35
nA
0
to
4
0.3
to
4.2
0
to
3.5
25C
3.2
3.8
55C
3.8
125C
3.8
25C
50
55C
50
125C
50
25C
23
55C
3.5
35
125C
3.5
16
25C
65
80
55C
60
81
125C
60
84
25C
65
95
55C
60
90
125C
60
dB
dB
97
3.2
1
125C
Full range is 55C to 125C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
2.2
VIC = 2.5
2 5 V,
V
mV
V/mV
55C
VO = 2.5
2 5 V,
V
No load
V
V
25C
1.4
Supply
y current ((two amplifiers))
mV
V/C
25C
IDD
UNIT
125C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
MAX
12
125C
High-level
High
level out
output
ut voltage
TYP
25C to
125C
Full range
VOH
MIN
25C
25C
VICR
TLC272M, TLC277M
25C
TLC272M
VIO
IIB
TA
mA
VIO
TEST CONDITIONS
TLC272M
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
Full range
TLC277M
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 10 k
Full range
VIO
IIO
IIB
VICR
VOH
VOL
AVD
CMRR
kSVR
TA
VIC = 5 V
Low-level
Low
level out
output
ut voltage
Large-signal
L
i
l differential
diff
ti l voltage
lt
amplification
Common-mode
Common
mode rejection ratio
VO = 1 V to 6 V,
RL = 10 k
IOL = 0
RL = 10 k
VIC = VICRmin
S
l
lt
j ti ratio
ti
Supply-voltage
rejection
(VDD /VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 5 V,
V
No load
VO = 1.4 V
VIC = 5 V,
V
MAX
1.1
10
250
25C to
125C
2.2
UNIT
mV
V
V
V/C
25C
0.1
60
pA
125C
1.8
15
nA
25C
0.7
60
pA
10
35
nA
25C
0
to
9
Full range
0
to
8.5
0.3
to
9.2
25C
8.5
55C
7.8
8.5
125C
7.8
8.4
25C
50
55C
50
125C
50
25C
10
36
55C
50
125C
27
25C
65
85
55C
60
87
125C
60
86
25C
65
95
55C
60
90
125C
60
97
1.9
mV
V/mV
dB
dB
4
55C
125C
1.3
2.8
10
800
4300
125C
TYP
12
25C
25C
IDD
MIN
25C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
High
level out
output
ut voltage
TLC272M, TLC277M
mA
VIO
TEST CONDITIONS
VO = 1.4 V,
RS = 50 ,
TLC272Y
MIN
VIC = 0,
RL = 10 k
TYP
MAX
11
1.1
10
UNIT
mV
1.8
V/C
IIO
IIB
0.1
pA
0.6
pA
VICR
0.2
to
4
0.3
to
4.2
VOH
VOL
3.2
3.8
AVD
CMRR
kSVR
IDD
2 5 V,
V
VO = 2.5
VO = 0.25 V to 2 V
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
25V
VIC = 2.5
RL = 10 k
IOL = 0
RL = 10 k
VO = 1.4 V
VIC = 2.5 V,
V
50
mV
23
V/mV
65
80
dB
65
95
dB
1.4
3.2
mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TEST CONDITIONS
VO = 1.4 V,
RS = 50 ,
TLC272Y
MIN
VIC = 0,
RL = 10 k
TYP
MAX
11
1.1
10
UNIT
VIO
VIO
1.8
V/C
IIO
IIB
0.1
pA
VO = 5 V,
V
VICR
VOH
VOL
AVD
CMRR
kSVR
IDD
VO = 1 V to 6 V,
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 5 V,
No load
VIC = 5 V
RL = 10 k
IOL = 0
RL = 10 k
VO = 1.4 V
VIC = 5 V,
mV
0.7
pA
0.2
to
9
0.3
to
9.2
8.5
0
V
50
mV
10
36
V/mV
65
85
dB
65
95
dB
1.9
mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
11
TEST CONDITIONS
TA
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIPP = 1 V
SR
RL = 10 k,
pF,
CL = 20 pF
See Figure 1
VIPP = 2.5 V
Vn
f = 1 kHz,
See Figure 2
RS = 20 ,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 k,
k
CL = 20 pF,
F
See Figure 1
B1
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
See Figure 3
VI = 10 mV,
V
CL = 20 pF
pF,
CL = 20 pF,
F
f = B1,
See Figure 3
TYP
25C
3.6
0C
70C
25C
2.9
0C
3.1
70C
2.5
25C
25
25C
320
0C
340
70C
260
25C
1.7
0C
70C
1.3
25C
46
0C
47
70C
43
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
MHz
TEST CONDITIONS
TA
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIPP = 1 V
SR
RL = 10 k,
pF,
CL = 20 pF
See Figure 1
VIPP = 5.5 V
Vn
f = 1 kHz,
See Figure 2
RS = 20 ,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 k,
k
F
CL = 20 pF,
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
B1
12
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
f = B1,
See Figure 3
TYP
25C
5.3
0C
5.9
70C
4.3
25C
4.6
0C
5.1
70C
3.8
25C
25
25C
200
0C
220
70C
140
25C
2.2
0C
2.5
70C
1.8
25C
49
0C
50
70C
46
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
MHz
TEST CONDITIONS
TA
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIPP = 1 V
SR
RL = 10 k,
pF,
CL = 20 pF
See Figure 1
VIPP = 2.5 V
Vn
f = 1 kHz,
See Figure 2
RS = 20 ,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 k,
k
CL = 20 pF,
F
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
B1
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
f = B1,
See Figure 3
TYP
25C
3.6
40C
4.5
85C
2.8
25C
2.9
40C
3.5
85C
2.3
25C
25
25C
320
40C
380
85C
250
25C
1.7
40C
2.6
85C
1.2
25C
46
40C
49
85C
43
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
MHz
TEST CONDITIONS
TA
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIPP = 1 V
SR
RL = 10 k,
pF,
CL = 20 pF
See Figure 1
VIPP = 5.5 V
Vn
BOM
B1
f = 1 kHz,
See Figure 2
RS = 20 ,
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 k,
k
F
CL = 20 pF,
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
f = B1,
See Figure 3
TYP
25C
5.3
40C
6.8
85C
25C
4.6
40C
5.8
85C
3.5
25C
25
25C
200
40C
260
85C
130
25C
2.2
40C
3.1
85C
1.7
25C
49
40C
52
85C
46
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
MHz
13
TEST CONDITIONS
VIPP = 1 V
SR
RL = 10 k,
pF,
CL = 20 pF
See Figure 1
VIPP = 2.5 V
Vn
BOM
B1
f = 1 kHz,
See Figure 2
RS = 20 ,
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 k,
k
F
CL = 20 pF,
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
f = B1,
See Figure 3
TA
TLC272M, TLC277M
MIN
TYP
25C
3.6
55C
4.7
125C
2.3
25C
2.9
55C
3.7
125C
25C
25
25C
320
55C
400
125C
230
25C
1.7
55C
2.9
125C
1.1
25C
46
55C
49
125C
41
MAX
UNIT
V/ s
V/s
nV/Hz
kHz
MHz
TEST CONDITIONS
VIPP = 1 V
SR
RL = 10 k,
pF,
CL = 20 pF
See Figure 1
VIPP = 5.5 V
Vn
f = 1 kHz,
See Figure 2
RS = 20 ,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 k,
k
F
CL = 20 pF,
See Figure 1
B1
14
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
See Figure 3
VI = 10 mV,
V
CL = 20 pF
pF,
CL = 20 pF,
F
f = B1,
See Figure 3
TA
TLC272M, TLC277M
MIN
TYP
25C
5.3
55C
7.1
125C
3.1
25C
4.6
55C
6.1
125C
2.7
25C
25
25C
200
55C
280
125C
110
25C
2.2
55C
3.4
125C
1.6
25C
49
55C
52
125C
44
MAX
UNIT
V/ s
V/s
nV/Hz
kHz
MHz
TEST CONDITIONS
MAX
UNIT
3.6
RS = 20 ,
See Figure 2
25
nV/Hz
VO = VOH,
See Figure 1
CL = 20 pF,
RL = 10 k,
320
kHz
VI = 10 mV,
VI = 10 mV,
See Figure 3
CL = 20 pF,
See Figure 3
1.7
MHz
f = B1,
CL = 20 pF,
46
RL = 10 k,
See Figure 1
CL = 20 pF,
F,
Vn
f = 1 kHz,
BOM
B1
Unity-gain bandwidth
Phase margin
TYP
VIPP = 1 V
VIPP = 2.5 V
SR
TLC272Y
MIN
V/ s
V/s
2.9
TEST CONDITIONS
UNIT
RS = 20 ,
See Figure 2
25
nV/Hz
CL = 20 pF,
RL = 10 k,
200
kHz
CL = 20 pF,
See Figure 3
2.2
MHz
f = B1,
CL = 20 pF,
49
RL = 10 k,
See Figure 1
CL = 20 pF,
F,
Vn
f = 1 kHz,
BOM
VO = VOH,
See Figure 1
B1
Unity-gain bandwidth
VI = 10 mV,
VI = 10 mV,
See Figure 3
MAX
5.3
Phase margin
TYP
VIPP = 1 V
VIPP = 5.5 V
SR
TLC272Y
MIN
4.6
V/ s
V/s
15
VDD +
VO
VO
+
CL
VI
VI
RL
CL
RL
VDD
(a) SINGLE SUPPLY
VDD +
20
2 k
1/2 VDD
VO
VO
20
20
20
VDD
VDD +
100
100
VI
10 k
VI
VO
1/2 VDD
VO
CL
CL
VDD
16
V = VIC
17
(a) f = 1 kHz
(c) f = BOM
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
18
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
VIO
Distribution
6, 7
Distribution
8, 9
VOH
High-level
High
level out
output
ut voltage
vs High-level out
output
ut current
vs Su
Supply
ly voltage
vs Free-air temperature
10, 11
12
13
VOL
input
vs Common-mode in
ut voltage
vs Differential input
in ut voltage
vs Free
Free-air
air tem
temperature
erature
vs Low-level output current
14, 15
16
17
18, 19
AVD
Large-signal
amplification
Large
signal differential voltage am
lification
vs Su
Supply
ly voltage
Free-air
temperature
vs Free
air tem
erature
vs Frequency
20
21
32, 33
IIB
IIO
vs Free-air temperature
22
vs Free-air temperature
22
VIC
vs Supply voltage
23
IDD
Supply current
Supply
vs Su
ly voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Su
Supply
ly voltage
vs Free-air temperature
26
27
vs Free-air temperature
28
vs Frequency
29
B1
vs Free
Free-air
air tem
temperature
erature
vs Supply voltage
30
31
Phase margin
vs Su
Supply
ly voltage
Free-air
temperature
vs Free
air tem
erature
vs Load capacitance
34
35
36
Vn
vs Frequency
37
Phase shift
vs Frequency
32, 33
VO(PP)
19
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC272
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC272
INPUT OFFSET VOLTAGE
Percentage of Units %
50
40
60
50
Percentage of Units %
60
30
20
40
30
20
10
10
0
5
0
4
3 2 1
0
1
2
3
VIO Input Offset Voltage mV
40
60
50
Percentage of Units %
Percentage of Units %
50
30
20
40
30
20
10
10
0
0
2
4
6
8
10 8 6 4 2
VIO Temperature Coefficient V/C
10
0
2
4
6
8
10 8 6 4 2 0
VIO Temperature Coefficient V/C
Figure 9
Figure 8
20
Figure 7
Figure 6
60
3 2 1
0
1
2
3
VIO Input Offset Voltage mV
10
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VID = 100 mV
TA = 25C
See Note A
VOH
VOH High-Level Output Voltage V
VOH
VOH High-Level Output Voltage V
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
0
2
4
6
8
IOH High-Level Output Current mA
10
14
VDD = 16 V
VID = 100 mV
TA = 25C
12
10
8
VDD = 10 V
6
4
2
0
5 10 15 20 25 30 35 40
IOH High-Level Output Current mA
Figure 10
Figure 11
14
12
VDD 1.6
VID = 100 mV
RL = 10 k
TA = 25C
VOH
VOH High-Level Output Voltage V
VOH
VOH High-Level Output Voltage V
16
10
8
6
IOH = 5 mA
VID = 100 mA
VDD 1.7
VDD = 5 V
VDD 1.8
VDD 1.9
VDD 2
VDD = 10 V
VDD 2.1
4
2
0
0
4
6
8
10
12
VDD Supply Voltage V
14
16
VDD 2.2
VDD 2.3
VDD 2.4
75
50
Figure 12
25
0
20
50
75 100
TA Free-Air Temperature C
125
Figure 13
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
21
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VDD = 5 V
IOL = 5 mA
650
TA = 25C
600
550
VID = 100 mV
500
450
VID = 1 V
350
300
0.5
1
1.5
2
2.5
3
3.5
VIC Common-Mode Input Voltage V
TA = 25C
450
400
VID = 100 mV
VID = 1 V
350
VID = 2.5 V
400
VDD = 10 V
IOL = 5 mA
VOL
VOL Low-Level Output Voltage mV
VOL
VOL Low-Level Output Voltage mV
700
300
250
2
4
6
8
3
5
7
9
VIC Common-Mode Input Voltage V
Figure 14
Figure 15
IOL = 5 mA
VIC = |VID/2|
TA = 25C
700
VOL
VOL Low-Level Output Voltage mV
800
600
500
VDD = 5 V
400
300
VDD = 10 V
200
100
0
800
700
IOL = 5 mA
VID = 1 V
VIC = 0.5 V
VDD = 5 V
600
500
400
VDD = 10 V
300
200
100
2 3 4 5 6 7 8 9 10
VID Differential Input Voltage V
0
75
50
Figure 16
25
0
25
50
75 100
TA Free-Air Temperature C
Figure 17
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
10
125
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL
VOL Low-Level Output Voltage V
0.9
0.8
0.7
3.0
VID = 1 V
VIC = 0.5 V
TA = 25C
See Note A
1.0
VDD = 5 V
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
0.3
0.2
0.1
0
0
2
3
4
5
6
7
IOL Low-Level Output Current mA
2.5
2.0
VID = 1 V
VIC = 0.5 V
TA = 25C
VDD = 16 V
VDD = 10 V
1.5
1.0
0.5
0
0
5
10
15
20
25
IOL Low-Level Output Current mA
30
Figure 19
Figure 18
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
60
50
TA = 0C
40
30
TA = 25C
TA = 85C
20
TA = 125C
10
0
0
4
6
8
10
12
VDD Supply Voltage V
14
16
RL = 10 k
45
AVD
AVD Large-Signal Differential
Voltage Amplification V/mV
AVD
AVD Large-Signal Differential
Voltage Amplification V/mV
50
TA = 55C
RL = 10 k
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
40
VDD = 10 V
35
30
25
20
VDD = 5 V
15
10
5
0
75
50
Figure 20
25
0
25
50
75
100
TA Free-Air Temperature C
125
Figure 21
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
23
TYPICAL CHARACTERISTICS
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
10000
16
VDD = 10 V
VIC = 5 V
See Note A
1000
IIB
100
IIO
10
0.1
25
TA = 25C
14
12
10
8
6
4
2
0
35
4
6
8
10
12
VDD Supply Voltage V
14
16
25
0
25
50
75
100
TA Free-Air Temperature C
125
Figure 23
Figure 22
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4
VO = VDD/2
No Load
3.5
VO = VDD/2
No Load
TA = 55C
4
3.5
TA = 25C
2.5
2
1.5
TA = 0C
TA = 70C
0.5
I DD Supply Current mA
I DD Supply Current mA
4.5
3
2.5
VDD = 10 V
2
1.5
VDD = 5 V
1
0.5
TA = 125C
0
0
4
6
8
10
12
VDD Supply Voltage V
14
16
0
75
50
Figure 24
Figure 25
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
TYPICAL CHARACTERISTICS
SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
SUPPLY VOLTAGE
8
8
AV = 1
VIPP = 1 V
RL = 10 k
CL = 20 pF
TA = 25C
See Figure 1
5
4
3
0
4
6
8
10
12
VDD Supply Voltage V
14
VDD = 10 V
VIPP = 1 V
VDD = 10 V
VIPP = 5.5 V
VDD = 5 V
VIPP = 1 V
VDD = 5 V
VIPP = 2.5 V
0
75
16
50
AV = 1
VIPP = 1 V
RL = 10 k
CL = 20 pF
1.4
VDD = 10 V
1.2
VDD = 5 V
1.0
0.9
0.8
0.7
0.6
0.5
75
50
25
25
125
1.5
1.1
25
0
25
50
75 100
TA Free-Air Temperature C
Figure 27
Figure 26
1.3
AV = 1
RL = 10 k
CL = 20 pF
See Figure 1
6
SR Slew Rate V/ s
SR Slew Rate V/ s
50
75
100
125
10
VDD = 10 V
9
8
TA = 125C
TA = 25C
TA = 55C
7
6
5
VDD = 5 V
4
3
RL = 10 k
See Figure 1
2
1
0
10
TA Free-Air Temperature C
100
1000
10000
f Frequency kHz
Figure 29
Figure 28
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
25
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
2.5
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
2.5
3.0
2.0
1.5
1.0
75
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 3
2.0
1.5
1.0
50
25
25
50
75
100
125
10
12
14
TA Free-Air Temperature C
Figure 31
Figure 30
VDD = 5 V
RL = 10 k
TA = 25C
10 5
10 4
30
AVD
10 3
60
10 2
90
Phase Shift
101
120
150
0.1
10
Phase Shift
AVD
AVD Large-Signal Differential
Voltage Amplification
10 6
180
100
1k
10 k
100 k
1M
10 M
f Frequency Hz
Figure 32
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
26
16
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
RL = 10 k
TA = 25C
10 5
10 4
30
Phase Shift
AVD
AVD Large-Signal Differential
Voltage Amplification
10 6
AVD
10 3
60
10 2
90
Phase Shift
101
120
150
0.1
100
10
1k
10 k
100 k
1M
180
10 M
f Frequency Hz
Figure 33
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
53
50
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
52
48
m
m Phase Margin
m
m Phase Margin
51
50
49
48
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 3
47
46
10
12
14
44
42
45
0
46
16
40
75
50
25
25
50
75
100
125
TA Free-Air Temperature C
Figure 34
Figure 35
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
27
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
CAPACITIVE LOAD
50
VDD = 5 V
VI = 10 mV
TA = 25C
See Figure 3
m
m Phase Margin
45
40
35
30
25
VN
V n Equivalent Input Noise Voltage nV/ Hz
300
200
100
0
0
10
20
30
40
50
60
70
80
90 100
CL Capacitive Load pF
100
f Frequency Hz
Figure 36
28
10
Figure 37
1000
APPLICATION INFORMATION
single-supply operation
While the TLC272 and TLC277 perform well using dual power supplies (also called balanced or split supplies),
the design is optimized for single-supply operation. This design includes an input common-mode voltage range
that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage
range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for
TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC272 and TLC277 permits the use of very large resistive values to implement
the voltage divider, thus minimizing power consumption.
The TLC272 and TLC277 work well in conjunction with digital logic; however, when powering both linear devices
and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
R1
R2
VI
VO
+
VREF
R3
REF
C
0.01 F
+ V
+ (V
R3
DD R1 ) R3
REF
* V ) R4 ) V
REF
I R2
OUT
Logic
Logic
Logic
Power
Supply
+
(a) COMMON SUPPLY RAILS
Logic
Logic
Logic
OUT
Power
Supply
29
APPLICATION INFORMATION
input characteristics
The TLC272 and TLC277 are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially
in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD 1 V at TA = 25C and at VDD 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC272 and TLC277 very
good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift
in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 V/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC272 and
TLC277 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good
practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC272 and TLC277 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 k, since bipolar devices exhibit
greater noise currents.
OUT
+
(b) INVERTING AMPLIFIER
OUT
VI
VI
VI
OUT
output characteristics
The output stage of the TLC272 and TLC277 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC272 and TLC277 are measured using a 20-pF load. The devices can
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
30
APPLICATION INFORMATION
output characteristics (continued)
2.5 V
VO
+
VI
TA = 25C
f = 1 kHz
VIPP = 1 V
CL
2.5 V
(d) TEST CIRCUIT
31
APPLICATION INFORMATION
output characteristics (continued)
VDD
VI
IP
RP
VO
IF
R2
R1
IL
RL
VO
VDD VO
IF + IL + IP
Rp =
feedback
Operational amplifier circuits almost always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC272 and
TLC277 inputs and outputs were designed to withstand 100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 F typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
32
APPLICATION INFORMATION
10 k
10 k
0.016 F
0.016 F
10 k
10 k
5V
10 k
1/2
TLC272
1/2
TLC272
VI
1/2
TLC272
Low Pass
+
High Pass
5 k
Band Pass
R = 5 k(3/d-1) (see Note A)
+
1/2
TLC272
H.P.
5082-2835
+
1/2
TLC272
0.5 F
Mylar
N.O.
Reset
VO
100 k
33
APPLICATION INFORMATION
VI
(see Note A)
100 k
1.2 k
0.47 F
4.7 k
TL431
20 k
1/2
TLC272
0.1 F
1 k
TIP31
15
TIS193
250 F,
25 V
VO
(see Note B)
10 k
47 k
0.01 F
110
22 k
NOTES: A. VI = 3.5 to 15 V
B. VO = 2 V, 0 to 1 A
9V
10 k
0.1 F
9V
C
100 k
1/2
TLC272
R2
10 k
1/2
TLC272
VO (see Note B)
+
100 k
fO +
R1
47 k
R3
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
34
[ ]
1
R1
4C(R2) R3
APPLICATION INFORMATION
5V
VI
10 k
1/2
TLC277
100 k
1/2
TLC277
VO
+
10 k
10 k
1/2
TLC277
95 k
R1,10 k
(see Note A)
VI +
5 V
NOTE B: CMRR adjustment must be noninductive.
5V
R
10 M
R
10 M
1/2
TLC272
VO
VI
2C
540 pF
f NOTCH +
R/2
5 M
C
270 pF
1
2pRC
C
270 pF
35
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-89494022A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC272ACD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
TLC272ACP
TLC272ACPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
TLC272ACP
TLC272AID
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
-40 to 85
TLC272AIP
TLC272AIPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
-40 to 85
TLC272AIP
TLC272BCD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
TLC272BCDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
TLC272BCDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
TLC272BCDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
Addendum-Page 1
Samples
www.ti.com
10-Jun-2014
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC272BCP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
TLC272BCP
TLC272BCPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
TLC272BCP
TLC272BID
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
-40 to 85
TLC272BIP
TLC272CD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
TLC272CP
TLC272CPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
TLC272CP
TLC272CPSR
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272
TLC272CPSRG4
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272
TLC272CPW
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
TLC272CPWG4
ACTIVE
TSSOP
PW
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
TLC272CPWLE
OBSOLETE
TSSOP
PW
TBD
Call TI
Call TI
0 to 70
Addendum-Page 2
Samples
www.ti.com
10-Jun-2014
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC272CPWR
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
TLC272CPWRG4
ACTIVE
TSSOP
PW
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
TLC272ID
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
-40 to 85
TLC272IP
TLC272IPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
-40 to 85
TLC272IP
TLC272MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC272MJG
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
-55 to 125
TLC272MJGB
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
-55 to 125
TLC272P-M
PREVIEW
PDIP
TBD
Call TI
Call TI
TLC277CD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC277CP
TLC277CPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC277CP
TLC277CPSR
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P277
TLC277ID
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
Addendum-Page 3
Samples
www.ti.com
10-Jun-2014
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TLC277IDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
TLC277IDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
TLC277IDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
TLC277IP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC277IP
TLC277IPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC277IP
TLC277MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC277MJG
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
-55 to 125
TLC277MJGB
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
-55 to 125
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 4
Samples
www.ti.com
10-Jun-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
14-May-2016
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC272ACDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272AIDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272BCDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272BCDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272BIDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272BIDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272CDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272CPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLC272IDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC277CDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC277CPSR
SO
PS
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TLC277IDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC277IDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
14-May-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC272ACDR
SOIC
2500
340.5
338.1
20.6
TLC272AIDR
SOIC
2500
340.5
338.1
20.6
TLC272BCDR
SOIC
2500
367.0
367.0
38.0
TLC272BCDR
SOIC
2500
340.5
338.1
20.6
TLC272BIDR
SOIC
2500
340.5
338.1
20.6
TLC272BIDR
SOIC
2500
367.0
367.0
38.0
TLC272CDR
SOIC
2500
340.5
338.1
20.6
TLC272CPWR
TSSOP
PW
2000
367.0
367.0
35.0
TLC272IDR
SOIC
2500
340.5
338.1
20.6
TLC277CDR
SOIC
2500
340.5
338.1
20.6
TLC277CPSR
SO
PS
2000
367.0
367.0
38.0
TLC277IDR
SOIC
2500
340.5
338.1
20.6
TLC277IDR
SOIC
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
0.280 (7,11)
0.245 (6,22)
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.023 (0,58)
0.015 (0,38)
015
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
PACKAGE OUTLINE
PW0008A
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
0.1 C
6X 0.65
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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PW0008A
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
4
(5.8)
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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PW0008A
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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