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1. List a pair of design metrics that may compete with one another, providing an
intuitive explanation of the reason behind the competition. [16]
4. Explain the need of special architecture for pipelining and parallelism. [16]
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7. Explain the parallel evolution of compilation and synthesis with the co-design lad-
der. [16]
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1. List a pair of design metrics that may compete with one another, providing an
intuitive explanation of the reason behind the competition. [16]
2. Design a 3-bit counter that counts the following sequence: 1,2,4,5,7,1,2,?.. start
from a state diagram, draw the state table, minimize the logic, and draw the final
circuit. [16]
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7. Give overview of the various levels of synthesis with Gazki Y-chart. [16]
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5. Explain the state chart language with elevator controller example. [16]
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variables with an example. [8+8]
7. Explain the parallel evolution of compilation and synthesis with the co-design lad-
der. [16]
8. (a) Explain the three types of cores such as hard, soft and firm cores.
(b) Show the correspondence of the three types of cores with Gazki’s Y-chart.
[8+8]
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2. (a) Build a 2-input AND gate using a minimum number of CMOS transistors.
Explain with truth table.
(b) Build a 2-input OR gate using a minimum number of CMOS transistors.
Explain with truth table. [8+8]
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7. (a) Explain in detail about the combinational logic synthesis approach?
(b) Explain in detail about FSM synthesis. [8+8]
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