&
microcontroller
INTRODUCTION
Memory
Unit
Input
Devices
Control
Unit
Output
Devices
ALU
MICROPROCESSOR
The microprocessor is a multipurpose, programmable, clockdriven
Semiconductor device consisting of electronics logic circuit manufactured
By using either LSI or VLSI technique.
. It is capable of performing various computing functions & making decision
To change the sequence of program execution.
These are operations that the microprocessor starts itself. These are usually one
of the following operations:
Memory Read : Reads data from memory
Memory Write : Writes data into the memory.
Accepts data from I/P devices
Sends data to O/P devices.
Data Processing
Arithmetic operations
Logical operations
BLOCK DIAGRAM OF MICROPROCESSOR
Processor System Architecture
Control Logic
Registers, etc
Memory
Address Bus
Data Bus
Control Bus
Bus: A shared group of wires used for communicating signals among devices
Address bus: the device and the location within the
device that is being
accessed.
Data bus: the data value being communicated
Address Bus
Data Bus
Control Bus
Registers
Accumulator
Flag Bits
based on
AC
C
Carry
Sign
Zero
Parity
Auxiliary Carry
X - Unspecified
Program Counter: This is a 16 bit register that deals with the forth
operation of the list i.e. sequencing the execution of instructions. This
register is a memory pointer. Memory locations have 16 bit address. The
function of the program counter is to point the memory address from
which the next byte is to be fetched. When one byte is being fetched the
contents of the program counter is increased by 1. to point the next
memory location.
Stack Pointer: The stack pointer is also a 16 bit register used as memory
pointer. It points to a memory location in R/W memory, called the stack.
The beginning of the stack is defined by loading a 16 bit address in the
stack pointer.
X1
X2
RE O
SE S
U
T
T
O
SI
D
TRA
P
RST
RST
7.5
RST
6.5
5.5
INT
_____
R
INTA
A
AD0
D
A1
D2
A
D3
A
D
A4
D
A5
D
A6
D
V7
SS
1
2
3
4
5
6
7
8
9
10
11
12
8085
A
40
39
38
37
36
35
34
33
32
31
14
15
16
17
18
19
30
29
28
27
26
25
24
23
22
20
21
13
V
cc
HO
D
LD
HLDA
M
CLK
______________
( OUT) A
___
READY RESET
__
S1
IO / M
IN
___
R
___
D
W
A
R
L
S
E
0A
15
A14
A13
A12
A11
A10
A9
A8
The steps which MP8085 takes to fetches machine codes from the memory
can be understood with the help of the command MOV C,A (4F) stored at
memory location 2005H :
1. The program places the 16 bit address on the address bus. At time T1 the
high order address 20H is placed on the address line A15-A8, the low
order memory address 05H is placed on the data bus AD7-AD0 and the
address latch signal goes high. Similarly the status signal IO/M goes low,
indicating that this is memory related operation.
2. The control unit sends the control signal RD to enable the memory chip.
This signal is sent out during the clock period T2, thus enabling the
memory chip. The RD signal is active during two clock periods.
3. The byte from the memory location is placed on the data bus. When the
memory is enabled the instruction byte (4F) is placed on the bus AD7AD0 and transferred to the microprocessor. The RD signal goes high,
the bus go into high impedance.
4. The byte is placed in the instruction decoder of the microprocessor, and
the task is carried out. The machine code 4F is decoded by the instruction
decoder and the contents of the accumulator are copied into the register
C. This task is performed during the period T4
TIMING DIAGRAM
T - State
One sub-division of the operation performed in one clock period is called
one T-state.
Machine Cycle
The time required to complete one operation of accessing either memory
or i/o is called one machine cycle. The machine cycle may consist of 3 to 6
T-state.
Instruction Cycle
The time required to complete the execution of an instruction. An
instruction cycle may consist of 1 to 5 machine cycles.
TIMING DIAGRAM(For MOV A,B)
Another
Example :- In MP8085 we have two machine codes 3EH ( MVI A, data) and 32H
are stored at memory location 2000H and 2001H respectively. Illustrate the bus
timing . Calculate the required to execute the Opcode Fetch and Memory Read
cycles and the entire instruction cycle if the clock frequency is 1.2 MHzs.
Ans :- This instruction consists of two bytes; the first op-code and the second is
the data byte. The MP reads these bytes from the memory and thus requires at
least two machine cycles. The first machine cycle is the Opcode fetch and the
second machine cycle is the memory read .
1. First machine cycle M1:1. At T1 microprocessor places the memory address 2000H from the PC on
the address bus. 20H on the A15-A8, and 00H on the bus AD7-AD0. The
ALE signal goes high during T1. which is used to latch the low order
address 00H to AD7-AD0. The status signals are S1 = 1, S0=1
2. At T2 the MP asserts the RD control signal, which enables the memory,
and memory places the byte 3EH from location 2000H on the data bus.
3. During T3 the MP places the opcode in the instruction register and
disables the RD signal . The fetch cycle is completed in state T3
4. During T4 the instruction is decoded
2. Second machine cycle M2:1. At T1 microprocessor places the memory address 2001H from the PC on
the address bus. 20H on the A15-A8, and 01H on the bus AD7-AD0. The
ALE signal goes high during T1. which is used to latch the low order
address 00H to AD7-AD0. The status signals are S1 = 1, S0=0
2. At T2 the MP activates the data bus as the input bus, memory places the
data byte 32H on the data bus.
3. During T3 the MP reads and store the byte in accumulator.
The execution time
Clock frequency f = 2 Mz
T- state = Clock Period = 1/f = 0.5 s
Execution time for fetch cycle = 4 X .5 = 2 s
Execution time for Memory Read = 3 X .5 = 1.5 s
Execution time for the instruction = 3.5 s
Example 2 :- In MP8085 explain the machine cycle for the instruction STA
2065 (32H,65,20). The machine codes are stored at the memory locations
2010H, 2011H, 2012H.
Ans :- This instruction consists of three bytes; the first op-code and the
second and the third are the address of the memory location. This
instruction stores the contents of the accumulator in the memory location
2065H. It consists of 4 machine cycles.
1. First machine cycle M1:In the first machine cycle the MP places the address 2010 on the address bus and
fetches the opcode 32h. It requires 4T states.
1. Second machine cycle M2:In the second machine cycle the memory is read. The processor places the
address 2011 and gets the low order byte 65H. It requires 3T states.
1. Third machine cycle M3:The third machine cycle is also the Memory Read cycle. The processor gets the
high order byte 20H from the memory location 2012. It requires 3 T states
1. Forth machine cycle M4 :The last machine cycle is the memory write . The MP places the address of
2065H on the address bus, identifies the operation as Memory Write ( S1=0,
S0=0 ). It places the contents of the accumulator on the data bus AD7-AD0 and
asserts the WR signal. During the last T state the contents of the data bus are
placed in memory location 2065H. It requires 3T states.
1.
2.
3.
4.
5.
Direct Addressing
Register Addressing
Register Indirect Addressing
Immediate Addressing.
Implicit Addressing