Program For 2016 29th IEEE International System-On-Chip Conference (SOCC) (SOCC 2016)

Program for 2016 29th IEEE International System-on-Chip Conference ...
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Program for 2016 29th IEEE International System-on-Chip Conference (SOCC)

Time
Courtyard
Foyer
East
Federal
Municipal
North
Superior
Visions
(28th
Floor)
Vista
Tuesday, September 6
09:00-10:30
Tutorial 1A:
Design
Challenges for
the Internet of
Things
Tutorial 1B:
Transistors:
Past, Present
and Future
10:30-10:45
10:45-12:15
Coffee Break
Tutorial 2B:
Coupling
and
Spurious
Mitigation in
Wideband
RF
Transceiver
SOCs
Tutorial 2A: 3D
Integration Challenges and
Advantages
12:15-14:00
14:00-15:30
Lunch
Tutorial 3B:
The Design
Challenges
for
Self-Powered
Wireless
Wearable
ECG Sensor
SoC
Tutorial 3A:
Bringing Cores
Closer
Together: The
Wireless
Revolution in
On-Chip
Comm unication
15:30-15:45
15:45-17:15
Coffee Break
Tutorial 4B:
ADC Design
- From
System
Architecture
to Transistor
Level Design
Tutorial 4A:
Supply Voltage
Noise and
Mitigation for
Real World
SoCs
Wednesday, September 7
08:00-08:15
Opening
Remarks
08:15-08:30
Technical
Program
Overview
08:30-09:30
Opening
Keynote
09:30-09:45
09:45-10:45
Plenary I
10:50-12:05
Coffee Break
RF, Analog
Design I
Best Paper
Award I
SoC Design
Methods and
Algorithms I
Industry
Forum : Low
Power Circuits
and System
Design
Techniques for
IoT Part I
12:05-13:30
13:30-15:10
15:10-15:30
1 of 13
Design Track
Lunch
Special
Session:
Emerging
Trends in SoC
Testing
Coffee Break
11-Aug-16 11:14 PM
2 of 13
Emerging
and
Evolutionary
Design
Algorithms
15:30-17:10
17:10-19:00
Industry
Forum : Low
Power Circuits
and System
Design
Techniques for
IoT Part II
Application
Specific SoC
Designs
Poster Session
& Reception
Thursday, September 8
08:30-09:30
09:30-10:30
10:30-10:45
Keynote II
Plenary II
Coffee Break
Industry
Forum : Data
Analytics and
Security in IoT
Part I
10:45-12:00
12:00-13:30
13:30-15:10
Best Paper
Award II
Lunch
Advanced
SoC
Com ponents
15:10-15:30
Industry
Forum : Data
Analytics and
Security in IoT
Part II
RF, Analog
Design II
Coffee Break
Panel
Discussion
15:30-17:00
Cocktail
Reception
17:30-18:00
Conference
Banquet
18:00-21:00
Friday, September 9
08:30-10:10
SoC Design
Methods and
Algorithms
II
10:10-10:30
10:30-12:10
Intel Training
Workshop Part
I
Special
Session:
Emerging
Stochastic
Computing
and
Neurom orphic
Computing:
Arithm etic,
Algorithm,
and
Applications
Coffee Break
Low Power
Design
12:10-13:00
13:00-17:00
Intel Training
Workshop Part
II
Special
Session:
Security and
Validation in
Mobile,
Embedded,
and IoT
Systems
Lunch
Post Conference Event
Tuesday, September 6
Tuesday, September 6, 09:00 - 10:30
Tutorial 1A: Design Challenges for the Internet of Things
11-Aug-16 11:14 PM
3 of 13
Danielle Griffith, Texas Instruments, Inc., USA

Room: East
Tutorial 1B: Transistors: Past, Present and Future
Gururaj Shamanna, Qualcomm India Pvt Limited, India
Room: North

Coffee Break

Tutorial 2A: 3D Integration - Challenges and Advantages
Malgorzata Chrzanowska-Jeske, Portland State University, USA
Room: East
Tutorial 2B: Coupling and Spurious Mitigation in Wideband RF Transceiver SOCs
Siraj Akhtar, Texas Instruments, Inc., USA
Room: North

Lunch

Tutorial 3A: Bringing Cores Closer Together: The Wireless Revolution in On-Chip Communication
Partha Pande, Washington State University, USA
Room: East
Tutorial 3B: The Design Challenges for Self-Powered Wireless Wearable ECG Sensor SoC
Yong Lian, National University of Singapore, Singapore
Room: North

Coffee Break

Tutorial 4A: Supply Voltage Noise and Mitigation for Real World SoCs
Visvesh Sathe, University of Washington, USA
Room: East
Tutorial 4B: ADC Design - From System Architecture to Transistor Level Design
Bhibhudatta Sahoo University of Illinois, Urbana-Champaign, USA and Vishal Saxena, University of
Idaho, USA
Room: North
11-Aug-16 11:14 PM
Wednesday, September 7
Wednesday, September 7, 08:00 - 08:15
Opening Remarks
Danella Zhao, SOCC 2016 Conference Chair
Room: Municipal
Chair: Danella Zhao (Old Dominion University, USA)

Technical Program Overview
Karan Bhatia, SOCC 2016 Technical Program Chair
Room: Municipal
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)

Opening Keynote
Crashing Drones and Hijacked Cameras: CyberTrust Meets CyberPhysical
Jeannette M. Wing, Corporate Vice President, Microsoft Research, USA
Room: Municipal
Cyber-physical systems are engineered systems that require tight conjoining of and coordination between the computational (discrete)
and the physical (continuous). Cyber-physical systems are rapidly penetrating every aspect of our lives, with potential impact on
sectors critical to national security and competitiveness, including aerospace, automotive, chemical production, civil infrastructure,
energy, finance, healthcare, manufacturing, materials, and transportation. As these systems fulfill the promise of the Internet of
Things, smart cities, household robots, and personalized medicine, we need to ensure they are trustworthy: reliable, secure, and
privacy-preserving. This talk will look at cyber-physical systems from the lens of trustworthy computing. Throughout my talk, I will raise
research challenges for how to make cyber-physical systems trustworthy.

Coffee Break

Plenary I
The Internet of Important Things
Edward A. Lee, Robert S. Pepper Distinguished Professor, UC Berkeley, USA
Room: Municipal
Cyber-physical systems are integrations of computation, communication networks, and physical dynamics. Applications include
manufacturing, transportation, energy production and distribution, biomedical, smart buildings, and military systems, to name a few.
Increasingly, today, such systems leverage Internet technology, despite a significant mismatch in technical objectives. A major challenge
today is to make this technology reliable, predictable, and controllable enough for "important" things, such as safety-critical and
mission-critical systems. In this talk, I will analyze how emerging technologies can translate into better models and better engineering
methods for this evolving Internet of important things. I will particularly focus on embedded processor design that can significantly
improve determinism and reduce power consumption for embedded software.
4 of 13
11-Aug-16 11:14 PM
Best Paper Award I

Room: Municipal
10:50 Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive
Body Biasing
Shu Hokimoto, Tohru Ishihara and Hidetoshi Onodera (Kyoto University, Japan)
11:15 Digital LDO Modeling for Early Design Space Exploration
Stefan Leitner (Southern Illinois University Carbondale); Paul West, Chao Lu and Haibo Wang
(Southern Illinois University Carbondale, USA)
11:40 A Digital-circuit-based Evolutionary-computation Algorithm for Time-interleaved ADC
Background Calibration
Dadian Zhou (Texas A&M University, USA); Claudio Talarico (Gonzaga University, USA); Jose SilvaMartinez (Texas A&M University, USA)
Design Track
Room: Superior
10:50 Design Challenges and Practical Solutions for a Mobile SoC in the 10nm FinFET Process
Hyosig Won, Hyounsoo Park, Kyongjun Noh, Myungsoo Jang, Dayeon Cho, Seongmin Ryu and
Minkook Kim (Samsung Electronics, Korea)
11:05 Design Challenges in a Low-Power Management Unit for a GNSS Receiver System in
28nm CMOS
Filippo Maria Neri, Thomas Brauner and Eric De Mey (U-blox AG); Christian Schippel
(Globalfoundries, Germany)
11:20 Intelligent Low Power Wake-Up Protocol for Multi-Regulator Power Management
Architectures
Sunny Gupta (Freescale Semiconductor India (NXP), India); Kumar Abhishek (NXP, USA); Nitin
Pant, Garima Sharda and Gautham Shivender Harinarayan (Freescale Semiconductor India (NXP),
India)
11:35 Efficient Circuit Architecture and FPGA Implementation for LTE Single Carrier FDMA DFT
J Greg Nash (Centar LLC, USA)
11:50 Energy Efficient Design of Ultra-Lightweight Hardware Security Circuits for IoT
Applications
Vikram Suresh (Intel Corporation); Sudhir Satpathy, Sanu Mathew and Ram Krishnamurthy (Intel
Corporation, USA)
RF, Analog Design I
Room: Federal
Chair: Andrew Marshall (University of Texas at Dallas, USA)
10:50 Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural
Sensing Applications
Jr-Ming Chen (Nation Chiao Tung University, Taiwan); Po-Tsang Huang (National Chiao Tung
University); Shang-Lin Wu (Nation Chiao Tung University, Taiwan); Wei Hwang and Ching-Te
Chuang (National Chiao Tung University, Taiwan)
11:15 A 12 Bit Split-Array Switched Capacitor Power Amplifier in 130nm CMOS
Zhidong Bai, Ali Azam, Dallas Johnson, Wen Yuan and Jeffrey Walling (University of Utah, USA)
11:40 Low-Jitter All-Digital Phase-Locked Loop with Novel PFD and High Resolution TDC & DCO
Xiaoying Deng, Yanyan Mo, Xin Lin and Mingcheng Zhu (Shenzhen University, P.R. China)
5 of 13
11-Aug-16 11:14 PM

Lunch

Industry Forum: Low Power Circuits and System Design Techniques for IoT Part I
Room: Municipal
Chairs: Ram Krishnamurthy (Intel Corporation, USA), Magdy Bayoumi (University of Louisiana, USA)
SoC Design Methods and Algorithms I
Room: Federal
Chair: Chris Ryan (Maxim Integrated Inc., USA)
13:30 Statistical Design Attribute Identification for FinFET Outlier and Silicon-to-SPICE Gap
Hyosig Won and Katsuhiro Shimazu (Samsung Electronics, Korea)
13:55 Intra-chip Traffic Generation Under Autoregressive Models Based on Time Series
Obtained by TLM Simulation
Jose E Bueno (University of Sao Paulo, Brazil); Jorge Gonzalez (University of Campinas, Brazil);
Wang Chau (University of Sao Paulo)
14:20 A Method to Estimate Effectiveness of Weak Bit Test: Comparison of Weak pMOS and WL
Boost Based Test - 28nm FDSOI Implementation
Nidhi Batra, Shashwat Kaushik and Anil Gundu Kumar (IIIT Delhi, India); Mohammad Hashmi (IIIT
Delhi); Anuj Grover (ST Microelectronics, India); Gangaikondan Visweswaran (IIIT Delhi, India)
14:45 CATBR-Congestion Aware Traffic Bridging Routing Among Hierarchical Networks-on-Chip
Mingmin Bai (University of Louisiana at Lafayette, USA); Danella Zhao (Old Dominion University,
USA); Hongyi Wu (University of Louisiana at Lafayette, USA)
Special Session: Emerging Trends in SoC Testing
Room: Superior
Chair: Yu Huang (Mentor Graphics, USA)
13:30 EDT Dynamic Bandwidth Management in SoC Testing
Yu Huang (Mentor Graphics, USA)
13:55 Toward More Efficient Scan Data Bandwidth Utilization on Modern SOCs
Grady Giles (AMD); GuoLiang Li (AMD, P.R. China); Jeff Rearick, John Schulze, James Wingfield,
Tim Wood and Yan Dong (AMD, USA)
14:20 In-Field System-Health Monitoring Based on IEEE 1687
Farrokh Ghani Zadegan, Dimitar Nikolov and Erik Larsson (Lund University, Sweden)
14:45 High Bandwidth Packetized DFT Fabric for Servers and SoCs
Glenn Colon-Bonet (Intel Corporation, USA)

Coffee Break

Application Specific SoC Designs
Room: Superior
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)
6 of 13
11-Aug-16 11:14 PM
15:30 Novel Lightweight FF-APUF Design for FPGA

Chongyan Gu (Queen's University Belfast, United Kingdom); Yijun Cui (Nanjing University of
Aeronautics and Astronautics, P.R. China); Neil Hanley and Maire O'Neill (Queen's University
Belfast, United Kingdom)
15:55 Efficient VLSI Architecture for SAO Decoding in 4K Ultra-HD HEVC Video Codec
Mihir N Mody, Niraj Nandan and Hetul Sanghvi (Texas Instruments, Inc.)
16:20 A Flexible Router Architecture for Three-Dimensional Network-on-Chips
Mostafa Khamis (Mentor Graphics Egypt, Egypt); Mostafa Said Abdelrehim (Sun Yat-sen UniversityCarnegie Mellon University (SYSU-CMU) Joint Institute of Engineering, Guangzhou, China); Ahmed
Shalaby (Egypt Japan University for Science and Technology, Egypt)
16:45 Single-ended D Flip-Flop with Implicit Scan Mux for High Performance Mobile AP
Min Su Kim, Chung-Hee Kim, Yong-geol Kim, Ah-Reum Kim, Jikyum Kim, Juhyun Kang, Daeseong
Lee, Changjun Choi, Ilsuk Suh, Jungyul Pyo, Youngmin Shin and Jae Cheol Son (Samsung
Electronics Inc., Korea)
Emerging and Evolutionary Design Algorithms
Room: Federal
15:30 Multi-Objective Sample Preparation Algorithm for Microfluidic Biochips Supporting
Various Mixing Models
Yung-Chun Lei (National Chiao Tung University, Taiwan); Tung-Hsuan Lin (MediaTek Inc., Taiwan);
Juinn-Dar Huang (National Chiao Tung University, Taiwan)
15:55 A Multiplication Reduction Technique with Near-Zero Approximation for Embedded
Learning in IoT Devices
Yuxiang Huan (Fudan University); Yifan Qin (Fudan University, P.R. China); Yantian You (KTH-The
Royal Institute of Technology); Lirong Zheng (Fudan University, P.R. China); Zhuo Zou (KTH-The
Royal Institute of Technology, Sweden)
16:20 Feature Study on a Programmable Network Traffic Classifier
Keissy Guerra Perez (Queen University of Belfast, United Kingdom); Xin Yang and Sandra ScottHayward (Queen's University Belfast, United Kingdom); Sakir Sezer (Queen's University Belfast &
CTO Titan IC, United Kingdom)
16:45 Design and ASIC Acceleration of Cortical Algorithm for Text Recognition
Sumon Dey and Paul Franzon (North Carolina State University, USA)
Industry Forum: Low Power Circuits and System Design Techniques for IoT Part II
Room: Municipal
Chairs: Ram Krishnamurthy (Intel Corporation, USA), Magdy Bayoumi (University of Louisiana, USA)

Poster Session & Reception
Room: Courtyard Foyer
A 200 MS/s 8-bit Time-Based Analog-to-Digital Converter with Inherit Sample and Hold
Ali H. Hassan (Cairo University); Mohammed Ismail (Cairo University, Egypt); Yehea Ismail
(American University in Cairo, USA); Hassan Mostafa (University of Toronto, Canada)
Dynamically Reconfigurable Architecture for Fault-tolerant 2D Networks-on-Chip
Poona Bahrebar and Dirk Stroobandt (Ghent University, Belgium)
A 0.4V 320Mb/s 28.7W 1024-bit Configurable Multiplier for Subthreshold SOC Encryption
Weiwei Shi (Shenzhen University & The Chinese University of Hong Kong, P.R. China); Chiu-sing
Oliver Choy (The Chinese University of Hong Kong)
7 of 13
11-Aug-16 11:14 PM
8 of 13
Low Voltage Flash Memory Design Based on Floating Gate SOFFET

Emeshaw Ashenafi (University of Missouri-Kansas City, USA); Azzedin Es-Sakhi (University of
Missouri Kansas City, USA); Masud H Chowdhury (University of Illinois at Chicago, USA)
Hardware Implementation of Hierarchical Temporal Memory Algorithm
Weifu Li and Paul Franzon (North Carolina State University, USA)
An Early Global Routing Framework for Uniform Wire Distribution in SoCs
Bapi Kar (Indian Institute of Technology, Kharagpur); Susmita Sur-Kolay (ISI Kolkata, India);
Chittaranjan Mandal (Indian Institute of Technology, Kharagpur, India)
SAMi: Self-Aware Migration Approach for Congestion Reduction in NoC-based MCSoC
Amin Rezaei (University of Louisiana at Lafayette, USA); Masoud Daneshtalab (KTH Royal Institute
of Technology, Sweden); Danella Zhao (Old Dominion University, USA); Mehdi Modarressi
(University of Tehran, Iran)
Modeling and Optimization of the Bond-Wire Interface in a Hybrid CMOS-Photonic
Traveling-Wave MZM Transmitter
Kehan Zhu, Vishal Saxena and Xinyu Wu (Boise State University, USA)
A Jitter Cancellation Circuit for High Speed I/O Interfaces
Anupjyoti Deka and Mahalingam Nagarajan (Intel, India)
A CMOS Analog Front-End for Driving a High-Speed SAR ADC in Low-Power Ultrasound Imaging
Systems
Taehoon Kim, Han Yang, Sangmin Shin, Hyongmin Lee and Suhwan Kim (Seoul National University,
Korea)
Behavioral Modeling of Drain Current of an Avalanche ISFET Near Breakdown Voltage
Mohammad Uzzal and Payman Zarkesh-Ha (University of New Mexico, USA); Paul Szauter
(ElectroSeq); Jeremy Edwards (University of New Mexico)
A Novel Power Reduction Technique Using Wire Multiplexing
Mostafa Said Abdelrehim (Sun Yat-sen University-Carnegie Mellon University (SYSU-CMU) Joint
Institute of Engineering, Guangzhou, China); Hossam Hassan and HyungWon Kim (Chungbuk
National University & College of Electrical and Computer Engineering, Korea)
An Ultra-Low Power Voltage-to-Time Converter (VTC) Circuit for Low Power and Low Speed
Applications
Hassan Mostafa (University of Toronto, Canada); Ali H. Hassan (Cairo University); Tawfik Ismail
(NILES, Cairo University, Egypt); Salam Gabran (University of Waterloo, Canada)
Automated Full Chip SPICE Simulations with Self-Checking Assertions for Last Mile Verification
& First Pass Silicon of Mixed Signal SoCs
Gautham Shivender Harinarayan, Manmohan Rana, Nitin Pant, Manish Bansal, Sarthak Sharma and
Nishant Kaundal (Freescale Semiconductor India (NXP), India)
Analytical Noise Model for Avalanche ISFET Sensor Suitable for Next Generation Sequencing
Mohammad Uzzal and Payman Zarkesh-Ha (University of New Mexico, USA); Paul Szauter
(ElectroSeq); Jeremy Edwards (University of New Mexico)
Rotator-Based Multiplexer Network Synthesis for Field-Data Extractors
Koki Ito and Kazushi Kawamura (Waseda University, Japan); Yutaka Tamiya (Fujitsu Laboratories
Ltd., Japan); Masao Yanagisawa and Nozomu Togawa (Waseda University, Japan)
A Comparator Timing Assisted SAR ADC Technique with Reduced Conversion Cycles
Abhilash Karnatakam Nagabhushana (Southern Illinois University Carbondale); Haibo Wang
(Southern Illinois University Carbondale, USA)
Efficient Implementation of the AES Algorithm for Security Applications
Shady Soliman, Mohamed Abdel Ghany and Baher Magdy (GUC, Egypt)
High-Voltage Low-Power Startup Backup Battery Switch Using Low Voltage Devices in 28nm
CMOS
Filippo Maria Neri (U-blox AG); Craig Keogh (U-blox AG, Switzerland); Thomas Brauner and Eric De
11-Aug-16 11:14 PM
Mey (U-blox AG); Christian Schippel (Globalfoundries, Germany)
Thursday, September 8
Thursday, September 8, 08:30 - 09:30
Keynote II
SoX at the Edge: the Heterogeneous, Highly Integrated IoT Systems of the future
Mircea Stan, Professor, University of Virginia, USA
Room: Municipal
Rumors of Moore's Law demise have been greatly exaggerated! While transistors are not getting simultaneously smaller, faster and
lower power every couple of years like for the past several decades, inexorable forces to cram more devices together are still running
strong, except that they are now pushing upwards in the third dimension. Heterogeneity, monolithic vs. TSV-based scaling for 3D, and
closing the energy loop (cooling and power delivery) will punctuate this talk as it explores the challenges and opportunities that IoT
systems of the future face as they move away from planar Systems-on-Chip (SoC) to becoming three dimensional Systemson-Anything (SoX, e.g. Systems-on-Package, Systems-on-Interposer, etc.)

Plenary II
Energy-Efficient and Ultra Low Voltage Design pf Sub-14nm SoCs and Microprocessors: Challenges and
Opportunities
Ram Krishnamurthy, Senior Principal Engineer, Intel Labs, USA
Room: Municipal

Coffee Break

Best Paper Award II
Room: Superior
10:45 Design of a Power-Efficient ARM Processor with a Timing-Error Detection and Correction
Mechanism
Sao-Jie Chen, Grace Liu, Hsin-Ping Yang and Cheng-Hao Luo (National Taiwan University, Taiwan);
Wen-Mei Hwu (University of Illinois at Urbana-Champaign, USA)
11:10 Compressive Image Sensor Technique with Sparse Measurement Matrix
Stefan Leitner (Southern Illinois University Carbondale); Haibo Wang (Southern Illinois University
Carbondale, USA); Spyros Tragoudas (Southern Illinois University, Carbondale, USA)
11:35 Performance Optimization and Power Efficiency in 3D IC with Buffer Insertion Scheme
Mohammad Ahmed, Sucheta Mohapatra and Malgorzata Chrzanowska-Jeske (Portland State
University, USA)
Industry Forum: Data Analytics and Security in IoT Part I
Room: Municipal
Chairs: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom), Ravi Mukkamala (Old
9 of 13
11-Aug-16 11:14 PM
10 of 13
Dominion University, USA)

Lunch

Advanced SoC Components
Room: Federal
Chair: Andrew Marshall (University of Texas at Dallas, USA)
13:30 Standard Cell Library Based Layout Characterization and Power Analysis for 10nm
Gate-All-Around (GAA) Transistors
Luhao Wang, Tiansong Cui and Shahin Nazarian (University of Southern California, USA); Yanzhi
Wang (Syracuse University, USA); Massoud Pedram (University of Southern California, USA)
13:55 Comparative Analysis of Hybrid Magnetic Tunnel Junction and CMOS Logic Circuits
Darya Almasi (San Francisco State University, USA); Houman Homayoun (George Mason
University, USA); Hassan Salmani (Howard University, USA); Hamid Mahmoodi (San Francisco
State University, USA)
14:20 Modeling and Simulation of Quantum-Well Infrared Photodetectors
Sao-Jie Chen, Hsin-Ping Yang, Ding-Jyun Lin and Grace Liu (National Taiwan University, Taiwan)
14:45 Sensitivity Analysis for SoC Performance Benchmark Against Interconnect Parasitic
Resistance and Capacitance Beyond 10-nm FinFET Technology
Motoi Ichihashi, Jia Zeng, Cole Zemke, Irene Lin, Greg Northrop, Ning Jin and Jongwook Kye
(Globalfoundries, USA)
Industry Forum: Data Analytics and Security in IoT Part II
Room: Municipal
Chairs: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom), Ravi Mukkamala (Old
Dominion University, USA)
RF, Analog Design II
Room: Superior
Chair: Haibo Wang (Southern Illinois University Carbondale, USA)
13:30 A Low Power Fourth Order CMOS Modulator with Subthreshold Amplifier
Kwang S. Yoon and Jae-Hyeon Seong (Inha University, Korea); Soo-Hun Yang (Silicon Works,
Korea)
13:55 Low-Power Analog Front-End Interleaved Chain Architecture Oriented to EEG Detection
System
Aisha Alhammadi and Soliman Mahmoud (University of Sharjah, United Arab Emirates (UAE))
14:20 A Novel Design of a Dual Functionality Read-Write Driver for SRAM
Pulkit Sharma (IIITD); Mohammad Hashmi (IIITD, India)
14:45 Novel Ultra Low Voltage Mobile Compatible RF MEMS Switch for Reconfigurable
Microstrip Antenna
Hassan Mostafa (University of Toronto, Canada); Moez El-Massry and Moataz M. Medhat (Cairo
University, Egypt)

Coffee Break
11-Aug-16 11:14 PM

Panel Discussion
Spreading intelligence across a trillion devices - How pervasive will sensemaking be in IoT, which killer apps
Room: Municipal
Chair: Massimo Alioto (National University of Singapore, Singapore)

Cocktail Reception
Room: Vista

Conference Banquet
Room: Visions (28th Floor)
Friday, September 9
Friday, September 9, 08:30 - 10:10
Intel Training Workshop Part I
Altera SDK for OpenCL for Embedded Applications on FPGAs
Marlon Price, Intel Programmable Solutions Group, USA
Room: Municipal
Chair: Marlon Price (Altera, USA)
This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former
knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an
FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while
communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and
performance optimization features that keep the development time short and productivity high.
SoC Design Methods and Algorithms II

Room: Federal
08:30 Heterogeneous Memory Assembly Exploration Using a Floorplan and Interconnect Aware
Framework
Prakhar Raj Gupta (Indian Institute of Technology, Delhi & ST Microelectronics India, India);
Gaurav Narang (STMicroelectronics, India); Gangaikondan Visweswaran (Indian Institute of
Technology, Delhi); Anuj Grover (ST Microelectronics, India)
08:55 Variable-Length VLIW Encoding for Code Size Reduction in Embedded Processors
Ting-Yu Shyu (National Chung Cheng University); Bo-Yu Su and Tay-Jyi Lin (National Chung Cheng
University, Taiwan); Chingwei Yeh (National Chung-Cheng University, Taiwan); Tien-Fu Chen
(National Chiao Tung University, Taiwan); Jinn-Shyan Wang (National Chung Cheng University,
Taiwan)
09:20 Self-dual Diamond-graph CMOS H-bridge Logic Family
Shun-Wen Cheng (Far East University, Taiwan)
09:45 ERFAN: Efficient Reconfigurable Fault-Tolerant Deflection Routing Algorithm for 3-D
Network-on-Chip
Somayeh Maabi (Shaid Beheshti University, Iran); Farshad Safaei (Shahid Beheshti University,
11 of 13
11-Aug-16 11:14 PM
12 of 13
Iran); Amin Rezaei (University of Louisiana at Lafayette, USA); Masoud Daneshtalab (KTH Royal
Institute of Technology, Sweden); Danella Zhao (Old Dominion University, USA)
Special Session: Emerging Stochastic Computing and Neuromorphic Computing: Arithmetic,
Algorithm, and Applications
Room: Superior
08:30 Design of High-speed Low-power Polar BP Decoder Using Emerging Technologies
Ao Ren (Syracuse University, USA); Bo Yuan (City University of New York, USA); Yanzhi Wang
(Syracuse University, USA)
08:55 A Low-Computation-Complexity, Energy-Efficient, and High-Performance Linear Program
Solver Using Memristor Crossbars
Ruizhe Cai, Ao Ren, Yanzhi Wang, Sucheta Soundarajan and Qinru Qiu (Syracuse University, USA);
Bo Yuan (City University of New York, USA); Paul Bogdan (University of Southern California, USA)
09:20 Efficient Hardware Architecture of Softmax Layer in Deep Neural Network
Bo Yuan (City University of New York, USA)
09:45 Noisy Neuromorphic Circuit Modeling Obsessive Compulsive Disorder
Saeid Barzegarjalal, Kun Yue and Alice C. Parker (University of Southern California, USA)

Coffee Break

Intel Training Workshop Part II
Altera SDK for OpenCL for Embedded Applications on FPGAs
Marlon Price, Intel Programmable Solutions Group, USA
Room: Municipal
Chair: Marlon Price (Altera, USA)
This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former
knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an
FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while
communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and
performance optimization features that keep the development time short and productivity high.
Low Power Design

Room: Federal
Chair: Sao-Jie Chen (National Taiwan University, Taiwan)
10:30 Practical Power Consumption Analysis with Current Smartphones
Xiang Chen (George Mason University, USA); Kent Nixon and Yiran Chen (University of Pittsburgh,
USA)
10:55 Fully Parallel Content Addressable Memory Design Using Multi-Bank Structure
Shixiong Jiang (University at Buffalo, USA); Vijayalakshmi Saravanan (University at Buffalo);
Pengzhan Yan and Ramalingam Sridhar (University at Buffalo, USA)
11:20 New Power Budgeting and Thermal Management Scheme for Multi-Core Systems in Dark
Silicon
Hai Wang and Ming Zhang (University of Electronic Science and Technology of China, P.R. China);
Sheldon Tan (University of California, Riverside, USA); Chi Zhang and Yuan Yuan (University of
Electronic Science and Technology of China, P.R. China); Keheng Huang and Zhenghong Zhang
11-Aug-16 11:14 PM
13 of 13
(Southwest China Research Institute of Electronic Equipment, P.R. China)

11:45 Overoptimistic Voltage Scaling in Pre-Error AVS Systems and Learning-Based Alleviation
Yi-Hsuan Ting (National Chung Cheng University, Taiwan); Chih-Yang Wang (National Tsing Hua
University, Taiwan); Yu-Sian Chang (National Chung Cheng University, Taiwan); Tay-Jyi Lin
(National Chung Cheng University, Taiwan); Shih-Chieh Chang (National Tsing Hua University);
Jinn-Shyan Wang (National Chung Cheng University, Taiwan)
Special Session: Security and Validation in Mobile, Embedded, and IoT Systems
Room: Superior
Chair: Sandip Ray (NXP Semiconductors, USA)
10:30 Security Challenges in Mobile and IoT Systems
Sandip Ray (NXP Semiconductors, USA); Jayanta Bhadra (NXP Semiconductors)
10:50 Quantifying Trust in Autonomous System Under Uncertainties
Raj Gautam Dutta, Xiaolong Guo and Yier Jin (University of Central Florida, USA)
11:10 Striking a Balance Between SoC Security and Debug Requirements
Wen Chen and Jayanta Bhadra (NXP Semiconductor, USA)
11:30 Can We Bell the CAD?
Jeyavijayan Rajendran (University of Texas at Dallas, USA)
11:50 Mobile Connected Devices: Security Challenges and Opportunities
Joe Hendrix (Galois Inc., USA)

Lunch

Post Conference Event
11-Aug-16 11:14 PM

Program For 2016 29th IEEE International System-On-Chip Conference (SOCC) (SOCC 2016)

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Program For 2016 29th IEEE International System-On-Chip Conference (SOCC) (SOCC 2016)

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Program for 2016 29th IEEE International System-on-Chip Conference ...