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Optimal Body Bias to Control

Stability, Leakage and Speed in
SRAM Cell
Article in Journal of Circuits System and Computers April 2016
Impact Factor: 0.25 DOI: 10.1142/S0218126616500961

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2 authors:
Rohit Lorenzo
National Institute of Technolog
12 PUBLICATIONS 5 CITATIONS
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Saurabh Chaudhury
National Institute of Technolog
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Available from: Saurabh Chaudhury

Retrieved on: 03 July 2016

Journal of Circuits, Systems, and Computers

Vol. 25, No. 8 (2016) 1650096 (15 pages)
#
.c World Scientic Publishing Company
DOI: 10.1142/S0218126616500961

Optimal Body Bias to Control Stability,

Leakage and Speed in SRAM Cell

Rohit Lorenzo and Saurabh Chaudhury

Department of Electrical Engineering,
National Institute of Technology,
Silchar, Assam 788010, India

rohit.lorenzo@gmail.com

saurabh1971@gmail.com
Received 7 February 2015
Accepted 25 February 2016
Published 20 April 2016
The stability, leakage power and speed of Static random access memory (SRAM) have become
an important issue with CMOS technology scaling. In this paper, a controller circuit is introduced which is separately controlling the load, driver and access transistors of SRAM cell. Based
on word line signal value, optimal body bias voltage is generated through control circuitry to
control stability, leakage and speed in SRAM cell. The proposed cell gives faster read and writes
with an improvement of 68.5% and 89.2% over conventional 6T SRAM cell. In standby mode,
about 62.2% leakage power reduction is observed in 8
16 array architecture of SRAM. The
proposed cell is implemented with 65 nm CMOS technology and exhibits higher hold and write
margins with an improvement of 26.29% in hold margin and 16.6% improvement in write
margin as compared to conventional 6T SRAM cell. Robustness of the proposed SRAM cell with
respect to stability, leakage and speed are conrmed under process, voltage and temperature
variations.
Keywords: Low leakage; body bias control; SRAM; stability; process variation.

1. Introduction
Now-a-days design of low power memory has become an important and essential
requirement because it occupies a large portion of the chip area. Static random access
memory (SRAM) has been widely used in system on chip (SOC) because of its high
speed and compatibility with standard processors. Low-power SRAM cell designs
without compromising speed and stability are very much important in very large
scale integrated systems. Continued device scaling reduces threshold voltage (Vt ),
channel length and gate oxide thickness in MOSFET devices,1 which consequently
leads to excessive leakage power consumption.
*This

paper was recommended by Regional Editor Piero Malcovati.

1650096-1

R. Lorenzo & S. Chaudhury

Eciency and reliability can be signicantly improved by reducing the power

consumption. Many researchers have proposed dierent schemes to reduce power
consumption such as voltage scaling, body biasing and power gating.2 All these
techniques reduce leakage power dissipation in SRAM cell. These leakage reduction
techniques are more eective when devices are scaled down to deep submicron regime
because leakage current sharply increases for down-scaled devices.3 Moreover, power
density is a growing concern in today's high-performance chip which even demands
for thermal-aware design.4
A typical memory organization consists of individual cells arranged in an array
of horizontal rows and vertical columns. Based on word line signal, a particular
row of the cell is in active mode or in standby mode. In standby mode, the static
power dissipation can be reduced by controlling the body biasing. A number of
techniques have been developed to tune the Vt using body biasing methodology to
enhance the performance of SRAM cell. Vt is one of the important parameter to
control leakage current and speed. Researchers have come out with a dierent
idea to control the Vt .5,6 In SRAM cell, low sub-threshold leakage in idle state and
high speed in active mode can be achieved by a suitable body-bias controlling
scheme. Dierent requirements of Vt of NMOS and PMOS transistor in idle and
active mode can be adjusted by an appropriate control of bulk voltages.
Similarly, speed can also be improved by decreasing the Vt during active mode and
sub-threshold leakage current can be reduced by increasing the Vt during idle mode.
Minimization in sub-threshold leakage can be achieved by an over-driven body bias
scheme whereas speed can be enhanced by an under-driven body bias scheme as
shown in Fig. 1.7
In standby mode, both transistors are reverse body-biased (RBB) while in active
mode both transistors are forward body-biased (FBB). With down scaling, the
leakage power will increase due to short channel eects, band to band tunneling, gate
leakage, Drain induced barrier lowering (DIBL), etc. Reverse body-bias may slightly
improve the sub-threshold leakage conduction by increasing the Vt , however, it will
aect the circuit's timing. FBB is found to be the most eective technique to minimize active leakage. However, it should be applied judiciously looking into circuit's
path-criticality. It must be applied partially as veried in Ref. 8. We have also
adopted the same idea and applied partial FBB. In the proposed cell, we have applied
FBB only to the access transistors in the SRAM cell, while keeping the load and
driver transistors Vt unaltered with no body bias. It is also possible to have Vt
modulation even at 32 nm technology.
It has been shown in Ref. 9 that a correctly applied body bias reduces the parameter variations. The variation in Vt can dramatically aect the static noise
margin (SNM).10 So optimal body bias leads to minimum leakage current and improved yield.11 In this paper, we propose, a word line based controller circuit to
operate the SRAM cell in active and idle modes. The word line signal decides

1650096-2

Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell

Vdd+
Vdd
Standby

In

Active

Out

Active

Standby

Vss-
Fig. 1. Over-driven body bias in standby mode.

dierent body voltages for PMOS load transistor, NMOS access and driver transistors in active and idle mode.
The remainder of the paper is organized as follows. In Sec. 2, we briey review
conventional 6T SRAM cell. Section 3 discusses the proposed SRAM cell. Section 4
analyzes the results of the proposed cell. Finally, Sec. 5 concludes this paper.
2. Conventional 6T SRAM Cell
In the structure of conventional 6T SRAM cell as shown in Fig. 2, there are three
main components of current which are considered to be the major contributors to
leakage power dissipation in SRAM cell. These are sub-threshold, gate and junction leakage,12 as indicated by the legends in the gure of 6T SRAM cell. Transistor leakage current is mainly dependent upon the type of transistor, logic level
of the word line and type of operation. There will be always some leaky transistors
in symmetric structure of SRAM cell, whatever the value stored in SRAM cell.
Another important performance matrix is read/write speed and SNM. Reading
and writing speed can be enhanced by decreasing the Vt of access transistor (N3
and N4) but decrease in Vt has a strong impact (negative) on the SNM.12 Sweeping
the Vt values of one transistor causes a mismatch between the two halves of
voltage.

1650096-3

R. Lorenzo & S. Chaudhury

WL
BL

BLB

P1

P2

N3

N4
(Low)

QB

(High)

N1

N2

Isub
Igate
Ijunction

Fig. 2. Conventional 6T SRAM cell.

3. Proposed Architecture
Body bias has been widely used in digital circuits and systems to control leakage
current and timing performances. Applying appropriate body bias while improving
the stability and delay is extremely challenging at deep nanometer level. Gate level
implementation of it has too much area overhead, while the architectural level implementation is inecient and has too much power overhead. However, if it is applied
at word level (row-based style) in SRAM cell architecture then it works eciently in
maintaining the timing constraints and minimizing the power dissipation.8 The
body-bias controller circuit with the proposed SRAM cell architecture is shown in
Fig. 3. This controller circuit improves the speed during active mode, reduces power
during standby mode and controls the stability during both active and standby
mode. In the array of SRAM cell, word line signal is used to control the body bias of
the load, driver and access transistors of SRAM cell. So to control the body bias
voltage of these transistors, dierent voltage levels must be provided during active
and standby mode through a body-bias control circuit. The proposed control circuit
provides three dierent body-bias signals to load, driver and access transistors.
During standby mode, it has two input signals, WL = 0 and WL = 1. Node A (red
node) in Fig. 3(b) of the body bias controller circuit transfers Va Vdd
V voltage
to the bulk (body) of PMOS load transistor. Similarly, node B (blue node) and C
(black node) in Figs. 3(c) and 3(d) transfers Vb Vss
V to the bulk of NMOS
driver and access transistors. In this way, Vt of both PMOS and NMOS transistors
become high, due to this high Vt sub-threshold leakage current will be reduced in
SRAM cell.

1650096-4

Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell

WL
BL

BLB

Vdd + V
N3

P2

P1

N4

WL
PMOS-bulkload

QB
N2

N1

Va

WL

Vdd
(a)

(b)

Small(+ V) = Vc

Vss

WL
NMOS-bulkdriver

Vb

NMOS-bulkaccess

WL

C
Vc

WL

Vss-V

Vss-V

(c)
Fig. 3.

(d)

Proposed SRAM cell with controller circuit (color online).

In active mode, both the access transistor N3 and N4 are FBB to enhance the
speed, when a small positive voltage Vc
V is applied to the bulk of both the
NMOS transistor N3 and N4. We have not supplied bulk with Vdd
V in active
mode just to avoid stability degradation.12 Whereas, the load and driver transistors
Vt is kept unaltered. This means the bulk of load transistors (P2 and P1) are supplied
with Vdd whereas, the bulk of driver transistors (N2 and N1) are tied to Gnd. This is
1650096-5

R. Lorenzo & S. Chaudhury

because, Vt variation of load and driver transistors during active mode has the largest
impact on the voltage transfer characteristic and hence the stability of SRAM is
aected.13 So to avoid the stability problem, we have provided no body bias to load
and driver transistors in active mode and so their Vt remained unaltered.
Based on word line signal, the voltage transfer to PMOS bulk load through A
node is Va 1:12 V and Vdd , voltage transfer to NMOS bulk driver through B node
which is Vb 0:12 V and Vss , voltage transfer to NMOS bulk access through C
node is Vc 0:8 V and 0.12 V. With this stimulus in the control circuit, the body
bias control signals for standby and active mode are shown in Fig. 4.
The advantage of such controller circuit is that by FBB the access transistor (N3,
N4) in active mode, leads to speed-up the read and write operation. Similarly, by
applying RBB to all transistors in idle modes, the leakage currents of the entire
transistor will decrease. The array of proposed design is shown in Fig. 5. The control
lines as indicated by the legends (red, blue and black lines) from controller circuit are
shared by the row of cells. These control lines are for PMOS-bulk-load-transistor,

Fig. 4. Control circuit signals.

1650096-6

Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell

Fig. 5. Array structure of proposed design (color online).

NMOS-bulk-driver-transistor and NMOS-bulk-access-transistor. Each row of array

architecture requires separate controllers because word line signal is dierent for
dierent row. Based on word line signal, particular row is selected for active or
standby mode.
4. Results
To evaluate the performance of the proposed SRAM cell, we perform circuit simulation using Tanner EDA tool. The result of simulation using 65 nm predictive
technology model is then compared with the conventional SRAM cell with a supply
voltage of 1 V and cell beta ratio of 1.8. We have taken a wide range of body bias
voltages for simulation purposes just to see the eect of body bias on performance
metric. Denitely the body bias voltages modulate the Vt even in deep nanometer.
There are library of cells as provided by ARM in 32 nm technology with dierent
body bias voltages having dierent power and timing characteristics with a power
supply of 1.1 V.8 Simulation and analysis for our proposed architecture are presented
in subsequent sections.
4.1. Standby power dissipation
In standby mode, the access transistors of both conventional 6T and proposed
SRAM cell are cut-OFF and the bit-line pairs are charged to Vdd . The total leakage
current is the sum of the sub threshold, gate and junction leakage current.
Again, in standby mode all the transistors are overdriven by applying a voltage of
Vdd
V for PMOS transistors and Vss
V for NMOS transistors. These voltages

1650096-7

R. Lorenzo & S. Chaudhury

Table 1. Static power dissipation (Standby mode at WL 0).
SRAM
6T
Proposed
Va (V)
1.12
1.19
1.26
1.31
1.35
1.4
8
16

Static power (W)

% saving

0.002435

0.001554
0.001341
0.001182
0.001078
0.000999
0.000907
(27  C)

36.10%
44.60%
51.45%
55.70%
59.34%
62.70%

Design at
Vb & Vc (V)
0:12
0:19
0:26
0:31
0:35
0:4
Array

will increase the Vt of all six (PMOS and NMOS) transistors. The static power
consumption has been drastically decreased by the reduction of leakage current in all
six transistors. From Table 1, we can see that the proposed design reduces more
leakage current as compared to conventional 6T SRAM cell, which is about 62.7% in
8
16 array. The static power dissipation of the proposed cell is measured in a wide
range of overdriven voltage of Va , Vb and Vc . At a voltage of Va 1:4 V, Vb 0:4 V
and Vc 0:4 V it gives the best reduction of static power.
Static power dissipation is a function of temperature because leakage current is
dependent on the temperature. Comparison of conventional 6T SRAM cell with
proposed cell at dierent temperature is shown in Fig. 6. The Vt can be increased up

Fig. 6. Static power dissipation at dierent temperatures.

1650096-8

Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell

Fig. 7. Static power dissipation of conventional and proposed cell.

to certain limit, in order to minimize leakage current. However, too much of RBB in
order to raise Vt will cause tunneling and other leakage problems. Static power
consumption is also tested and compared at a dierent process corner of TT, SS, FF,
SF and FS as shown in Fig. 7. From results we can observe that as overdriving
voltage increases, better leakage reduction is achieved in the proposed design.
Finally, in proposed cell, the word line signal controls the Vt of transistors and
maintains the performance by transferring the appropriate body bias signal to the
substrate of all the transistors of SRAM cell.
4.2. Read and write delay
Read and write access time (Read/write delay) is measured, when word line is activated. In the architecture of proposed cell as shown in Fig. 3, during active mode,
control circuit transfers a voltage Va Vdd through node A (red), to load PMOS
transistor and Vb Vss (ground) to the driver NMOS transistor through node B
(blue). In this way, load and driver transistors are actually with no body bias, while
Vt of access transistors in active mode are reduced because the bulk of access transistors forward body- biased by voltage
V through node C (black). So the
proposed cell provides good access time, and consequently results in better read and
write performance. Read and write performance of the proposed design is compared
with conventional 6T SRAM cell, and are shown in Table 2. From Table 2, we can
say that the proposed design achieves better read delay over conventional design by
68.2% at Vc 0:8 V and write delay is reduced by 89.2% at Vc 0:8 V. Performance
1650096-9

R. Lorenzo & S. Chaudhury

Table 2. Comparison of read/write performance at 27  C.
SRAM
6T
Proposed

Read-delay (s)

% reduction

Write-delay (s)

% reduction

5.02E-11

2.05E-11

3.13E-11
2.13E-11
1.59E-11

37.60%
57.40%
68.20%

1.29E-11
5.31E-12
2.25E-12

37.20%
74.30%
89.20%

design

Va

Vb

Vc

Vdd
Vdd
Vdd

Vss
Vss
Vss

0.2 V
0.4 V
0.8 V

Fig. 8. Read delay at dierent corner conditions.

improvement of proposed design with conventional 6T SRAM is also observed at

dierent process corners of TT, SS, FF, SF and FS and are shown in Figs. 8 and 9.
We can see from the results that the proposed design shows better read/write
performance at Vc 0:8 V.
4.3. SNM and stability
Figure 10 shows the buttery curve for conventional 6T and proposed SRAM cell as
obtained during read operation. The plotted curves are obtained at room temperature using a supply voltage of 1 V. Overall SNM is determined by the side length of
smaller square as illustrated in Fig. 10.
The beta ratios of proposed and conventional 6T SRAM cell are taken as 1.8.
Therefore, W /L ratio of driver transistor is large compared to other transistors in

1650096-10

Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell

Fig. 9.

Write delay at dierent corner conditions.

Fig. 10. Buttery curve of conventional -6T and proposed SRAM during read operation.

1650096-11

R. Lorenzo & S. Chaudhury

the SRAM cell. In active mode, Vt of driver transistor is kept unaltered. This is
because Vt variation of the driver transistor has the largest impact on the shape of
voltage transfer characteristic as explained in Ref. 12. Therefore, the body of driver
transistor is tied to Vss (ground), so there is no body bias for driver transistor.
Whereas, the read and write performance of the SRAM cell depends on the Vt of
access transistor. Thus, in order to reduce the read and write delay, the Vt of access
transistor is decreased by applying a FBB, Vc
V . Of course, this reduction in Vt
of access transistor has a negative impact on read SNM. Consequently, stability is
little degraded during read operation when Vc gradually changes. On the other hand,
body terminal of PMOS load transistors are xed to Vdd , in order to avoid degradation in read SNM during active mode. The results of read SNM are shown in the
plot of Fig. 10. From the plot we can observe that as we gradually increase the FBB
of access transistor, the read stability decreases. Table 3 shows the performance
Table 3. Read and write SNM of proposed and conventional 6T-SRAM cell.
SRAM
6T

RSNM

% penalty

WSNM

% improvement

193.58 mv

271.25 mV

185.91 mV
179.41 mV
165.48 mV

3:90%
7:28%
10:50%

296.33 mV
303.58 mV
325.44 mV

8.40%
10.64%
16.60%

Proposed design
Vc 0:2 V
Vc 0:4 V
Vc 0:8 V

Fig. 11. Buttery curve of conventional-6T and proposed SRAM during standby operation.

1650096-12

Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell
Table 4. Hold SNM of proposed and conventional 6T-SRAM cell.
SRAM
6T

HSNM

% improvement

326.569 mV

Proposed design
Va 1:12 V & Vb 0:12 V
Va 1:19 V & Vb 0:19 V

403.079 mV
443.091 mV

18.98%
26.29%

comparison of conventional 6T and proposed SRAM cell in terms of read and write
SNM. Writing in SRAM cell takes place, when the bitline pairs are set with VDD and
0 V. The write operation can be carried out successfully, when access device and write
driver win the ght with the PMOS pull-up transistor inside the cell. An improved
noise margin is achieved in the proposed SRAM cell because Vt of accessed transistor
is decreased. From Table 3 we can observe that the improvement in write margin is
about 16.60% at Vc 0:8 V. Buttery curve of hold static noise margin (HSNM) of
conventional 6T and proposed SRAM cell is shown in Fig. 11. In standby mode, Vt of
all transistors are high, so SNM is improved. As the body bias voltage Va and Vb of
proposed cell increases, voltage transfer characteristic curve is expanded and the size
of the buttery lobe increases which means a better HSNM. Table 4 shows an improvement of 26.29% in hold SNM at Va 1:1 V and Vb 0:19 V as compared to
conventional 6T-SRAM cell.
4.4. Dynamic power dissipation
Dynamic power is calculated during active mode, so the access transistors are
switched ON for both conventional and proposed cell. Table 5 shows the comparison
of 6T and proposed SRAM cell. In the proposed SRAM cell architecture, each row of
SRAM cell is connected to the control circuit. The bulk of each transistor of SRAM
cell is connected to the control circuit, so due to charging/discharging of capacitance
and variation of Vt with the proposed control circuit leads to increase in dynamic
power dissipation of proposed cell as compared to conventional 6T SRAM cell.
Table 5 shows the dynamic power dissipation of 8
16 SRAM array. From the table,

Table 5. Dynamic power dissipation (Active mode at WL 1).

SRAM
6T

Dynamic power

% penalty

7.07E-04

Proposed design
Vc
0.2 V
0.4 V
0.8 V
8
16 array (27  C)

8.13E-04
8.20E-04
8.31E-04

1650096-13

13:03%
13:78%
14:92%

Controller

R. Lorenzo & S. Chaudhury

128 Cells

Fig. 12. Layout Photo of 8
16 SRAM with proposed controller circuit.

we can conclude that increase in dynamic power is negligibly small with the proposed
design even for large arrays as compared to conventional SRAM array.
4.5. Layout
Figure 12 shows the layout of 8
16 SRAM array architecture. The layout of proposed SRAM cell is done using L-EDIT environment in Tanner EDA tool. It is clear
that the body bias controller is causing some area overhead. Today, transistor size
has reached to a level of deep nanometer, so the area is not a major concern.
Moreover, the extra area overhead due to controller circuit can be further minimized
by using common controller for multiple bit SRAM cells.
5. Conclusion
Leakage power, speed and stability are critical issues in SRAM design. In this paper,
a novel control circuit is introduced which is based on word line signal. This control
circuit minimizes the leakage power, delay and improves the stability by controlling
the threshold voltage of all the transistors of SRAM cell. In standby mode, static
power consumption of 8
16 array is reduced by about 62.5%, and the read and
write performance is enhanced by 68.5% and 89.2%. The cell also exhibits 26.29%
and 16.6% higher HSNM and WSNM, by the variation of threshold voltages. Furthermore, the amount of dynamic power penalty of 14% for 8
16 array and read
stability penalty of 10%, which can be considered to be in acceptable range. The
proposed technique is not able to provide the desired leakage reduction at nanoscale
level but it will certainly provide desired speed and stability up to 45 nm.14 Using
65 nm technology, we have seen the eectiveness of the proposed SRAM cell, under
various process, voltage and temperature variations.

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