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Three-Dimensional Hybrid Integration Technology of

CMOS, MEMS, and Photonics Circuits for
Optoelectronic Heterogeneous Integrated Systems
Kang-Wook Lee, Member, IEEE, Akihiro Noriki, Kouji Kiyoyama, Takafumi Fukushima,
Tetsu Tanaka, Member, IEEE, and Mitsumasa Koyanagi, Fellow, IEEE

AbstractWe have developed a new 3-D hybrid integration

technology of complementary metaloxidesemiconductors, microelectromechanical systems (MEMS), and photonics circuits for
optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and
microfluidics hybrid integration. In order to verify the applied
3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI),
MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS
were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of
vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical
and optical interposers were precisely bonded together to form a
3-D optoelectronic multichip module. The photonics and electrical
devices could communicate via TSVs. The photonics devices could
be connected via an optical waveguide formed onto the optical
interposer. Microfluidic channels were formed into the interposer
by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of
individual chips of LSI, MEMS, and photonics devices as they
were integrated into the 3-D optoelectronic multichip module to
verify the applied 3-D hybrid integration technology. LSI, passive,
MEMS, and photonics devices were successfully implemented. The
3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated
systems.
Index TermsChip self-assembly, microfluidic channel, optoelectronic heterogeneous integrated system, Si interposer,
through-silicon via (TSV), waveguide, 3-D hybrid integration.

Manuscript received January 18, 2010; revised November 19, 2010; accepted
November 19, 2010. Date of publication December 30, 2010; date of current
version February 24, 2011. This work was supported by the Grant-in-Aid
for Scientific Research (S), Japan Society for the Promotion of Science,
under Grant 21226009. The review of this paper was arranged by Editor
A. M. Ionescu.
K.-W. Lee, T. Fukushima, and M. Koyanagi are with the New Industry
Creation Hatchery Center, Tohoku University, Sendai 980-8579, Japan (e-mail:
kriss@bmi.niche.tohoku.ac.jp).
A. Noriki is with the Department of Bioengineering and Robotics, Graduate
School of Engineering, Tohoku University, Sendai 980-8579, Japan.
K. Kiyoyama is with the New Industry Creation Hatchery Center, Tohoku
University, Sendai 980-8579, Japan, and also with the Department of Electrical
and Electronic Engineering, Nagasaki Institute of Applied Science, Nagasaki
851-0193, Japan.
T. Tanaka is with the Department of Biomedical Engineering, Graduate
School of Biomedical Engineering, Tohoku University, Sendai 980-8579,
Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2099870

Fig. 1.

Example of the latest safety-vehicle electronics systems.

I. I NTRODUCTION

HE DEMAND for a high-performance and highly integrated optoelectronic system has significantly increased
in correspondence to anticipated future needs. To meet these
requirements, the 3-D integration technology has attracted
attention because it vertically stacks multiple complementary metaloxidesemiconductor (CMOS) large-scale integration (LSI) chips such as processor, memory, logic, analog,
and power integrated circuits (ICs) into one stacked chip.
The 3-D integration technology can provide many benefits,
namely, increased performance, increased data bandwidth, reduced power, a small form factor, reduced packaging volume,
increased yield, and reduced overall costs [1][9].However,
current 3-D integration technologies in the industry solely focus
on stacking the electrical chips. A tremendous increase in
demand for system- and module-level performances has created
the necessity for the integration of photonics circuits with
electronic circuits in realizing exascale computing applications.
Moreover, heterogeneous system integrations involving CMOS,
microelectromechanical systems (MEMs), and photonics circuits have attracted much attention owing to its high functionality, high-speed communication, and low power consumption
[5], [10][17]. Such integrated systems have many potential
applications. One of the important potential applications is the
intelligent vehicle system. Fig. 1 shows an example of the latest
safety-vehicle electronic systems [18], [19]. Various systems
such as radars, sensors, local area networks, microprocessors,

0018-9383/$26.00 2010 IEEE

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Fig. 2. Conceptual structure of the 3-D heterogeneous optoelectronic integrated system-on-silicon for an intelligent vehicle systems variable signal-processing
functions depending on the moving speed of the car.

and electronic control units communicate through car-to-car and

car-to-infrastructure to prevent abnormal events or accidents.
However, current safety-vehicle electronic systems face the
challenges of a limited number of installing systems, limitation
of high-speed signal sensing/data transmission networking, and
large power consumption owing to the large size and long
distance between the systems. Thus, to enhance the functional
performance and decrease power consumption, a compact-size
intelligent vehicle system is necessary. Such an intelligent
vehicle system requires high-speed variable real-time signal
sensing and processing functions that are strongly dependent on
the moving speed of the car, high-performance data-computing
and transmission-networking functions, and a compact size
for low power consumption. For example, high-speed realtime image processing with several thousands of frames per
second might be needed when the vehicle moves with the speed
of more than a hundred kilometers per hour, whereas slower
signal processing is sufficient when it moves with slower speed.
To meet such variable signal-processing functions depending
on the moving speed, high-sensitive MEMS sensors and onchip optical interconnections have to be compactly integrated
with high-performance signal-computing and signal-processing
LSIs. To realize a compact-sized intelligent vehicle system, we
propose a 3-D heterogeneous optoelectronic integrated systemon-silicon, as shown in Fig. 2.
An image sensor stacked with an analog-to-digital converter
is used for high-performance image processing. An accelerometer MEMS sensor, an optical sensor, and radio-frequency ICs
(RF ICs) are used for high-sensitive sensing of the high moving
speed. Three-dimensional memory and processor devices are
used for high-performance data computing. The optical interconnection facilitates high-speed data transmission networking.
Microfluidic channels assist in heat sinking from high-power
LSIs. However, heterogeneous integrations of CMOS, MEMS,
and optoelectronic circuit devices have many technical challenges owing to incompatible processes. On-chip CMOS integrations of photonics and electronics, such as back-end-of-line
(BEOL) and front-end-of-line (FEOL) photonics integrations
[20][23] and silicon-on-insulator (SOI) CMOS optoelectronic
devices, have limitations of complicated and extra processes,
insufficient scalability with CMOS, poor temperature stability, and severe temperature constraints for volume-production
processing [11], [22], [24], [25]. In addition, integration of

Fig. 3. (a) Conceptual structure and layout (b) of the 3-D heterogeneous optoelectronic multichip module composed of LSI, passive, MEMS, and photonics
chips.

CMOS circuits and MEMS sensors using bulk and SOI substrates, such as embedded MEMS sensors on CMOS circuits
and wafer-level encapsulation of MEMS sensors on CMOS
circuits, also have various limitations of complicated process
and design, low production yield, and severe temperature constraints for volume-production processing [26][30].
We have developed a couple of 3-D integration technologies,
such as high-accuracy 3-D integration technologies based on
wafer-level stacking [31][35], heterogeneous multichip module integration technologies based on fluidic chip self-assembly
[36][38], novel sidewall interconnections [39][42], and the
chip-to-chip optical interconnection technology by utilizing
a Si interposer [43][45]. Based on these technologies, we
developed a new 3-D hybrid integration technology of CMOS,
MEMS, and photonics circuit devices for optoelectronic heterogeneous integrated systems. To verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic
multichip module comprising LSI, passive, MEMS, and photonics devices. Individual chips of LSI, passive, MEMS, and
photonics devices in the 3-D optoelectronic multichip module
were successfully implemented.

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Fig. 4. Fabrication process of the 3-D heterogeneous optoelectronic multichip module.

II. D ESIGN AND FABRICATION OF A 3-D H ETEROGENEOUS

O PTOELECTRONIC M ULTICHIP M ODULE
To develop the integration technology of optoelectromechanical and microfluidics for 3-D hybrid integration, we fabricated
a 3-D heterogeneous optoelectronic multichip module.
Fig. 3(a) and (b) shows the conceptual structure and the layout of the 3-D heterogeneous optoelectronic multichip module,
respectively. In this paper, the module is designed to individually measure the component chips of electrical devices and
photonics via TSVs that were formed in the module for evaluating the usability of the 3-D hybrid heterointegration technology.
The module comprised two Si interposers, which are bonded
by a nonconductive film (NCF) layer. The electrical devices of
LSI, passive, and MEMS sensors were mounted onto the surface of the electrical interposer having TSVs and microfluidic
channels. The photonics devices of vertical-cavity surfaceemitting laser (VCSEL) and photodiode (PD) were embedded into the optical interposer having TSVs and an optical
waveguide. The polynorbornene (PNB) optical waveguide film
was laminated on the backside of the optical interposer.
The photonics and electrical devices communicate with each
other through the TSVs. Two photonics devices are connected
through the optical waveguide. Microfluidic channels were
formed by a wafer-direct bonding method. The electrical and
optical interposers are 8.5 mm 14 mm and 11 mm 22 mm
in size, respectively.
Fig. 4 shows the fabrication process of the 3-D heterogeneous
optoelectronic multichip module. First, the optical interposer

with TSVs and an optical waveguide was fabricated. A deep

via of 40-m diameter and 150-m depth was formed into
a Si substrate by a plasma deep reactive-ion etching (DRIE)
process using SF6 and C4 F8 chemical gases. A thermal SiO2
layer of 1.0-m thickness was formed into the TSVs as an
isolation layer at 900 C under H2 thickness and O2 ambience.
A sputtered Ta barrier layer of 0.3-m thickness and a Cu
seed layer of 0.5-m thickness were deposited into TSVs
sequentially. TSVs were completely filled using a Cu electroplating method without photoresist (PR) patterning. After
chemicalmechanical polishing and wet etching processes for
the removal of excess Cu and Ta layers on the surface, a
sputtered Ti layer of 0.1-m thickness and a Au layer of 0.3-m
thickness were deposited. After PR patterning, Au/Ti beamlead metal wires were patterned on the front surface of the
Si substrate. A polyimide film of 10-m thickness was spin
coated on beam-lead metal wires as a supporting layer. The
Si substrate was thinned to 150-m thickness by a mechanical
grinding process until exposure to Cu TSVs. After the cleaning
process, a plasma dielectric layer of 0.3-m thickness was
deposited on the back side of the Si substrate. Then, Au/Ti
beam-lead metal wires were patterned on the back surface of
the Si substrate. A photosensitive polyimide film of 10-m
thickness was spin coated and patterned on the backside surface, except for the cavity areas. After PR mask patterning, two
cavities with 150-m depth were formed from the backside of
the Si substrate through the DRIE process using SF6 and C4 F8
chemical gases. The Si substrate was etched for exposure to
the SiO2 layer, which was formed under a Au/Ti beam-lead

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wire of the front surface. Due to a metal contamination

concern, SiO2 and Ti layers were removed by the HF wet
etching process until a Au beam-lead wire was exposed. A
beam-lead wire of 0.3-m thickness was not attacked during
the wet etching process owing to the polyimide supporting
layer. VCSEL and PD chips having solder bumps of 100-m
height were dropped down into the cavities after a rough
alignment using the conventional flip-chip bonder. Then, they
were precisely embedded into the cavities by using a twostep alignment process comprising cavity-assisted positioning
and surface-tension-assisted self-assembling by using molten
solder bumps. The photonics chips of VCSEL and PD were
electrically connected to beam-lead metal wires after annealing
at 280 C for 1 min. Long aligning time was not required
for high-accuracy alignment and pressure for the bonding of
each chip. Hence, it could be a suitable process for large-scale
production. The supporting polyimide layer was not degraded
after the chip bonding. A PNB optical waveguide film was
laminated on the backside of the Si substrate for an optical
waveguide. Finally, the mirrors of 45 were formed onto the
optical waveguide using an excimer laser [43][45]. The optical
interposers with TSVs and the embedded photonics chips were
successfully formed in a wafer level.
Second, the electrical interposer with microfluidic channels
and TSVs was fabricated. Holes with 10-m depth and 50-m
diameter were formed in the Si substrate of 100-m thickness
using the plasma DRIE process using SF6 and C4 F8 chemical
gases. The supporting wafer of 100-m thickness was directly
bonded to the Si substrate having the holes to form microfluidic channels. Then, the upper wafer was thinned to 50-m
thickness. The total thickness of the electrical interposer was
150-m. TSVs of 40-m diameter and 150-m depth were
formed through the bonded Si substrate wafer by the plasma
DRIE process using SF6 and C4 F8 chemical gases. A thermal
SiO2 layer of 1.0-m thickness was formed into the TSVs as
an isolation layer at 900 C under H2 and O2 ambience. A
sputtered Ta barrier layer of 0.3-m thickness and a Cu seed
layer of 0.5-m thickness were deposited into TSVs sequentially. In order to completely fill into the TSVs, we developed
a double-sided exposure process. First, the front side of the
wafer was exposed. Then, the wafer was flipped to the backside
and exposed using the same mask. By applying the doublesided exposure method, the TSVs were successfully patterned
without any residual PR into them. A Cu electroplating method
was performed to fill into the TSVs. Subsequently, Cu/Sn
microbumps of 5.0-m/2.0-m thickness were formed onto
TSVs at both sides by employing the electroplating method.
After removing the PR, Cu seed and Ti barrier layers of both
sides were sequentially removed by wet etching processes. The
electrical interposers having TSVs and microfluidic channels
were successfully fabricated in a wafer level.
After being attached to a dicing tape, the optical and electrical interposers were diced by a mechanical dicing process,
respectively. An NCF of 5-m thickness was laminated on the
front side of the optical interposer. The electrical interposer
having Cu/Sn microbumps was compressed to the optical interposer having Cu lands at 280 C, 2 min, and bonding force of
20 N using the flip-chip bonder. The electrical and optical inter-

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Fig. 5. SEM cross-sectional views of Cu-sidewall interconnections crossed

over the chip with a step height of 100 m.

posers were electrically connected through Cu/Sn eutectic joining and mechanically bonded through the NCF film. A Cu3 Sn
intermetallic compound was dominantly occupied in the joined
area [46]. Then, the hydrophilic bonding areas were patterned
onto the surface of the electrical interposer for the chip selfassembling method, which is based on the surface tension of
acoustic liquid. A low-temperature plasma-enhanced chemical
vapor deposition (PECVD) layer was pattered as a hydrophilic
area at 230 C. The surrounding area is rendered hydrophobic.
An acoustic liquid with optimized volume is dropped on the
hydrophilic bonding area. Liquid volume is a crucial parameter
to achieve high-accuracy bonding. LSI and passive chips with
100-m thickness were roughly prealigned to the hydrophilic
areas and released onto the electrical interposer. Each component chip was automatically aligned to the bonding areas at high
accuracy and fast speed of a few hundred microseconds by the
surface tension of acoustic liquid. Average alignment accuracy
was 0.5 m. The component chips were tightly bonded to the
hydrophilic area after the liquid droplet is completely evaporated. Shear bonding strength of the self-assembled chip was
measured by a pull test. The bonding strength between the chip
and the Si interposer has been estimated to be more than 5 MPa.
The bonding strength is sufficient for postprocessing [31]
[33]. Then, LSI and passive chips with 100-m thickness were
electrically connected by Cu-sidewall interconnections directly
crossing over the chips by the optimized photolithography and
Cu electroplating process. After sputtered Ti and Cu layers, a
thick PR with high viscosity was spin coated to cover over chips
with a step height of 100 m. However, the PR thickness has a
difference between near the chip sidewall and on the flat area.
Owing to this difference, it is hard to pattern a fine and uniform
interconnection crossing over the chip. In order to overcome
this problem, we find the optimum exposure condition. A
uniform Cu-sidewall interconnection of 10-m thickness and
30-m width crossed over the chip successfully with a step
height of 100 m, as shown in Fig. 5 [39][41].
After the removal of the Ti and Cu layers by the wet
etching process, a MEMS chip with 360-m thickness was
roughly prealigned to the hydrophilic area and released onto
the electrical interposer. The MEMS chip was automatically
aligned to the bonding area at accuracy of 2.0 m and speed
of 2 s by the surface tension of acoustic liquid. The accuracy
and speed of alignment are a little bit degraded compared with
the case of the LSI chip. We assume that this degradation is
induced by the degradation of the hydrophilic area and the

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Fig. 6. Optical image of the cavity chip comprising a Cu TSV and a beamlead wire.

Fig. 8. (a) Cross-sectional structure of the optical interposer. (b) Optical

image from the front of the optical interposer.

Fig. 7. Cross-sectional views of the (a) cavity and (b) optical images from the
top view of the cavity formed in the optical interposer.

higher thickness of the MEMS chip. The MEMS chip was

tightly bonded to the hydrophilic area after the liquid droplet
is completely evaporated. The cavity chip comprising a beamlead wire and a Cu TSV interconnection was fabricated well by
a micromachining process for integrating the thick MEMS chip
without degrading the sensing elements, as shown in Fig. 6.
After dotting Ag pastes on the pads of the MEMS chip and
the Si interposer by a high-accuracy dispenser, the cavity chip
of 300-m thickness was bonded thermal compressively to the
MEMS chip of 360-m thickness and the Si substrate via Ag
pastes simultaneously at a low bonding force of 1 N/bump and
200 C for 2 min by the chip bonder. During the bonding, the
MEMS chip was not directly exposed to mechanical force and
heating. Mechanical force and heat were supplied only to the
cavity chip. A thick MEMS chip with 350-m thickness was
electrically connected by the cavity chip without degradation
in its performance [42]. Thus, the 3-D heterogeneous optoelectronic multichip module comprising LSI, passive, MEMS, and
photonics chips was fabricated.
Fig. 7(a) shows the cross-sectional views of the cavity, and
Fig. 7(b) shows the optical images from the top view of the
cavity formed in the optical interposer. In Fig. 7(b), the left
figure shows the cavity for the VCSEL chip, whereas the right
figure shows the cavity for the PD chip. It can be observed that
thin Au beam leads are well formed on the bottom area of the
cavity without peeling off from underneath the polyimide layer.
This means that the bonding quality between the Au beam-lead
wire and the polyimide layer is good.

Fig. 9.

Optical image from the backside of the optical interposer.

Fig. 10. SEM cross-sectional images of TSV and Cu-Sn microbumps formed
on the electrical interposer.

Fig. 8(a) shows the cross-sectional structure of the optical

interposer, and Fig. 8(b) shows the optical image from the front
of the optical interposer, wherein the photonics chips of the
VSCEL and PD chips were precisely embedded into the cavities.
Fig. 9 shows the optical image from the backside of the optical interposer. The photonics chips were electrically connected
via TSVs, beam leads, and an optical waveguide, which were
formed on the backside of the optical interposer.
Fig. 10 shows the scanning electron microscopy (SEM)
cross-sectional images of TSV and Cu/Sn microbumps formed
on the electrical interposer. A Cu TSV of 40-m diameter
and 150-m depth and Cu/Sn microbumps of 5.0-m/2.0-m
thickness were well formed by double-sided patterning.

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Fig. 11. SEM cross-sectional images of microfluidic channels in the electrical

interposer.

Fig. 14. (a) Cross-sectional structure and (b) optical image from the top view
of the 3-D heterogeneous optoelectronic multichip module.

Fig. 12. (a) Layout of the microfluidic channels. (b) IR image of the fabricated
microfluidic channel.

Fig. 15. Optical image of the heterogeneous MEMSLSI multichip module

that was integrated onto the surface of the electrical interposer.

Fig. 13. IR images of the microfluidic channels after the liquid sealing test.
(a) Before liquid flowing. (b) At the start of liquid flowing. (c) After 5 min of
liquid flowing.

Fig. 11 shows the SEM cross-sectional images of microfluidic channels in the electrical interposer. Microfluidic channels
of 50-m width and 10-m depth were formed successfully by
a wafer-direct bonding method. Two Si wafers were bonded
well without voids and defects at the interface.
Fig. 12(a) shows the layout of the microfluidic channels,
and Fig. 12(b) shows the infrared (IR) image of the fabricated
microfluidic channels. No voids were seen in the IR image of
the bonded wafer with microfluidic channels. We evaluated a
sealing test by allowing the liquid to flow into the microfluidic
channels. No leak was observed during the flow of the liquid
until 5 min, as shown in Fig. 13.
Fig. 14 shows the optical image of the 3-D heterogeneous
optoelectronic multichip module from the top view. The optical
interposer embedded with optoelectronic chips and the electrical interposer mounted with LSI, passive, and MEMS chips
were well bonded together.
Fig. 15 shows the magnified optical image of the heterogeneous MEMSLSI multichip module, where LSI, passive, and

MEMS chips were integrated onto the surface of the electrical

interposer. LSI and passive chips with 100-m thickness were
connected by the Cu-sidewall interconnection, and a MEMS
chip with 350-m thickness was connected by the cavity-chip
interconnection.
III. I MPLEMENTATION OF A 3-D H ETEROGENEOUS
O PTOELECTRONIC M ULTICHIP M ODULE
To verify the 3-D hybrid integration technology, we evaluated the basic functions of individual chips of LSI, passive,
MEMS, and photonics devices, which were integrated into the
3-D optoelectronic multichip module. In this paper, we used
commercial chips of ASK demodulator LSI, pressure-sensing
MEMS, and photonics devices of VCSEL and p-i-n PD.
Fig. 16(c) shows the photograph, block diagram, and measured frequency response characteristics, respectively, of a
third-order LC high-pass filter, where the inductor and the
capacitor chips were connected by Cu-sidewall interconnections. The third-order LC high-pass filter functioned well via
Cu-sidewall interconnections without degradation in its performance. The Cu spiral on-chip inductor and the capacitor were
fabricated using the standard 0.18-m CMOS technology [47].

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Fig. 16. (a) Photograph, (b) block diagram, and (c) measured frequency
response characteristics of the LC high-pass filter, where the inductor and the
capacitor chips were connected by Cu-sidewall interconnections.
Fig. 18. (a) Photograph, (b) block diagram, and measured resistance characteristics of the pressure-sensing MEMS chip (c) before capping and (d) after
capping of the cavity chip.

Fig. 17. (a) Photograph, (b) block diagram, and (c) measured waveform
characteristics of the ASK LSI demodulator LSI, which was connected by Cusidewall interconnections.

Fig. 17(c) shows the photograph, block diagram, and measured waveforms, respectively, of the ASK demodulator LSI,
which was connected by Cu-sidewall interconnections. The
ASK demodulator LSI was fabricated using the standard
0.35-m CMOS technology. The upper signals were the demodulated RF signal VIN and the reference voltage VCM, and
the lower signal was the system clock CLK. The ASK demodulator was able to detect the zero-cross point of the RF signal and
generate the system clock. The ASK demodulator functioned
well via Cu-sidewall interconnections without degradation in
its performance.
Fig. 18 shows the photograph [see Fig. 18(a)], block diagram
[see Fig. 18(b)], and measured characteristics of the pressuresensing MEMS chip before capping [see Fig. 18(c)] and after
capping [see Fig. 18(d)] of the cavity chip. A MEMS chip of
350-m thickness was connected by the cavity chip comprising
Cu TSV beam-lead interconnections. The piezoresistance of the
bridge configuration was implanted into the device to measure
the pressure. The output voltage shows a linear proportional
relation to the applied pressure, even after being capped by the
cavity chip.

Fig. 19. Emitted light signal from the VCSEL chip, which was embedded into
the optical interposer.

However, the output voltage was decreased by around 25%

after capping of the cavity chip, as shown in Fig. 18(d). This
means that the pressure sensitivity of the MEMS chip is reduced
from 70 to 60 mV/bar. We assume that this response delay is
induced by the high resistance of the Ag paste that was used as
an electrode for connecting the cavity chip and the MEMS chip.
The resistance of the Ag paste that was used is 100 , even after
annealing at 150 C for 30 min. However, the annealing temperature could not be increased in the future owing to the limitation
of the maximum operation temperature of the MEMS chip. We
can overcome this response delay by using a low-resistance
metal bump as an electrode instead of the Ag paste. We measured the basic functions of the photonics chips that were embedded into the optical interposer. As the electrical signals were
inputted to the VCSEL chip via TSVs, a light was successfully
emitted from the embedded VCSEL chip, as shown in Fig. 19.
The electrical characteristics of the p-i-n PD chip that was
embedded into the optical interposer were measured through
the TSVs. A light signal was inputted into the PD chip from
the backside of the optical interposer. The reverse current of the
PD is considerably increased on receiving the light signal. The
embedded p-i-n PD chip operated well without degradation in
its performance, as shown in Fig. 20.

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Fig. 20. Electrical characteristics of the p-i-n photodiode chip, which was
embedded into the optical interposer.

In our 3-D hybrid heterointegration technology, many electrical and optical Si interposers can be formed simultaneously
at a wafer level by conventional LSI and micromachining
processes, respectively. The photonics chips with small size
can be embedded precisely into the cavity in the optical interposer by using a conventional flip-chop bonder. The electrical
and optical Si interposers can be bonded easily by an NCF
layer using a conventional flip-chop bonder. Different kinds
of LSI, passive, and MEMS sensor chips can be mounted
simultaneously onto the electrical interposer at high accuracy
of 1-m and fast speed of a few hundred microseconds by the
surface tension of acoustic liquid. The self-assembly method
does not require aligning time, mechanical force, and heating
for bonding the chips. Novel interconnections can be connected
to the component chips at relatively low temperatures of less
than 200 C. This hybrid integration technology has benefits for solid processes, high throughput, sufficient scalability
with the CMOS process, and nontemperature constraints for
processing. Moreover, the signals can be transmitted through
optical interconnects for long distances and through electrical
interconnects for short interconnects. Therefore, the applied
3-D hybrid heterointegration technology could provide a powerful solution for large-scale production of an optoelectronic
heterogeneous integrated system with increased performance,
increased reliability, and reduced overall cost.
IV. C ONCLUSION
We have developed a new 3-D hybrid integration technology of LSI, MEMS, and photonics devices for optoelectronic
heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics
integration. By applying the 3-D hybrid integration technology, we have fabricated the 3-D heterogeneous optoelectronic
multichip module. The electrical components of ASK LSI,
LC filter, and pressure-sensing MEMS chips were mounted
onto the electrical interposer using chip self-assembly and
novel sidewall interconnections. The photonics components of
VCSEL and PD chips were precisely embedded into the optical
interposer by using the two-step alignment process comprising
cavity-assisted positioning and surface tension-assisted selfassembling of molten solder bumps. We have evaluated the
basic functions of individual chips of LSI, passive, MEMS,
and photonics devices that were integrated into the 3-D op-

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toelectronic multichip module. ASK LSI, LC filter, pressuresensing MEMS, and photonics devices of VCSEL and p-i-n
PD were successfully implemented. However, the MEMS chip
showed the degradation of pressure sensitivity after capping of
the cavity chip owing to the high resistance of the Ag paste
electrode. Microfluidic channels were well formed by a waferdirect bonding method. Based on these results, it can be concluded that the applied 3-D hybrid integration technology could
provide a powerful solution for the realization of optoelectronic
heterogeneous integrated systems. The next version of the
3-D optoelectronic multichip module is under development so
that the overall system-level performance could be verified,
and thereby, the possibility of the production of optoelectronics
integrated systems is further explored.
ACKNOWLEDGMENT
This work was performed at the Micro/Nano-Machining Research and Education Center and Jun-ichi Nishizawa Research
Center, Tohoku University. The authors would like to thank
M. Fujiwara, Sumitomo Bakelite Ltd., for his cooperation.
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Kang-Wook Lee (M09) received the B.S. and M.S.

degrees in metallurgical engineering from Inha University, Incheon, Korea, in 1990 and 1992, respectively, and the Ph.D. degree in machine intelligence
and systems engineering (currently bioengineering
and robotics) from Tohoku University, Sendai, Japan,
in 2000.
From 1992 to 1997, he was an Associate Engineer with Kumwon Ltd., Incheon, Korea, where
he engaged in the development of semiconductor
materials. From 2000 to 2001, he was an Engineer
with Japan Science and Technology Corporation, Sendai, where he engaged
in the development of wafer-level 3-D integration technology for integrated
microsystems. From 2001 to 2002, he was a Postdoctoral Researcher with the
Center for Integrated Electronics and Electronics Manufacturing, Department
of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic
Institute, Troy, NY, where he joined the 3-D Processing Technology Research
Program. From 2002 to 2008, he has a Principal Engineer with the Memory
Division, Samsung Electronics Ltd., where he led the research and development
of through-silicon-via-based 3-D stacking technology. He developed prototype
3-D memory devices for high-density memory cards and high-performance
memory modules for the first time in the industry. In 2008, he joined the Department of Bioengineering and Robotics, Tohoku University. He is currently with
the New Industry Creation Hatchery Center, Tohoku University, as an Associate
Professor. His current interests are 3-D stacked large-scale integrations (LSIs),
3-D hybrid heterointegrated LSI microelectromechanical and optoelectronics
systems, retinal prosthesis, brainmachine interface implantable devices, and
intelligent neural probes.

LEE et al.: INTEGRATION TECHNOLOGY OF CMOS, MEMS, AND PHOTONICS CIRCUITS

Akihiro Noriki received the B.S. and M.S. degrees

in 2008 and 2010, respectively, from Tohoku University, Sendai, Japan, where he is currently working
toward the Ph.D. degree with the Department of
Bioengineering and Robotics, Graduate School of
Engineering.
His current interests are silicon-based optoelectronics and on-chip optical interconnections.

Kouji Kiyoyama received the B.E., M.E., and Ph.D.

degrees from Nagasaki Institute of Applied Science
(NiAS), Nagasaki, Japan, in 2000, 2002, and 2006,
respectively, all in engineering.
From 2007 to 2010, he was a Member of Research
Staff with the Micro/Nano-Machining Research and
Education Center, Tohoku University, Sendai, Japan.
Since April 2010, he has been with the Department
of Electrical and Electronic Engineering, NiAS,
where he is currently a Lecturer. In 2010, he joined
the New Industry Creation Hatchery Center, Tohoku
University, where he is currently a Member of Research Staff. His research is in
the field of integrated circuit design, where his interests are low-power mixedsignal circuit design, image data acquisition, circuit design techniques for 3-D
stacked large-scale integration systems, and biomedical applications.

Takafumi Fukushima was born in Gunma, Japan,

on February 6, 1976. He received the B.S., M.S., and
Ph.D. degrees from Yokohama National University,
Yokohama, Japan, in 1998, 2000, and 2003, respectively, all in synthetic chemistry.
From 2001 to 2003, he was a Technical Advisor
with PI R&D Corporation, Yokohama, where he
studied adhesives, interlayer dielectrics, electrodeposition, and photoresists based on soluble block
copolyimides. After that, he worked with the Venture
Business Laboratory, Tohoku University, Sendai,
Japan, as a Postdoctoral Fellow for a year. He was with the Department of
Bioengineering and Robotics, Tohoku University, as a Research Associate from
2004 to 2007 and an Assistant Professor from 2007 to 2009. He is currently
with the New Industry Creation Hatchery Center, Tohoku University, as an
Associate Professor, focusing on many aspects of high-performance large-scale
integrations (LSIs) and bioengineering, including optical interconnections, 3-D
stacked LSIs, retinal prosthesis, and brain-implantable probe systems. His
research interests include polymeric studies focusing on the synthesis and characterization of high-performance heat-resistant polymers such as polyimides
and thermosetting resins.

757

Tetsu Tanaka (M90) received the B.S. and M.S.

degrees in electronics engineering and the Ph.D.
degree in machine intelligence and systems engineering from Tohoku University, Sendai, Japan, in 1987,
1990, and 2003, respectively.
In 1990, he joined Fujitsu Laboratories Ltd.,
where he was engaged in the research and development of scaled MOS devices, including siliconon-insulator devices. From 1994 to 1995, he was a
Visiting Fellow with the University of California,
Berkeley. In 2005, he joined Tohoku University as
an Associate Professor, where he has been a Professor with the Graduate
School of Biomedical Engineering since 2008. He is currently working on
retinal prosthesis, brain-implant devices, 3-D large-scale integration, nanoscale
complementary metaloxidesemiconductor devices, nanodot memory, etc.
Dr. Tanaka is a member of the IEEE Electron Devices Society, IEEE SolidState Circuits Society, and IEEE Engineering in Medicine and Biology Society.

Mitsumasa Koyanagi (M86M90F97) was born

in Hokkaido, Japan, on February 4, 1947. He received the B.S. degree in electrical engineering from
Muroran Institute of Technology, Muroran, Japan, in
1969 and the M.S. and Ph.D. degrees in electronic
engineering from Tohoku University, Sendai, Japan,
in 1971 and 1974, respectively.
In 1974, he joined the Central Research Laboratory, Hitachi Ltd., where he worked on the research
and development of metaloxidesemiconductor
(MOS) memory device and process technology and
invented a stacked capacitor dynamic random access memory (DRAM) memory cell, which has been widely used in the DRAM production. The stacked
capacitor DRAM was the first commercialized 3-D large-scale integration (LSI)
system. He employed high-k materials in DRAM for the first time in 1978.
In addition, he fabricated MOS transistors with shallow junction using laser
annealing technology for the first time in 1979. From 1980 to 1985, he was with
the Device Development Center, Hitachi Ltd. In 1985, he joined the Xerox Palo
Alto Research Center, Palo Alto, CA, where he worked on the research and
development of submicrometer complementary metaloxidesemiconductor
(CMOS) devices, polysilicon thin-film transistors, and the design of analog/digital LSIs. In 1988, he joined the Research Center for Integrated Systems,
Hiroshima University, Hiroshima, as a Professor, where he worked on scaled
MOS devices, 3-D integration technology, optical interconnections, and parallel
computer systems specific for scientific computation. He fabricated the smallest
MOS transistor with a gate length of 70 nm in 1992. He proposed a 3-D
integration technology based on wafer-to-wafer bonding for the first time
in 1989. Since 1994, he has been a Professor with Tohoku University (the
Department of Machine Intelligence and Systems Engineering, the Department
of Bioengineering and Robotics, and, currently, the New Industry Creation
Hatchery Center), where his current interests are nano-CMOS devices, memory
devices, low-voltage and low-power integrated circuits, new intelligent memory
for parallel processor systems, 3-D integration technology, optical interconnections, parallel computer systems specific for scientific computation, real-time
image processing systems and artificial retina chips, retinal prosthesis, and
brain-implant devices and brainlike computer systems. He has been researching
3-D integration technology and optical interconnection for more than 15 years.
Dr. Koyanagi was the recipient of the 2006 IEEE Jun-ichi Nishizawa Medal,
the 1996 IEEE Cledo Brunetti Award, the 2001 Award of Ministry of Education,
Culture, Sports, Science and Technology, the 1994 Solid-State Devices and
Materials Award, the 2004 Optoelectronic Technology Achievement Award
(Japan Society of Applied Physics), and the 1990 Okouchi Prize.