1.

The Boolean expression A B C is a

a) sum term

b) literal term

c) product term

d) complemented term

c) literal term

d) always 1

2. The Boolean expression AB CD is a

a) sum term

b) product term

3. An example of a SOP expression is

a) A( B C ) AC

b) ( A B )( A B C )

c) AB AB ABC

d) Both answers (a) and

(b)
4. An example of a POS expression is
a) A B C

b) A( B C ) AC

c) ( A B )( A B C )

d) Both answers (a) and (b)

5. On a K-map grouping 1s produces

a) SOP expression

b) dont care condition

c) POS expression

d) AND-OR Logic

6. On a K-map grouping 0s produces

a) SOP expression

b) dont care condition

c) pos expression

d) AND-OR Logic

7. How many bits are required to represent an 8-digit decimal number in BCD?
8. How many bytes are in a 32-bit string?
9. How many bytes are needed to represent the decimal value 8,46,569 in BCD?
10. How many fundamental products are there for two variables?
11. How many entries are there on a 4-variable k-map?
12. On a k-map, an octet contains how many 1s ?
13. What is the output of an XOR gate when a logic signal and its exact inverse are connected to its input?
14. What is the output of an XNOR gate when a logic signal and its exact inverse are connected to its input?
15. The most suitable gate for comparing two bits is ________________________
16. An example of a data storage device is
(a) logic gate
(b) flip-flop
(c) comparator

(d) register

(e) both answers (b) and (d)

17. If a 1-of-16 decoder with active-LOW outputs exhibits a LOW on the decimal 12 output, what are the inputs?
(a) A3A2A1A0 = 1010
(b) A3A2A1A0 = 1100 (c) A3A2A1A0 = 1110
(d) A3A2A1A0 = 0100
18. Data selectors are basically same as
(a) decoders
(b) de-multiplexers

(c) multiplexers

(d) encoders

19. if an S-R latch has a 1 on S input and a 0 on R input and then S input goes to 0, the latch will be

a) set

b) reset

c) invalid

20. The invalid state of an S-R latch occurs when

d) clear

b) S=1, R=0

b) S=0, R=1

c) S=1, R=1

d) S=0, R=0

21. For a gated D latch, the Q output always equals the D input

c) Before the enable pulse

c) Immediately after the enable pulse

b) during the enable pulse

d) answers (b) and (c)

22. Like the latch, the flip-flop belongs to a category of logic circuits known as

a) monostable multivibrators
c) astable multivibrators

b) bistable multivibrators
d) one shots

23. The purpose of the clock input to a flip-flop is to

a) clear the device

b) set the device
c) always cause the output to change states
d) cause the output assume a state dependent on the controlling (S-R,J-K, or ) inputs.
24. For an edge-triggered flip-flop,

a)
b)
c)
d)

A change in the state of the flip-flop can occur only at a clock pulse edge
The state that the flip-flop goes to depend on the D input
The output follows the input at each clock pulse
All of these answer

25. A feature that distinguishes the J-K flip-flop from the S-R flip-flop is the

a) toggle condition

b) preset input

c) type of clock

d) clear input

c)

d) J=0, K=1

26. A flip-flop is in the toggle condition when

a) J=1, K=0

b) J=1, K=1

J=0, K=0

27. A J-K flip-flop with J=1 and K=1 has a 10 kHz clock input. The Q output is

a) Constantly HIGH

b) constantly LOW

c) a 10 kHz square wave

d) a 5 kHz sq. wave

28. Asynchronous counters are known as

a) ripple counters
c) decade counters

b) multiple clock counters

d) modulus counters

29. An asynchronous counter differs from a synchronous counter in

a) the number of states in its sequence

c) the type of flip-flops used

b) the method of clocking

d) the value of the modulus

30. The modulus of a counter is

a) the number of flip-flops b) the actual number of states in its sequence

c) the number of times it recycles in a second
d) the maximum possible number of states
31. A 4-bit binary counter has a maximum modulus of

a) 16
b) 32
c) 8
d) 4
32. A modulus-12 counter must have
a) 12 flip-flops b) 3 flip-flops c) 4 flip-flops d) synchronous clocking
33. Which one of the following is an example of a counter with a truncated modulus?

a) Modulus 8

b) Modulus 14

c) Modulus 16

d) Modulus 32

34. A 4-bit ripple counter consists of flip-flops the each have a propagation delay from clock to Q output of

12 ns. For the counter to recycle from 1111 to 0000, it takes a total of
a) 12ns

b) 24ns

c) 48ns

d) 36ns

35. A BCD counter is an example of

a) a full-modulus counter
d) answers (b) and (c)

b) a decade counter

c) a truncated-modulus counter

36. Which of the following is an invalid state in an 8421 BCD counter?

a) 1100

b) 0010

c) 0101

d)1000

37. Three cascaded modulus-10 counters have an overall modulus of

a) 30

b) 100

c) 1000

d)10,000

38. A 10 MHz clock frequency is applied to cascaded counter consisting of a modulus-5 counter, a modulus-

8 counter, and two modulus-10 counters. The lowest output frequency possible is
a) 10 kHz
b) 2.5 kHz
c) 5 kHz
d) 25 kHz
39. A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN mode is

a) 0001

b) 1111

c) 1000

d) 1110

40. The terminal count of a modulus-13 binary counter is

a) 0000

b) 1111

c) 1101

d) 1100

c) a byte of storage

d) four bits of storage

41. A stage in a shift register consists of

a) a latch

b) a flip-flop

42. To serially shift a byte of data into a shift register, there must be

a) 1 clock pulse

b) 1 load pulse

c) 8 clk pulses

d) 1 clk pulse for each 1 in the data

43. To parallel load a byte of data into a shift register with a synchronous load, there must be

a) one clock pulse

c) eight clock pulses

b) one clock pulse for each 1 in the data

d) one clock pulse for each 0 in the data

44. The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit parallel output shift

register with an initial state of 11100100. After tow clock pulses, the register contains
a) 01011110
b) 10110101
c) 01111001

d) 00101101

45. With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register

a) in 8 s
c) in 1s

b) in the propagation delay time of eight flip-flops

d) in the propagation delay time of one flip-flop

46. A modulus-10 Johnson counter requires

a) ten flip-flops

b) four flip-flops

c) five flip-flops

d) twelve flip-flops

47. A modulus-10 ring counter requires a minimum of

a) ten flip-flops

b) five flip-flops

c) four flip-flops

d) twelve flip-flops

48. When an 8-bit serial in/serial out shift register is used for a 24 s time delay, the clk frequency must be

a) 41.67 kHz b) 333 kHz c) 125 kHz d) 8 MHz

49.