ARM Cortex-M

1.1 ARM license

ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the
processor architecture to interested parties. ARM oers
a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable
hardware description of the ARM core, as well as complete software development toolset and the right to sell
manufactured silicon containing the ARM CPU.

ARM Cortex-M0 and Cortex-M3 ICs from NXP and Energy Micro

1.2 Silicon customization

Integrated device manufacturers (IDM) receive the ARM
Processor IP as synthesizable RTL (written in Verilog).
In this form, they have the ability to perform architectural
level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher
clock speed, very low power consumption, instruction
set extensions, optimizations for size, debug support, etc.
To determine which components have been included in
a particular ARM CPU chip, consult the manufacturer
datasheet and related documentation.
Some of the most important options for the Cortex-M
cores are:
SysTick timer: A 24-bit system timer that extends the functionality of both the processor and
the Nested Vectored Interrupt Controller (NVIC).
When present, it also provides an additional congurable priority SysTick interrupt.[6][7][8] Though the
SysTick timer is optional, its rare to see a Cortex-M
microcontroller without it.

Die of a STM32F100C4T6B ARM Cortex-M3 microcontroller

with 16 KB ash memory, 24 MHz CPU, motor control, and
CEC functions. Manufactured by STMicroelectronics.

Bit-banding: Maps a complete word of memory

onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the
corresponding bit in the bitband region. This allows every individual bit in the bit-banding region
to be directly accessible from a word-aligned address, and individual bits to be toggled from C/C++
without performing a read-modify-write sequence
of instructions.[6][7][8]

The ARM Cortex-M is a group of 32-bit RISC ARM

processor cores licensed by ARM Holdings. The cores
are intended for microcontroller use, and consist of the
Cortex-M0, M0+, M1, M3, M4, and M7.[1][2][3][4][5]

Overview

Memory Protection Unit (MPU): Provides support

for protecting regions of memory through enforcing
privilege and access rules. It supports up to eight
dierent regions, each of which can be split into a
further eight equal-size sub-regions.[6][7][8]

Main articles: ARM architecture and List of ARM cores

See also: ARM Cortex-A and ARM Cortex-R

1
Note: Most Cortex-M3 and M4 chips have bitbanding and MPU. The bit-banding option can be
added to the Cortex-M0 / M0+ using the Cortex-M
System Design Kit.[9]

OVERVIEW

M0+ / M1 were designed to create the smallest silicon

die, thus having the fewest instructions of the Cortex-M
family.

The Cortex-M0 / M0+ / M1 include Thumb instructions,

Note: Software should validate the existence of a except new instructions (CBZ, CBNZ, IT) which were
added in ARMv7-M architecture. The Cortex-M0 / M0+
feature before attempting to use it.[8]
/ M1 include a minor subset of Thumb-2 instructions (BL,
DMB, DSB, ISB, MRS, MSR). The Cortex-M3 / M4 /
Additional silicon options:[6][7]
M7 have all base Thumb and Thumb-2 instructions. The
Cortex-M3 adds 3 Thumb instructions, all Thumb-2 in Data endianness: Little-endian or big-endian. Un- structions, hardware divide, and saturation arithmetic inlike legacy ARM cores, the Cortex-M is perma- structions. The Cortex-M4 adds DSP instructions and an
nently xed in silicon as one of these choices.
optional single-precision oating-point unit (VFPv4-SP).
The Cortex-M7 adds an optional double-precision FPU
Interrupts: 1 to 32 (Cortex-M0/M0+/M1), 1 to 240
(VFPv5).[6][7]
(Cortex-M3/M4/M7).
Wake-up interrupt controller: Optional.
Vector Table Oset Register: Optional.
Instruction fetch width: 16-bit only, or mostly 32bit.
User/privilege support: Optional.
Reset all registers: Optional.
Single-cycle I/O port: Optional.
Debug Access Port (DAP): Optional.
Halting debug support: Optional.
Number of watchpoint comparators: 0 to 2 (Cortex
M0/M0+/M1), 0 to 4 (Cortex-M3/M4/M7).
Number of breakpoint comparators: 0 to 4 (Cortex
M0/M0+/M1), 0 to 8 (Cortex-M3/M4/M7).

1.3

Instruction sets

See also: ARM architecture Instruction set

The Cortex-M0 / M0+ / M1 implement the ARMv6-M
architecture,[6] the Cortex-M3 implements the ARMv7M architecture,[7] and the Cortex-M4 / M7 implements
the ARMv7E-M architecture.[7] The architectures are
binary instruction upward compatible from ARMv6-M to
ARMv7-M to ARMv7E-M. Binary instructions available
for the Cortex-M0 / M0+ / M1 can execute without modication on the Cortex-M3 / M4 / M7. Binary instructions available for the Cortex-M3 can execute without
modication on the Cortex-M4 / M7.[6][7] Only Thumb
and Thumb-2 instruction sets are supported in Cortex-M
architectures, but the legacy 32-bit ARM instruction set
isn't supported.
All six Cortex-M cores implement a common subset of
instructions that consists of most Thumb, some Thumb2, including a 32-bit result multiply. The Cortex-M0 /

Note: The Cortex-M0 / M0+ / M1 doesn't include

these 16-bit Thumb instructions: CBZ, CBNZ,
IT.[6][7]
Note: The Cortex-M0 / M0+ / M1 only include
these 32-bit Thumb-2 instructions: BL, DMB,
DSB, ISB, MRS, MSR.[6][7]
Note: The Cortex-M0 / M0+ / M1 only has 32bit multiply instructions with a lower-32-bit result
(32bit 32bit = lower 32bit), where as the CortexM3 / M4 / M7 includes additional 32-bit multiply instructions with 64-bit results (32bit 32bit = 64bit).
The Cortex-M4 / M7 also include DSP instructions
for (16bit 16bit = 32bit), (32bit 16bit = upper
32bit), (32bit 32bit = upper 32bit) multiplications.
If a smaller silicon die is required, the Cortex-M0 /
M0+ / M1 has an option to be a much slower instruction, though it is rarely implemented in the M0
or M0+.[6][7]
Note: The Cortex-M4 has a silicon FPU option (VFPv4-SP) of single-precision (SP), which is
known as a Cortex-M4F. The Cortex-M7 has silicon FPU options (VFPv5) of single-precision (SP),
or both single-precision (SP) and double-precision
(DP). If the Cortex-M4 or M7 has a FPU, then it is
known as the Cortex-M4F or Cortex-M7F.[6][7]
Note: The Cortex-M series includes three new 16bit Thumb instructions for sleep mode: SEV, WFE,
WFI.
Note: The single-precision (SP) FPU instructions
are valid in the Cortex-M4/M7 only when the SP
FPU option exists in the silicon.
Note: The double-precision (DP) FPU instructions
are valid in the Cortex-M7 only when the DP FPU
option exists in the silicon.

2.1

1.4

Chips

ARM deprecations

The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:[6][7]
The 32-bit ARM instruction set is not included in
Cortex-M cores.
Endianness is chosen at silicon implementation in
Cortex-M cores. Legacy cores allowed on-the-y
changing of the data endian mode.
Co-processors aren't supported on Cortex-M cores.

3
3-stage pipeline.
Instruction sets:
Thumb (most), missing CBZ, CBNZ, IT.
Thumb-2 (some), only BL, DMB, DSB, ISB,
MRS, MSR.
32-bit hardware multiply with 32-bit result.
1 to 32 interrupts, plus NMI.
Silicon options:

Hardware multiply speed: 1-cycle or 32-cycles.

The capabilities of the 32-bit ARM instruction set is duplicated in many way by the Thumb and Thumb-2 instruction sets, but some ARM features don't have a simi- 2.1 Chips
lar feature:
The following microcontrollers are based on the Cortex The SWP and SWPB (swap) ARM instructions M0 core:
don't have a similar feature in Cortex-M.
Cypress PSoC 4
The 16-bit Thumb instruction set has evolved over time
Inneon XMC1000
since it was rst released in the legacy ARM7T cores
with the ARMv4T architecture. New Thumb instruc Nordic nRF51 Series
tions were added as each legacy ARMv5 / ARMv6 /
NXP LPC1100, LPC1200
ARMv6T2 architectures were released. Some 16-bit
Thumb instructions were removed from the Cortex-M
nuvoTon NuMicro
cores:
Sonix SN32F700
BLX <immediate>" instruction doesn't exist be STMicroelectronics STM32 F0
cause it was used to switch from Thumb to ARM
instruction set. The BLX <register>" instruction is
Toshiba TX00
still available in the Cortex-M.
CPSIE and CPSID also don't exist because ARM
instruction set is missing from Cortex-M. Other CPS
instructions still exists in the Cortex-M.
SETEND doesn't exist because on-the-y switching
of data endian mode is no longer supported.
Co-processor instructions are not supported.
SWI instruction was renamed to SVC instruction,
though the instruction binary coding is the same.
However, the SVC handler code is dierent than
SWI handler because of changes to the exception
models.

The following chips have a Cortex-M0 as a secondary

core:
NXP LPC4300 (one Cortex-M4F + one CortexM0)
Texas Instruments SimpleLink Wireless MCUs
CC1310 and CC2650 (one programmable CortexM3 + one Cortex-M0 network processor + one proprietary Sensor Controller Engine)

3 Cortex-M0+

The Cortex-M0+ is an optimized superset of the CortexM0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing one to use
The Cortex-M0 core is optimized for small silicon die size the same compiler and debug tools. The Cortex-M0+
pipeline was reduced from 3 to 2 stages, which lowers the
and use in the lowest price chips.
power usage. In addition to debug features in the existing
Key features of the Cortex-M0 core are:[1]
Cortex-M0, a silicon option can be added to the CortexM0+ called the Micro Trace Buer (MTB) which pro ARMv6-M architecture[6]
vides a simple instruction trace buer. The Cortex-M0+

Cortex-M0

4 CORTEX-M1
NXP LPC800, LPC11E6x, LPC11U6x
Silicon Labs/Energy Micro EFM32 Zero, Happy
STMicroelectronics STM32 L0
Smallest ARM microcontrollers are of the Cortex-M0+
type (as of 2014, smallest at 1.6 mm by 2 mm is Kinetis
KL03)[12]

Freescale FRDM-KL25Z Board with KL25Z128VLK (Kinetis L

series)

4 Cortex-M1

The Cortex-M1 is an optimized core especially designed

also received Cortex-M3 and Cortex-M4 features, which to be loaded into FPGA chips.
can be added as silicon options, such as the memory proKey features of the Cortex-M1 core are:[3]
tection unit (MPU) and the vector table relocation.[2]
Key features of the Cortex-M0+ core are:[2]

ARMv6-M architecture[6]

ARMv6-M architecture[6]

3-stage pipeline.

2-stage pipeline (one less than Cortex-M0).

Instruction sets:

Instruction sets: (same as Cortex-M0)

Thumb (most), missing CBZ, CBNZ, IT.
Thumb-2 (some), only BL, DMB, DSB, ISB,
MRS, MSR.
32-bit hardware multiply with 32-bit result.
1 to 32 interrupts, plus NMI.
Silicon options:
Hardware multiply speed: 1-cycle or 32-cycles.

Thumb (most), missing CBZ, CBNZ, IT.

Thumb-2 (some), only BL, DMB, DSB, ISB,
MRS, MSR.
32-bit hardware multiply with 32-bit result.
1 to 32 interrupts, plus NMI.
Silicon options:
Hardware multiply speed: 3-cycle or 33-cycles.

8 region memory protection unit (MPU) (same as

Cortex-M3 and Cortex-M4).

Optional Tightly-Coupled Memory (TCM): 0 to 1

MB instruction-TCM, 0 to 1 MB data-TCM, each
with optional ECC.

Vector table relocation (same as Cortex-M3 and

Cortex-M4).

External interrupts: 0, 1, 8, 16, 32.

Single-cycle I/O port (unique to Cortex-M0+).

Debug: none, reduced, full.

Micro Trace Buer (MTB) (unique to CortexM0+).

Data endianness: little-endian or BE-8 big-endian.

OS extension: present or absent.

3.1

Chips
4.1 Chips

The following microcontrollers are based on the CortexM0+ core:

The following FPGA vendors support the Cortex-M1 as
soft-cores:
Atmel SAMD, SAMR, SAML, SAMC
Cypress PSoC 4 S-Series and FM0+

Actel/Microsemi FPGAs

Freescale/NXP Kinetis E, EA, L, M, V1, W0

Altera FPGAs

Holtek HT32F52xxx

Xilinx FPGAs

5.1

Chips

5
Silicon options:
Optional Memory Protection Unit (MPU): 0 or 8 regions.

5.1 Chips

Arduino Due board with Atmel ATSAM3X8E (ARM Cortex-M3

core) microcontroller

The following microcontrollers are based on the CortexM3 core:

Actel SmartFusion, SmartFusion 2
Analog Devices ADuCM3xx
Atmel SAM3A, SAM3N, SAM3S, SAM3U,
SAM3X

NXP LPCXpresso Development Board with LPC1343

Texas Instruments "Ducati" SIP core

Holtek HT32F

Cortex-M3

Luminary Micro/TI LM3S1968

(sys)
Notify driver

IVA-HD
(video sub-system)

NXP LPC1300, LPC1700, LPC1800

Cortex-A9
(Host CPU)
Linux

ON Semiconductor Q32M210

Cortex-M3
(app)
Ducati MM
software

ISS
(image sub-system)

The TI Ducati SIP core uses a Cortex-M3 cores to ooad video

acceleration and image processing.

Cypress PSoC 5LP, FM3

Cortex-M3

Key features of the Cortex-M3 core are:[4][13]

ARMv7-M architecture[7]
3-stage pipeline with branch speculation.
Instruction sets:
Thumb (entire).
Thumb-2 (entire).

Silicon Labs Precision32

Silicon Labs/Energy Micro EFM32 Tiny, Gecko,
Leopard, Giant
STMicroelectronics STM32 F1, F2, L1, W
Texas
Instruments
SimpleLink
MCUs (CC1310 Sub-GHz and
BLE+ZigBee+6LoWPAN)

Wireless
CC2650

Toshiba TX03
The following chips have a Cortex-M3 as a secondary
core:
Apple A9 (Cortex-M3 as integrated M9 motion CoProcessor)

32-bit hardware multiply with 32-bit or 64-bit

result, signed or unsigned, add or subtract after
the multiply.

CSR Quatro 5300 series (Cortex-M3 as coprocessor)

32-bit hardware divide (2-12 cycles).

Samsung Exynos 7420 (Cortex-M3 as a DVS

microcontroller)[14]

saturation arithmetic support.

1 to 240 interrupts, plus NMI.
12 cycle interrupt latency.
Integrated sleep modes.

Texas Instruments F28, LM3, TMS470, OMAP

4470 (one Cortex-A9 + two Cortex-M3)
XMOS XS1-XA family (seven xCORE + one
Cortex-M3)

6 CORTEX-M4
1 to 240 interrupts, plus NMI.
12 cycle interrupt latency.
Integrated sleep modes.
Silicon options:

Energy Micro Wonder Gecko STK Board with EFM32WG990

Optional Floating-Point Unit (FPU): singleprecision only IEEE-754 compliant. It is called the
FPv4-SP extension.
Optional Memory Protection Unit (MPU): 0 or 8 regions.

6.1 Chips
The following microcontrollers are based on the CortexM4 core:
Atmel SAM4L, SAM4N, SAM4S, SAM4N
Freescale/NXP Kinetis K, W2
The following microcontrollers are based on the CortexM4F (M4 + FPU) core:
Atmel SAM4C (dual core), SAM4E, SAMG
Cypress FM4
TI Stellaris Launchpad Board with LM4F120

Cortex-M4

Freescale/NXP Kinetis K, V3, V4

Inneon XMC4000
Microchip CEC1302

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP

Instructions, and optional oating-point unit (FPU). If a
core contains an FPU, it is known as a Cortex-M4F, otherwise it is a Cortex-M4.

Nordic nRF52

Key features of the Cortex-M4 core are:[5]

Silicon Labs/Energy Micro EFM32 Wonder

NXP LPC4000, LPC4300 (one Cortex-M4F + one

Cortex-M0)

ARMv7E-M architecture[7]

STMicroelectronics STM32 F3, F4, L4

3-stage pipeline with branch speculation.

Texas Instruments LM4F, TM4C, MSP432

Instruction sets:

Texas Instruments SimpleLink Wi-Fi CC3200 and

CC3200MOD (FCC, IC, CE pre-certied module)

Thumb (entire).
Thumb-2 (entire).

Toshiba TX04

32-bit hardware multiply with 32-bit or 64-bit

result, signed or unsigned, add or subtract after The following chips have either a Cortex-M4 or M4F as
a secondary core:
the multiply.
32-bit hardware divide (2-12 cycles).
Saturation arithmetic support.
DSP extension: Single cycle 16/32-bit MAC,
single cycle dual 16-bit MAC, 8/16-bit SIMD
arithmetic.

Freescale/NXP Vybrid VF6 (one Cortex-A5 + one

Cortex-M4F)
Freescale/NXP i.MX 6 SoloX (one Cortex-A9 +
one Cortex-M4F)

7.1

Chips

Freescale/NXP i.MX 7 Solo/Dual (one or two

Cortex-A7 + one Cortex-M4F)
Texas Instruments OMAP 5 (two Cortex-A15s +
two Cortex-M4)
Texas Instruments Sitara AM57xx (one or two
Cortex-A15s + two Cortex-M4s as image processing units + two Cortex-M4s as general purpose
units)

7
Optional Tightly-Coupled Memory (TCM): 0 to 16
MB instruction-TCM, 0 to 16 MB data-TCM, each
with optional ECC.
Optional Memory Protection Unit (MPU): 8 or 16
regions.
Optional Embedded Trace Macrocell (ETM):
instruction-only, or instruction and data.
Optional Retention Mode (with ARM Power Management Kit) for Sleep Modes.

Cortex-M7
7.1 Chips

The Cortex-M7 is a high-performance core with almost double the power eciency of the older Cortex- The following microcontrollers are based on the CortexM4. It features a 6-stage superscalar pipeline with M7 core:
branch prediction and an optional oating-point unit capable of single-precision and optionally double-precision
Atmel SAME70, SAMS70, SAMV70
operations.[15][16] The instruction and data buses have
been enlarged to 64-bit wide over the previous 32-bit
Freescale/NXP Kinetis KV5x[17]
buses. If a core contains an FPU, it is known as a Cortex STMicroelectronics STM32 F7[18]
M7F, otherwise it is a Cortex-M7.
Key features of the Cortex-M7 core are:
ARMv7E-M architecture.
6-stage pipeline with branch speculation.

8 Development tools
Main article: List of ARM Cortex-M development tools

Instruction sets:
Thumb (entire).
Thumb-2 (entire).

9 Documentation

32-bit hardware multiply with 32-bit or 64-bit The amount of documentation for all ARM chips is
result, signed or unsigned, add or subtract after daunting, especially for newcomers. The documentation
the multiply.
for microcontrollers from past decades would easily be
inclusive in a single document, but as chips have evolved
32-bit hardware divide (2-12 cycles).
so has the documentation grown. The total documenta Saturation arithmetic support.
tion is especially hard to grasp for all ARM chips since
DSP extension: Single cycle 16/32-bit MAC, it consists of documents from the IC manufacturer and
single cycle dual 16-bit MAC, 8/16-bit SIMD documents from CPU core vendor (ARM Holdings).
arithmetic.
A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufac 1 to 240 interrupts, plus NMI.
turer datasheet for the exact physical chip, manufacturer
12 cycle interrupt latency.
detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core
Integrated sleep modes.
generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes
the instruction set(s).
Silicon options:
Optional Floating-Point Unit (FPU): (single preci- Documentation tree (top to bottom)
sion) or (single and double-precision), both IEEE754-2008 compliant. It is called the FPv5 exten1. IC manufacturer website
sion.
2. IC manufacturer marketing slides
Optional CPU cache: 0 to 64 KB instruction-cache,
0 to 64 KB data-cache, each with optional ECC.
3. IC manufacturer datasheet

13
4. IC manufacturer reference manual
5. ARM core website
6. ARM core generic user guide
7. ARM core technical reference manual
8. ARM architecture reference manual

EXTERNAL LINKS

[13] Sadasivan, Shyam. An Introduction to the ARM CortexM3 Processor (PDF). ARM Holdings. Archived from
the original on July 26, 2014.
[14] The Samsung Exynos 7420 Deep Dive - Inside A Modern
14nm SoC. AnandTech. Retrieved 2015-06-15.
[15] Cortex-M7 Processor.
2014-09-24.

ARM Holdings.

Retrieved

IC manufacturers have additional documents, such as: [16] Press Release - ARM Supercharges MCU Market
with High Performance Cortex-M7 Processor; arm.com;
evaluation board user manuals, application notes, getting
September 24, 2014;
started guides, software library documents, errata, and
more. See External Links section for links to ocial [17] KV5x: Kinetis KV5x - 240 MHz, ARM CortexARM documents.
M7, Real-Time Control, Ethernet, Motor Control and

10

See also

ARM architecture, List of ARM microprocessor

cores

Power Conversion, High-Performance Microcontrollers

(MCUs)". Freescale Semiconductor. Retrieved 2015-0409.
[18] STM32 F7 series of very high performance MCUs with
ARM Cortex-M7 core. STMicroelectronics. Retrieved 2014-09-24.

Microcontroller, List of common microcontrollers

Embedded system, Single-board microcontroller
JTAG, SWD

11

References

[1] Cortex-M0 r0p0 Technical Reference Manual; ARM

Holdings.
[2] Cortex-M0+ r0p0 Technical Reference Manual; ARM
Holdings.
[3] Cortex-M1 r1p0 Technical Reference Manual; ARM
Holdings.
[4] Cortex-M3 r2p1 Technical Reference Manual; ARM
Holdings.
[5] Cortex-M4 r0p1 Technical Reference Manual; ARM
Holdings.
[6] ARMv6-M Architecture Reference Manual; ARM Holdings.
[7] ARMv7-M Architecture Reference Manual; ARM Holdings.
[8] Cortex-M3 Embedded Software Development; App Note
179; ARM Holdings.
[9] Cortex-M System Design Kit; ARM Holdings.
[10] http://infocenter.arm.com/help/index.jsp?topic=/com.
arm.doc.dai0321a/BIHEADII.html

12 Further reading
The Denitive Guide to the ARM Cortex-M0 and
Cortex-M0+ Processors; 2nd Edition; Joseph Yiu;
Newnes; 784 pages; 2015; ISBN 978-0128032770.
The Denitive Guide to the ARM Cortex-M3 and
Cortex-M4 Processors; 3rd Edition; Joseph Yiu;
Newnes; 600 pages; 2013; ISBN 978-0124080829.
Embedded Systems with ARM Cortex-M3 Microcontrollers in Assembly Language and C; 1st Edition; Yifeng Zhu; 542 pages; 2014; ISBN 9780982692622.
Digital Signal Processing and Applications Using the
ARM Cortex-M4; 1st Edition; Donald Reay; Wiley;
250 pages; 2014; ISBN 978-1118859049.
Embedded Systems: Introduction to Arm Cortex-M
Microcontrollers; 5th Edition; Jonathan Valvano;
506 pages; 2012; ISBN 978-1477508992.
Assembly Language Programming: ARM CortexM3; 1st Edition; Vincent Mahout; Wiley-ISTE; 256
pages; 2012; ISBN 978-1848213296.
An Introduction To Reverse Engineering for Beginners including ARM assembly; Dennis Yurichev;
online book.
ARM Architecture Fundamentals; YouTube.

[11] K60 Family Product Brief; Freescale; May 2011.

[12] Fingas, Jon (25 February 2014). Freescale makes the
worlds smallest ARM controller chip even tinier. Retrieved 2 October 2014.

13 External links
ARM Cortex-M ocial documents

9
ARM Cortex-M ocial website
ARM Cortex-M Software Interface Standard (CMSIS)

Quick Reference Cards

Instructions: Thumb (1), ARM and Thumb-2 (2),
Vector Floating-Point (3), arm.com
Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives (5).
Migrating
Migrating from 8051 to Cortex-M, arm.com
Migrating from PIC to Cortex-M3, arm.com
Migrating from ARM7TDMI to Cortex-M3,
arm.com
Other
Bit Banding on the STM32 microcontrollers

10

14

14
14.1

TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES

Text and image sources, contributors, and licenses

Text

ARM Cortex-M Source: https://en.wikipedia.org/wiki/ARM_Cortex-M?oldid=731987029 Contributors: Jni, Brouhaha, Mcapdevila,

Podom, Alexander.stohr, Imroy, Jantangring, Corwin8, Lightkey, Ketiltrout, Gabrieldiego, Jaycarlson, Geoeg, Chris Burrows, GeorgJohann, Khazar, Hu12, Xose.vazquez, Quibik, Figjam88au, Guy Macon, Elric2056, VolkovBot, MarkMLl, Wdwd, Niceguyedc, Joosteto,
HumphreyW, Mortense, Ndsm, Chchou7, Mjbcswitzerland, Nogib, Andreasfa, ZroBot, Sbmeirow, Tlwm, Toshio Yamaguchi, Ashok2102,
Mcunerd, Bwbuckley, Helpful Pixie Bot, Alpheb, Yowanvista, FossMCU, Glacialfox, Prithvirajnarendra, BattyBot, Pratyya Ghosh, Cyberbot II, ChrisGualtieri, Dhx1, Mogism, Ravaz1977, Comp.arch, Jkba, Lishengyang, ScotXW, Lagoset, Filedelinkerbot, (don't talk secrets),
Csd113, Maredsous10 and Anonymous: 80

14.2

Images

File:ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg Source:
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ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg License: CC BY-SA 3.0 Contributors: Own work Original artist: Viswesr
File:ArduinoDue_Front.jpg Source: https://upload.wikimedia.org/wikipedia/commons/3/36/ArduinoDue_Front.jpg License: CC BYSA 3.0 Contributors: http://arduino.cc/ Original artist: Arduino SA
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File:Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256__(ARM_Cortex-M4F)_MCU.JPG
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%28ARM_Cortex-M4F%29_MCU.JPG License: CC BY-SA 3.0 Contributors: Own work Original artist: Viswesr

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