Quartus

Thc hnh Cu trc my tnh
Trang 1
BI 1 : HNG DN S DNG QUARTUS II

1/- To project :
1. Sau khi ci t xong phn mm QuartusII, bt u chy chng trnh bng cch
double-click vo biu tng
trn desktop.
Giao din QuartusII s xut hin :
2. u tin, cn to mt project mi : File New Project Wizard. ca s u

tin in vo thng tin v th mc cha project, tn project v tn top-module (tn topmodule thng trng tn project). Click Next 2 ln.
GV: TS. Hunh Hu Thun

ThS. Cao Trn Bo Thng
Trang 2
3. Ca s Family & Device Settings dng chn h v tn linh kin FPGA

cu hnh. Chn h linh kin CycloneII, tn EP2C70F896C6 (board DE2-70). Chn
Finish.
4. Vo File New Block Diagram/Schematic File.

5. Click chut phi vo trong thit k, chn Insert Symbol.

Trang 3
Chn cng AND bng cch g vo and2. Bm OK. Gn vo trong thit k.
6. Lm tng t bc 5 gn input (ng vo) v output (ng ra) cho thit k (c

th dng phm Ctrl copy). a chut vo chn ca linh kin v thc hin ni dy.
7. t tn cho input v output (input : in1, in2; output : out) bng cch doubleclick vo symbol.
8. Cui cng ta c hnh cng AND vi input v output, chn File Save, tn
file : congand.

Trang 4
9. Bin dch thit k chn Processing Start Compilation
10. Nu khng c li, s xut hin ca s bo successful. Bm OK.
* M phng thit k
11. Vo File New Vector Waveform File.
12. Click chut phi vo ca s Name. Chn InsertInsert Node or Bus.

Trang 5
13. Chn Node Finder. Ca s Node Finder chn Pins: all v bm List. Chn tt
c cc chn. Bm OK 2 ln.
14. V dng sng cho cc ng input bng hp cng c bn tri
15. Zoom out, dng cc biu tng ln 1 v xung 0 v cc ng tn hiu ng

vo. Lu li vi tn file : congand.vwf.

Trang 6
16. Vo Processing Start Simulation m phng.
17. Kt qu dng sng thu c.
* Cu hnh cho FPGA trn DE2-70

18. Thc hin map chn cho FPGA : vo Assignments Assignment Editor
19. Map chn cho 2 ng vo ca cng AND vi nt gt SW[0] v SW[1], ng ra

ni vi led LEDR[0].

Trang 7
20. Sau khi map chn xong, Save v Compile li mt ln na. cu hnh cho
FPGA: chn Tools Programmer
21. Bm Start. Sau khi chy 100%, FPGA c cu hnh xong. Kim tra li
hot ng ca thit k trn kit DE2-70.
Bi tp : Thay i cc cng logic OR, XOR, NAND, NOR, XNOR v kim tra bng
chn tr ca chng trn DE2-70.
* Tham kho :
www.altera.com
www.terasic.com

Trang 8
BI 2 : THIT K MCH CNG, TR 4 BIT

Hu ht cc thit k u c thc hin theo m hnh phn cp. M hnh phn cp
s dng cc sub-module kt hp vi nhau trong mt top-module to thnh thit k
hon chnh.
1. Chy chng trnh bng cch double-click vo biu tng
trn desktop.
2. To mt project mi c tn : cong4bit.
3. u tin cn to mch cng 1 bit gm Half Adder v Full Adder : File New
Block Diagram/Schematic File.
4. Thc hin thit k mch cng 1 bit HA nh trong hnh :
Lu li vi tn : HA.bdf.
5. Tip tc, thc hin thit k mch cng 1 bit FA.

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Lu li vi tn file : FA.bdf.
6. To symbol (ng gi thit k) cho file FA.bdf v HA.bdf bng cch vo File
Create/Update Create Symbol File for Current File.
7. Thc hin thit k mch cng 4 bit bng cch ghp 4 module mch cng 1 bit
li vi nhau. Vo File New Block Diagram/Schematic File.
8. Thm module mch cng 1 bit vo : Insert Symbol FA (hoc HA).

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HA
B
A
Cout
S
inst1
FA
B
A
Cin
Cout
S
inst
FA
B
A
Cin
Cout
S
inst2
FA
B
A
Cin
Cout
S
inst3
9. Ghp 4 module cng 1 bit li to thnh mch cng 4 bit.
10. Thm vo cc input v output. Cc input l A, B dng bus (4 ng). Cc

output l S dng bus (5 ng). t tn cho cc input A, B bng cch double-click vo
input, phn Pin name g vo : A[3..0] v B[3..0]. Tng t cho output S[4..0].
11. V cc ng bus (

) v dy ni (
) cho mch.
Trang 11
12. Click chut phi vo ng bus v dy ni, chn Properties t tn cho

chng theo hnh.
13. Lu li vi tn : cong4bit.bdf.
* M phng thit k
14. Bin dch thit k chn Processing Start Compilation.
15. To ra Vector Waveform File nh sau :

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16. Thay i h c s ca A, B v S bng cch click chut phi vo A, B hoc S.

Chn Properties. Trong Radix chn Unsigned Decimal (thp phn khng du).
17. V dng sng cho A v B bng cng c thit lp gi tr ty
18. Vo Processing Start Simulation m phng.


20. Thc hin map chn cho FPGA : vo Assignments Assignment Editor

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21. Map chn cho 2 ng vo A, B vi 8 nt gt v ng ra S vi 5 led .

iSW[0]
iSW[1]
iSW[2]
iSW[3]
iSW[4]
iSW[5]
iSW[6]
iSW[7]
PIN_AA23
PIN_AB26
PIN_AB25
PIN_AC27
PIN_AC26
PIN_AC24
PIN_AC23
PIN_AD25
oLEDR[0]
oLEDR[1]
oLEDR[2]
oLEDR[3]
oLEDR[4]
oLEDR[5]
oLEDR[6]
oLEDR[7]
PIN_AJ6
PIN_AK5
PIN_AJ5
PIN_AJ4
PIN_AK3
PIN_AH4
PIN_AJ3
PIN_AJ2
22. Sau khi map chn xong, Save v Compile li mt ln na. cu hnh cho
FPGA: chn Tools Programmer.
23. Bm Start. Sau khi chy 100%, FPGA c cu hnh xong. Kim tra li
hot ng ca thit k trn kit DE2-70.
Bi tp : Thit k mch cng/tr 4 bit v cu hnh trn DE2-70.
* Tham kho :
www.altera.com
www.terasic.com

Trang 14
BI 3 : THIT K MCH NHN

Cch thc hin php nhn 3 bit cho 2 s A v B, kt qu l S :
Thit k mch nhn Baugh Wooley 3 bit nh sau :

trn desktop.
2. To mt project mi c tn : nhan3bit.
3. u tin cn to mch cng 1 bit gm Half Adder v Full Adder : File New
Block Diagram/Schematic File.
4. Thc hin thit k mch cng 1 bit HA nh trong hnh :
Lu li vi tn : HA.bdf
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5. Tip tc, thc hin thit k mch cng 1 bit FA.
Lu li vi tn file : FA.bdf
6. To symbol (ng gi thit k) cho file FA.bdf v HA.bdf bng cch vo File
7. Thc hin thit k mch nhn 3 bit bng cch ghp cc module mch cng 1 bit
cng vi cng AND li vi nhau. Vo File New Block Diagram/Schematic File.
8. Thm module mch cng 1 bit vo : Insert Symbol FA (hoc HA).

Trang 16
9. Ghp 3 module FA v 3 module HA li to thnh mch nhn 3 bit.

output l S dng bus (6 ng). t tn cho cc input A, B bng cch double-click vo
input, phn Pin name g vo : A[2..0] v B[2..0]. Tng t cho output S[5..0].
11. V cc ng bus (

) v dy ni (
) cho mch.
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chng.
13. Lu li vi tn : nhan3bit.bdf
* M phng thit k

15. Map chn cho 2 ng vo A, B vi 6 nt gt v ng ra S vi 6 led .
iSW[0]
iSW[1]
iSW[2]
iSW[3]
iSW[4]
iSW[5]
iSW[6]
iSW[7]
PIN_AA23
PIN_AB26
PIN_AB25
PIN_AC27
PIN_AC26
PIN_AC24
PIN_AC23
PIN_AD25
oLEDR[0]
oLEDR[1]
oLEDR[2]
oLEDR[3]
oLEDR[4]
oLEDR[5]
oLEDR[6]
oLEDR[7]
PIN_AJ6
PIN_AK5
PIN_AJ5
PIN_AJ4
PIN_AK3
PIN_AH4
PIN_AJ3
PIN_AJ2
16. Sau khi FPGA c cu hnh xong. Kim tra li hot ng ca thit k trn
kit DE2-70.
Bi tp : Thit k mch bnh phng 3 bit v cu hnh trn DE2-70.
* Tham kho :
www.altera.com
www.terasic.com

Trang 18
BI 4 : THIT K MCH SO SNH 4 BIT

Mch so snh 2 s 4 bit c thc hin theo biu thc logic sau :
(A=B)
(A3=B3) (A2=B2) (A1=B1) (A0=B0)
(A>B)
(A3>B3) + (A3=B3) (A2>B2) + (A3=B3) (A2=B2) (A1>B1) +

(A3=B3) (A2=B2) (A1=B1) (A0>B0)
trn desktop.
2. To mt project mi c tn : sosanh4bit.
3. u tin cn to mch so snh 1 bit : File New Block Diagram/Schematic
File.
4. Thc hin thit k mt mch so snh 1 bit nh trong hnh :
Cc input l : A, B, G; output l : AlonB, AbangB.

5. Lu li vi tn file : sosanh1bit.bdf
6. To symbol (ng gi thit k) cho file sosanh1bit.bdf bng cch vo File

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7. Thc hin thit k mch so snh 4 bit bng cch ghp 4 module mch so snh 1
bit li vi nhau. Vo File New Block Diagram/Schematic File.
8. Thm module mch so snh 1 bit vo : Insert Symbol sosanh1bit.
9. Ghp 4 module so snh 1 bit li to thnh mch so snh 4 bit.

Trang 20

output l ABangB v AlonB. t tn cho cc input A, B bng cch double-click vo
input, phn Pin name g vo : A[3..0] v B[3..0].
11. V cc ng bus (
) v dy ni (
) cho mch.

chng.
13. Lu li vi tn : sosanh4bit.bdf
* M phng thit k

15. Map chn cho 2 ng vo A, B vi 8 nt gt v 2 ng ra AbangB, AlonB vi 2
led .
iSW[0]
iSW[1]
iSW[2]
iSW[3]
iSW[4]
PIN_AA23
PIN_AB26
PIN_AB25
PIN_AC27
PIN_AC26

oLEDR[0]
oLEDR[1]
oLEDR[2]
oLEDR[3]
oLEDR[4]
PIN_AJ6
PIN_AK5
PIN_AJ5
PIN_AJ4
PIN_AK3

iSW[5]
iSW[6]
iSW[7]
PIN_AC24
PIN_AC23
PIN_AD25
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oLEDR[5]
oLEDR[6]
oLEDR[7]
PIN_AH4
PIN_AJ3
PIN_AJ2
kit DE2-70.
Bi tp : Kho st mch so snh trong th vin ca QuartusII (vo Megafunction
arithmetic lpm_compare)
* Tham kho :
www.altera.com
www.terasic.com

Trang 22
BI 5 : THIT K MCH A HP
Biu thc logic cho b a hp 2-1 1 bit :
m = x s ys
u tin, ta s thit k mt b a hp 2-1 8 bit

desktop.
trn
2. To mt project mi c tn : machdahop
3. u tin cn to mch a hp 2-1 1 bit : File New Block Diagram/
Schematic File.
4. Thc hin thit k mch a hp 2-1 1 bit nh trong hnh :
Lu li vi tn : dahop1bit.bdf
5. To symbol (ng gi thit k) cho file dahop1bit.bdf bng cch vo File
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6. Thc hin thit k mch a hp 2-1 8 bit bng cch ghp cc module
mch a hp 2-1 1 bit li vi nhau.
7. Kt qu dng sng thu c :

Trang 24

8. Map chn cho 2 ng vo X, Y vi 16 nt gt, ng vo S vi 1 nt gt, v ng ra
M vi 8 led .
iSW[0]
iSW[1]
iSW[2]
iSW[3]
iSW[4]
iSW[5]
iSW[6]
iSW[7]
iSW[8]
iSW[9]
iSW[10]
iSW[11]
iSW[12]
iSW[13]
iSW[14]
iSW[15]
PIN_AA23
PIN_AB26
PIN_AB25
PIN_AC27
PIN_AC26
PIN_AC24
PIN_AC23
PIN_AD25
PIN_AD24
PIN_AE27
PIN_W5
PIN_V10
PIN_U9
PIN_T9
PIN_L5
PIN_L4
iSW[16]
iSW[17]
PIN_L7
PIN_L8
oLEDR[0]
oLEDR[1]
oLEDR[2]
oLEDR[3]
oLEDR[4]
oLEDR[5]
oLEDR[6]
oLEDR[7]
PIN_AJ6
PIN_AK5
PIN_AJ5
PIN_AJ4
PIN_AK3
PIN_AH4
PIN_AJ3
PIN_AJ2
kit DE2-70.
Bi tp : Thit k mch a hp 4-1 3 bit
m A.Sel1.Sel 0 B.Sel1.Sel 0 C.Sel1.Sel 0 D.Sel1.Sel 0

* Tham kho :
www.altera.com
www.terasic.com

Trang 25
BI 6 : THIT K ALU
u tin, ta s thit k mt b ALU gm 2 chc nng : AND v cng.

1. To mt project mi c tn : alu8bit
2. To b ALU 1 bit nh hnh di (gm 1 cng AND, 1 b cng FA, 1 b
a hp 2-1 1 bit). Lu li vi tn file : alu1bit.bdf

Trang 26
3. Thc hin thit k b ALU 8 bit bng cch ghp 8 b ALU 1 bit li vi
nhau.
Lu li vi tn : alu8bit.bdf
4. Kt qu m phng :

5. Map chn cho 2 ng vo A, B vi 16 nt gt, ng vo S vi 1 nt gt, v ng ra
Result vi 8 led .


iSW[0]
iSW[1]
iSW[2]
iSW[3]
iSW[4]
iSW[5]
iSW[6]
iSW[7]
iSW[8]
iSW[9]
iSW[10]
iSW[11]
iSW[12]
iSW[13]
iSW[14]
iSW[15]
PIN_AA23
PIN_AB26
PIN_AB25
PIN_AC27
PIN_AC26
PIN_AC24
PIN_AC23
PIN_AD25
PIN_AD24
PIN_AE27
PIN_W5
PIN_V10
PIN_U9
PIN_T9
PIN_L5
PIN_L4
Trang 27
iSW[16]
iSW[17]
PIN_L7
PIN_L8
oLEDR[0]
oLEDR[1]
oLEDR[2]
oLEDR[3]
oLEDR[4]
oLEDR[5]
oLEDR[6]
oLEDR[7]
PIN_AJ6
PIN_AK5
PIN_AJ5
PIN_AJ4
PIN_AK3
PIN_AH4
PIN_AJ3
PIN_AJ2
kit DE2-70.
Bi tp : Thit k b ALU 4 bit gm 5 chc nng : cng, tr, NAND, OR, XOR
* Tham kho :
www.altera.com
www.terasic.com

Trang 28
BI 7 : THANH GHI, B M
* Flip-flop T
1. Chy chng trnh bng cch double-click vo biu tng QuartusII trn
Desktop.
2. To project c tn FlipFlopT.
3. Vo File New Block Diagram/Schematic File.

4. Click chut phi vo trong thit k, chn Insert Symbol.

Trang 29
5. G tff vo name OK
6. Thm cc input, output v t tn tn hiu cho schematic nh trong hnh.
7. Lu li vi tn FlipFlopT
8. Bin dch thit k: Processing Start Compilation

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9. Nu khng c li, s xut hin ca s bo successful. Bm OK.

10. Vo File New Vector Waveform File.
11. Click chut phi vo ca s Name. Chn InsertInsert Node or Bus.

12. Chn Node Finder.
13. Ca s Node Finder chn Pins: all v bm List. Chn tt

c cc chn. Bm OK 2 ln.

Trang 31
14. V dng sng cho chn Clock: la chn tn hiu Clock v s dng cng
c to sng.
15. Qui nh chu k cho xung Clock OK

Trang 32
16. V dng sng cho cc tn hiu khc theo hnh sau.
17. Lu file dng sng.

18. M phng (Processing Start Simulation)
19. Quan st dng sng v nhn xt lin h gia Q v cc tn hiu khc
20. Cho bit mi lin h gia Q v Clock khi cc tn hiu khc mc cao.
21. Map chn cho Clock vi KEY (nt bm), CLRN, PRN, T vi 3 switch (nt
gt) v ng ra Q vi n led. Bin dch v cu hnh xung board DE2-70.
Bi tp : Kho st cc flip flop khc: flip flop D (tn trong th vin l dff), cht
(tn trong th vin l latch).
* Thanh ghi/ Thanh ghi dch

Trong mt CPU, ngoi ALU cn c cc thanh ghi (register), n v iu
khin (control unit) v b nh cache.

Trang 33
1. To mt project mi c tn : thanhghidich8bit
2. Thanh ghi dch c cu to t cc flip flop D (DFF), do thit k
mt thanh ghi dch 8 bit ta s dng 8 flip flop D ghp li. Lu li vi tn file :
thanhghidich8bit.bdf
3. Kt qu m phng
4. Map chn cho CLK l nt bm (KEY), IN l nt gt (SWITCH), S l 8

n led. Bin dch v cu hnh xung board DE2-70.
5. Thit k thanh ghi bng cch sa li thit k
6. M phng, map chn v cu hnh xung board DE2-70.

Trang 34
* B m
1. To mt project mi c tn : dem4bit
2. B m c cu to t cc flip flop T (TFF), do thit k mt
thanh ghi 4 bit ta s dng 4 flip flop T ghp li. Lu li vi tn file : dem4bit.bdf
3. M phng, map chn v cu hnh xung board DE2-70.
* Tham kho :
www.altera.com
www.terasic.com

Trang 35
BI 8 : B NH
Trong mt h thng my tnh, b nh l thnh phn ng vai tr rt quan
trng v khng th thiu. B nh c s dng cha m lnh (vng nh lnh)
v d liu (vng nh d liu) nhm phc v cho CPU trong qu trnh x l.
C 2 loi b nh chnh : ROM v RAM (u c h tr trong th vin ca
Quartus II)
* RAM
1. To mt project mi c tn : ram8byte
2. Chn New Block Diagram. Vo Tools MegaWizard Plug-In
Manager. Click Next.
3. Trong Memory Compiler, chn RAM 1-PORT. t tn file : ram. Bm

Next.
Do b nh ca RAM l 8 byte nn rng bus d liu l 8 bit, bus a ch

l 3 bit. Ln lt thit lp cc ty chn theo cc hnh sau.

Trang 36
Bm Finish.
4. Ly b nh RAM va to ra v gn cc input v output vo. Lu li vi
tn file : ram8byte.bdf
5. M phng


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Thc hnh Cu trc my tnh

BI 1 : HNG DN S DNG QUARTUS II

Giao din QuartusII s xut hin :

2. u tin, cn to mt project mi : File New Project Wizard. ca s u

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

3. Ca s Family & Device Settings dng chn h v tn linh kin FPGA

4. Vo File New Block Diagram/Schematic File.

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

Chn cng AND bng cch g vo and2. Bm OK. Gn vo trong thit k.

6. Lm tng t bc 5 gn input (ng vo) v output (ng ra) cho thit k (c

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

9. Bin dch thit k chn Processing Start Compilation

10. Nu khng c li, s xut hin ca s bo successful. Bm OK.

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

14. V dng sng cho cc ng input bng hp cng c bn tri

15. Zoom out, dng cc biu tng ln 1 v xung 0 v cc ng tn hiu ng

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

16. Vo Processing Start Simulation m phng.

17. Kt qu dng sng thu c.

* Cu hnh cho FPGA trn DE2-70

19. Map chn cho 2 ng vo ca cng AND vi nt gt SW[0] v SW[1], ng ra

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

BI 2 : THIT K MCH CNG, TR 4 BIT

1. Chy chng trnh bng cch double-click vo biu tng

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

9. Ghp 4 module cng 1 bit li to thnh mch cng 4 bit.

10. Thm vo cc input v output. Cc input l A, B dng bus (4 ng). Cc

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

12. Click chut phi vo ng bus v dy ni, chn Properties t tn cho

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

16. Thay i h c s ca A, B v S bng cch click chut phi vo A, B hoc S.

17. V dng sng cho A v B bng cng c thit lp gi tr ty

18. Vo Processing Start Simulation m phng.

* Cu hnh cho FPGA trn DE2-70

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

21. Map chn cho 2 ng vo A, B vi 8 nt gt v ng ra S vi 5 led .

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

BI 3 : THIT K MCH NHN

Thit k mch nhn Baugh Wooley 3 bit nh sau :

Thc hnh Cu trc my tnh

5. Tip tc, thc hin thit k mch cng 1 bit FA.

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

9. Ghp 3 module FA v 3 module HA li to thnh mch nhn 3 bit.

10. Thm vo cc input v output. Cc input l A, B dng bus (3 ng). Cc

GV: TS. Hunh Hu Thun

Thc hnh Cu trc my tnh

12. Click chut phi vo ng bus v dy ni, chn Properties t tn cho

* Cu hnh cho FPGA trn DE2-70