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INTRODUCTION TO 8086

INTERRUPTS

THEORY

Interrupt (INT):
There are three types of interrupts. Namely:

1. Hardware Interrupt (External Interrupt):


It occurs as signal on external hardware pins
8086 has 2 pins to accept hardware interrupts: NMI and INTR.

2. Software Interrupt (Special Instruction):


It is caused by writing the software interrupt instruction INTn (where n can be any
value between 0-255)

3. Dedicated Interrupt (Internal Interrupt):


It is produced by programs. 8086 is interrupted when some special condition occurs
while executing certain instructions in the program.

Hardware Interrupt:
Lets see the two ways where we get hardware interrupts, namely
1. NMI
2. INTR
If NMI line receives an INT, microprocessor executes INT2.
If INTR line receives an INT, MP executes two INTA pulses:
During the 1st INTA: the interrupting device calculates the vector number.
During the 2nd INTA: the interrupting device sends the vector number N to the
microprocessor.
Handling hardware interrupt:
If IF (INT FLAG) =0, then INT is masked (masked means not taken).
If IF (INT FLAG) =1, then INT is unmasked.

Software Interrupt:
Here when this type of interrupt comes, following steps are followed by the
microprocessor:
Decrease SP (stack pointer) by 2 and push flag registers on stack.
Disable INT input by clearing IF in the flag register.
Reset the TF (trap flag) in flag register.
Decrease SP by 2 and push current CS (code section) register content on stack.
Decrease SP by 2 and push current IP (instruction pointer) register content on
stack.
Jump to new address of the ISR (Interrupt service routine) by getting new value
of CS and IP from IVT (interrupt vector table).
8086 will execute ISR.
An IRET at the end of an ISR return executes to main program.
8086 will restore IP & CS register content from stack.
8086 will also restore flag register from the stack.
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INTRODUCTION TO 8086

INTERRUPTS

THEORY

Handling a software interrupt:


Main Program
Push Flags
INTn

Clear IF
Clear TF
PUSH CS
PUSH IP
FETCH ISR
Address

HLT
IRET
POP IP
POP CS
POP FLAGS

ISR

IRET

INTRODUCTION TO 8086

INTERRUPTS

THEORY

Interrupt Vector Table (IVT):


IVT contains ISR address for 256 interrupts.
Each ISR address is stored as CS & IP.
As each ISR address is of 4 bytes . Each ISR address requires 4 locations to be stored.
There are 256 INTURRUPTS: INT0 INT255.
Total size of IVT is 1KB.
`

INT0- Divide Error

INT1- Single Stepping


INT2- NMI
INT3- Breakpoint
INT4- Interrupt on overflow
INT5
.
.
- Reserved
.
INT31
INT32
.
.
- User Defined
.
INT255
(INT0-INT4) Dedicated interrupts.
INT0

INT1

Reserved for divide instruction error.


INT occurs when there is a
o division error
o result too large
o divisor is very small as compared to the dividend/divisor=0
o ISR is used to show error message on screen
Reserved for single step.
Microprocessor executes this interrupt after every instruction if TF=1.
This is helpful during debugging.
ISR generally displays contents of all registers.
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INTRODUCTION TO 8086

INTERRUPTS

INT2

Reserved for hardware interrupt NMI.


Microprocessor executes this ISR in response to an INT on the NMI line

INT3

Reserved for breakpoint interrupt.


Used to cause breakpoint in program.
Useful in debugging large program where single stepping is inefficient.
Its ISR is used to display the content of all register on screen.

INT4

THEORY

Reserved for overflow INT.


This interrupt occurs if the overflow flag is set and microprocessor executes INT0
instruction.
Used to detect overflow error in signed arithmetic
OF (overflow flag) =0 (microprocessor is not interrupted).
OF=1 (microprocessor is interrupted).

INT5 INT31
Reserved interrupts.
Reserved by INTEL for higher processors.
INT32 INT255
User defined interrupts.
Interrupt written by user to service various user defined conditions.
Interrupts are invoked by writing INTn.