Viterbi Decoder Node Synchronization Design Example v1.0.

0 README
File
This readme file for the Viterbi Decoder Node Synchronization Design
contains
information about the design example posted on the Altera Support
website:
http://www.altera.com/support/examples/exm-index.html
Ensure that you have read the information on the design example web
page
before using the example.

This readme file contains the following sections:

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Package Contents
Tool Requirements
Quartus II Compilation
ModelSim Simulation Models
Core Directory Names
Release History
Design Examples Disclaimer
Contacting Altera

Package Contents
================
Viterbi Decoder Node Synchronization Design Example v1.0.0
Design files in the zip download include:
o viterbi_node_sync.vhd - Top-level design file
o ber_node_sync.vhd - Wrapper file for ber_threshold and
rotate_node_sync blocks
o viterbi_BER.vhd Wrapper file for Viterbi decoder
implemented using the Viterbi Compiler intellectual property (IP)
block
o ber_threshold.vhd Monitors the bit error rate (BER) and
determines if system is in or out of sync
o rotate_node_sync.vhd Rotates encoded symbols based on
decision made from the ber_threshold block
o viterbi_node_sync_testbench.vhd Testbench for RTL
simulation
o run_script.tcl - TCL script to set up project for running
functional simulation using ModelSim
Tool Requirements
=================
This design example requires the following software package:
o Quartus II 4.1 or later
o Viterbi Compiler v4.1.0
o ModelSim version 5.8c or later
Please contact your local sales representative if you do not have one
of these
software tools.

Quartus II Compilation
======================
To run the compilation for the Viterbi Decoder Node Synchronization
project in Quartus II,
perform the following steps:
1. Open Quartus II project: File -> Open Project ->
..\Quartus_II\viterbi_node_sync.qpf
2. Specify the Viterbi Compiler user library: Assignments -> Settings
-> Category (User Libraries)
Browse to the <path>\viterbi-v4.1.0\lib in the Library name box.
3. Review Viterbi Compiler parameters using IP Toolbench: Tools ->
MegaWizard Plug-in Manager
Select "Edit an existing custom megafunction variation" and choose
the Viterbi IP block:
../source/viterbi_BER.vhd
You can review the parameters by clicking on the "Parameterize"
button in IP Toolbench.
4. Regenerate the Viterbi core files by clicking on the "Generate"
button in IP Toolbench.
5. You are ready to compile the design in Quartus II: Processing ->
Start Compilation
To get more details on the Viterbi Compiler IP, refer to the Viterbi
Compiler User Guide
located at:
http://www.altera.com/literature/ug/ug_viterbi-compiler.pdf
ModelSim Simulation Models
==========================
In IP Toolbench, the option to generate VHDL simulation model is
enabled in the "Set Up Simulation" window.
The steps to generate the simulation models from IP Toolbench are
highlighted in the previous section:
"Quartus II Compilation". We will be using these IP Toolbenchgenerated IP functional simulation models
to verify the design in ModelSim.
To run the functional simulation for the Viterbi Decoder Node
synchronization project
using ModelSim, perform the following steps:
1. In ModelSim, change the directory to the Quartus II project
directory: File -> Change Directory
2. Source the TCL script file: Tools -> Execute Macro ->
run_script.tcl
The TCL script sets up the ModelSim project, compiles the
appropriate libraries and design files,
runs the simulation, and displays the result in the waveform
editor.
To get more details on the IP Functional Simulation Models, refer to
the Altera white paper titled

"Using IP Functional Simulation Models to Verify Your System Design

White Paper" located at:
http://www.altera.com/literature/wp/wp_simgen.pdf

Core Directory Names

====================
The default directory for your design example design is
c:\altera\design_examples\viterbi_node_sync,
but you can specify an alternative directory.
Release History
===============
Version 1.0.0
------------Initial release

Design Examples Disclaimer

==========================
These design examples may only be used within Altera Corporation
devices and remain
the property of Altera. They are being provided on an as-is basis
and as an accommodation;
therefore, all warranties, representations, or guarantees of any kind
(whether express,
implied, or statutory) including, without limitation, warranties of
merchantability, non-infringement,
or fitness for a particular purpose, are specifically disclaimed.
Altera expressly does not recommend,
suggest, or require that these examples be used in combination with
any other product not provided
by Altera.

Contacting Altera
=================
Although we have made every effort to ensure that this design example
works
correctly, there might be problems that we have not encountered. If
you have
a question or problem that is not answered by the information
provided in this
readme file or the example's documentation, please contact your
Altera Field
Applications Engineer.
If you have additional questions that are not answered in the
documentation
provided with this function, please contact Altera Applications:

World-Wide Web:
Technical Support Hotline:

http://www.altera.com
http://www.altera.com/mysupport/
(800) 800-EPLD (U.S.)
(408) 544-7000 (Internationally)

Copyright (c) 2004 Altera Corporation. All rights reserved.