6. Explain the operation of SR flip plop.

Figure : 1

Truth table

The NAND basic flip-flop circuit in Figure 1 operates with inputs normally at 1
unless the state of the flip-flop has to be changed. A 0 applied momentarily to the
set input causes Q to go to 1 and Q' to go to 0, putting the flip-flop in the set state.
When both inputs go to 0, both outputs go to 1. This condition should be avoided
in normal operation.

5. What is the difference between Combinational and

Sequential circuits?
Sequential logic circuits have its output based on the inputs and
the present states of the system, while combinational logic
circuits output is based only on the present inputs.
Sequential Logic Circuits have a memory, while combinational
logic circuits do not have the ability to retain data (state)

 Combinational Logic Circuits are used mainly for arithmetic and

Boolean operations, while sequential logic circuits are used for
storage of data.
Combinational logic circuits are built with logic gates as the
elementary device while, in most cases, sequential logic circuits
have (f-fs) as the elementary building unit.
Most sequential circuits are clocked (triggered for operation with
electronic pulses), while combinational logic does not have clocks.

8. Explain Memory organization of PIC Microcontroller.

PIC Memory Organisation:

PIC microcontroller has 13 bits of program memory address.
Hence it can address up to 8k of program memory. The program
counter is 13-bit. PIC 16C6X or 16C7X program memory is 2k or
4k. While addressing 2k of program memory, only 11- bits are
required. Hence two most significant bits of the program counter
are ignored. Similarly, while addressing 4k of memory, 12 bits are
required. Hence the MSb of the program counter is ignored.

Fig Program Memory Map.

Data memory (Register Files):
Data Memory is also known as Register File. Register File consists of two
components.
1. General purpose register file (same as RAM).
2. Special purpose register file (similar to SFR in 8051).

4. Explain the operation of 2 input CMOS logic gates with circuit diagram.
Write the advantages and disadvantages of CMOS logic gate over TTL
logic gate.

This CMOS gate example contains 3 N-channel

MOSFETs, one for each input FET1 and FET2 and one for
the output FET3. When both the inputs A and B are at

logic level 0, FET1 and FET2 are both switched OFF

giving an output logic 1 from the source of FET 3.
When one or both of the inputs are at logic level 1
current flows through the corresponding FET giving an
output state atQ equivalent to logic 0, thus producing
a NAND gate function.
Improvements in the circuit design with regards to
switching speed, low power consumption and improved
propagation delays has resulted in the standard CMOS
4000 CD family of logic ICs being developed that
complement the TTL range.
As with the standard TTL digital logic gates, all the
major digital logic gates and devices are available in
the CMOS package such as the CD4011, a Quad 2input NAND gate, or the CD4001, a Quad 2input NOR gate along with all their sub-families.

Advantages of CMOS: Like TTL logic, complementary MOS (CMOS) circuits take
advantage of the fact that both N-channel and P-channel
devices can be fabricated together on the same substrate
material to form various logic functions.
Disadvantages: COMOS ICs are damaged by static electricity so extra care
must be taken when handling these devices.
Also unlike TTL logic gates that operate on single +5V
voltages for both their input and output levels, CMOS
digital logic gates operate on a single supply voltage of
between +3 and +18 volts.