CS422 Lab Assignment 1

(Mayank Arya 1301CS28)

QUESTION 1
Model the given logic function using Verilog gate level description and design appropriate test bench.
Explanation
Circuit is provided in the problem sheet. We have to use the gates given in the circuit to simulate it.
module lab1_q1(Z, S0, S1, D0, D1, D2, D3);
output Z;
input S0,S1,D0,D1,D2,D3;
not n1(inv_s0,S0);
not n2(inv_s1,S1);
and a1(a1_0,D3,S0,S1);
and a2(a2_0,D1,inv_s0, S1);
and a3(a3_0,D2,S0,inv_s1);
and a4(a4_0,D0,inv_s0, inv_s1);
nor o1(Z,a1_0,a2_0,a3_0,a4_0);
endmodule

Test Bench:
module q1_test();
reg S0, S1, D0, D1, D2, D3;
wire Z;
lab1_q1 uut(Z, S0, S1, D0, D1, D2, D3);
initial
begin
S0 = 1'b0;
S1 = 1'b0;
D0 = 1'b0;
D1 = 1'b0;
D2 = 1'b0;
D3 = 1'b0;
#10;
S0 = 1'b0;
S1 = 1'b1;
D0 = 1'b0;
D1 = 1'b0;
D2 = 1'b0;
D3 = 1'b0;

#10;
S0 = 1'b1;
S1 = 1'b0;
D0 = 1'b0;
D1 = 1'b0;
D2 = 1'b0;
D3 = 1'b0;
#10;
S0 = 1'b0;
S1 = 1'b0;
D0 = 1'b1;
D1 = 1'b0;
D2 = 1'b0;
D3 = 1'b0;
#10;
S0 = 1'b0;
S1 = 1'b0;
D0 = 1'b0;
D1 = 1'b1;
D2 = 1'b0;
D3 = 1'b0;
#10;
S0 = 1'b0;
S1 = 1'b0;
D0 = 1'b0;
D1 = 1'b0;
D2 = 1'b1;
D3 = 1'b0;
#10;
S0 = 1'b0;
S1 = 1'b0;
D0 = 1'b0;
D1 = 1'b0;
D2 = 1'b0;
D3 = 1'b1;
#10;
S0 = 1'b1;
S1 = 1'b1;
D0 = 1'b0;
D1 = 1'b0;
D2 = 1'b0;
D3 = 1'b0;
#10;
S0 = 1'b1;

S1 = 1'b0;
D0 = 1'b1;
D1 = 1'b0;
D2 = 1'b1;
D3 = 1'b0;
#10;
end
initial
begin
$monitor("S0=%b, S1=%b, D0=%b, D1=%b, D2=%b, D3=%b, Z=%b, time=%t\n", S0, S1, D0, D1,
D2, D3, Z, $time);
end
endmodule

QUESTION 2
A car has a fuel level detector that outputs the current fuel level as a 3-bit binary number, with 000
meaning empty and 111 meaning full. Create a simplified logic circuit (use Boolean algebra for
simplification) that illuminates a low fuel indicator light (by setting an output L to 1) when the fuel
level drops below level 3. Develop a Verilog model for the logic and test bench to verify the model.
Explanation
Let the three bit number M2M1M0. The value is greater than 3 is M2 is 1 or equal to three if M2 is 0 and
M1 and M0 both are 1. So output should be 1 if fuel is less than 3.
Output = ~(M2) || ~(M1 && M2)
module lab1_q2(out, m0, m1, m2);
output out;
input m0,m1,m2;
not n1(inv_m2,m2);
nand n2(inv_a1,m0,m1);
and n3(out,inv_a1,inv_m2);
endmodule

Test Bench
module q2_test();
reg m0, m1, m2;
wire out;
lab1_q2 uut(out, m0, m1, m2);
initial
begin

m0 = 1'b0;
m1 = 1'b0;
m2 = 1'b0;
#10;
m0 = 1'b0;
m1 = 1'b0;
m2 = 1'b1;
#10;
m0 = 1'b0;
m1 = 1'b1;
m2 = 1'b0;
#10;
m0 = 1'b0;
m1 = 1'b1;
m2 = 1'b1;
#10;
m0 = 1'b1;
m1 = 1'b0;
m2 = 1'b0;
#10;
m0 = 1'b1;
m1 = 1'b0;
m2 = 1'b1;
#10;
m0 = 1'b1;
m1 = 1'b1;
m2 = 1'b0;
#10;
m0 = 1'b1;
m1 = 1'b1;
m2 = 1'b1;
#10;
end
initial
begin
$monitor("m0=%b, m1=%b, m2=%b, out=%b, time=%t\n", m0, m1, m2, out, $time);
end
endmodule

QUESTION 3
Use a simulation to demonstrate whether or not the following functions are equal. (Be sure to state
which, if any, are equal.) and verify using truth table.
f = a b' + b' c' + a c
g = (b' + c) (a + b + c')
h = b' c' + b c + a c
Explanation
The problem statement states to write a test bench to find which two function are equal or all of them
are equal.
module lab1_q3(f, g, h, a, b, c);
output f,g,h;
input a, b, c;
assign f = a & (~b) + (~b) & (~c) + a & c;
assign g = (~b + c) & (a + b + ~c);
assign h = (~b)&(~c) + b & c + a & c;
endmodule
Test Bench
module q3_test();
reg m0, m1, m2;
wire f,g,h;
lab1_q3 uut(out, m0, m1, m2);
initial
begin
m0 = 1'b0;
m1 = 1'b0;
m2 = 1'b0;
#10;
m0 = 1'b0;
m1 = 1'b0;
m2 = 1'b1;
#10;
m0 = 1'b0;
m1 = 1'b1;
m2 = 1'b0;
#10;
m0 = 1'b0;
m1 = 1'b1;
m2 = 1'b1;
#10;
m0 = 1'b1;

m1 = 1'b0;
m2 = 1'b0;
#10;
m0 = 1'b1;
m1 = 1'b0;
m2 = 1'b1;
#10;
m0 = 1'b1;
m1 = 1'b1;
m2 = 1'b0;
#10;
m0 = 1'b1;
m1 = 1'b1;
m2 = 1'b1;
#10;
end
initial
begin
$monitor("m0=%b, m1=%b, m2=%b, out=%b, time=%t\n", m0, m1, m2, out, $time);
end
endmodule

QUESTION 4
Simulate the following function using appropriate test bench.
Explanation
The problem statement states to write a test bench to find which two numbers are greater, equal or
lesser.
Test Bench
module tb_a1q4();
reg[7:0] a,b;
wire eq,neq,lt,lte,gt,gte;
integer d=0,i;
comparators test(eq,neq,lt,lte,gt,gte,a,b);
initial begin
a=8'b11010011;
b=8'b01101111;
#10;
a=8'b11000111;
b=8'b10000011;
#10;
a=8'b00011111;

b=8'b00011111;
#10;
a=8'b00011111;
b=8'b11000111;
#10;
end
initial begin
$monitor("d = %d,eq = %b,neq = %b,lt = %b,lte = %b,gt = %b,gte = %b,time
= %t\n",d,eq,neq,lt,lte,gt,gte,$time);
end
endmodule

QUESTION 5
A museum has three rooms, each with a motion sensor (m0, m1, m2) that outputs 1 when motion is det
ected. At night, the only person in the museum is one security guard who walks from room to room. Cre
ate a circuit that sounds an alarm (by setting an output A to 1) if motion is ever detected in more than o
ne room at a time (i.e., in two or three rooms), meaning there must be an intruder or intruders in the m
useum. Develop a Verilog model for the above and write a test bench to verify the model.

module lab1_q5(out, m0, m1, m2);

output out;
input m0,m1,m2;
not n1(inv_m0,m0);
not n2(inv_m1,m1);
not n3(inv_m2,m2);
and a1(a1_0,inv_m0, m1, m2);
and a2(a1_1,inv_m1, m0, m2);
and a3(a1_2,inv_m2, m0, m1);
and a4(a1_3,m0, m1, m2);
or o1(out,a1_0,a1_1,a1_2,a1_3);
endmodule
Explanation
If either two of the motion sensor senses person in room at the same time than the alarm is turned on
Test Bench
module q5_test();
reg m0, m1, m2;
wire out;
lab1_q5 uut(out, m0, m1, m2);
initial
begin

m0 = 1'b0;
m1 = 1'b0;
m2 = 1'b0;
#10;
m0 = 1'b0;
m1 = 1'b0;
m2 = 1'b1;
#10;
m0 = 1'b0;
m1 = 1'b1;
m2 = 1'b0;
#10;
m0 = 1'b0;
m1 = 1'b1;
m2 = 1'b1;
#10;
m0 = 1'b1;
m1 = 1'b0;
m2 = 1'b0;
#10;
m0 = 1'b1;
m1 = 1'b0;
m2 = 1'b1;
#10;
m0 = 1'b1;
m1 = 1'b1;
m2 = 1'b0;
#10;
m0 = 1'b1;
m1 = 1'b1;
m2 = 1'b1;
#10;
end
initial
begin
$monitor("m0=%b, m1=%b, m2=%b, out=%b, time=%t\n", m0, m1, m2, out, $time);
end
endmodule

QUESTION 6
Write a structural description of the following schematic. Check the functionality of the circuit by writing
appropriate test bench.

Explanation
The problem statement states to implement the given circuit and write test bench to check for the
same.

module lab1_q6(out1, out2, I0, I1, I2, I3, I4);

output out1,out2;
input I0, I1, I2, I3, I4;
nor n1(op1,I0,I1);
nand n2(op2,I2,I3);
not n3(op3,I4);
not n4(op4,op3);
not n5(op5,op2);
nor n6(op6,op5,op1);
not n7(op7,op4);
or n8(op8,op7,op1);
xnor n9(op9,op6,op4);
nand n10(out1,op7,op2);
not n11(out2,op9);
endmodule

Test Bench
module q6_test();
reg I0, I1, I2, I3, I4;
wire out1, out2;
lab1_q6 uut(out1, out2, I0, I1, I2, I3, I4);
initial
begin
I0 = 1'b0;
I1 = 1'b0;
I2 = 1'b0;
I3 = 1'b0;
I4 = 1'b0;
#10;
I0 = 1'b1;
I1 = 1'b0;
I2 = 1'b0;
I3 = 1'b0;
I4 = 1'b0;
#10;
I0 = 1'b0;
I1 = 1'b1;

I2 = 1'b0;
I3 = 1'b0;
I4 = 1'b0;
#10;
I0 = 1'b0;
I1 = 1'b0;
I2 = 1'b1;
I3 = 1'b0;
I4 = 1'b0;
#10;
I0 = 1'b0;
I1 = 1'b0;
I2 = 1'b0;
I3 = 1'b1;
I4 = 1'b0;
#10;
I0 = 1'b0;
I1 = 1'b0;
I2 = 1'b0;
I3 = 1'b0;
I4 = 1'b1;
#10;
I0 = 1'b1;
I1 = 1'b1;
I2 = 1'b0;
I3 = 1'b0;
I4 = 1'b0;
#10;
I0 = 1'b1;
I1 = 1'b0;
I2 = 1'b1;
I3 = 1'b0;
I4 = 1'b0;
#10;
I0 = 1'b1;
I1 = 1'b0;
I2 = 1'b0;
I3 = 1'b1;
I4 = 1'b0;
#10;
I0 = 1'b1;
I1 = 1'b0;
I2 = 1'b0;
I3 = 1'b0;

I4 = 1'b1;
#10;
I0 = 1'b1;
I1 = 1'b1;
I2 = 1'b1;
I3 = 1'b1;
I4 = 1'b1;
#10;
end
initial
begin
$monitor("I0=%b, I1=%b, I2=%b, I3=%b, I4=%b, out1=%b, out2=%b time=%t\n", I0, I1, I2, I3, I4,
out1, out2, $time);
end
endmodule