ADVANCED PROCESSOR ARCHITECTURES

AND MEMORY ORGANISATION

Lesson-15: DSPs

2008

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education

DSP
Advanced signal processor circuits
MAC (Multiply and Accumulate) unit (s)
provides fast multiplication of two operands
and accumulating results at a single address.
MAC unit computes fast an expression such
as the following summation. yn = (ai
xni) where the sum is made for i = 0, 1, 2,
, N-1. Here i, n and N are the integers, ai is
a coefficient, xj is independent variable or an
input element and yk is the dependent
variable or an output element.

2008

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education

DSP

DSP processors invariably have Harvard architecture.

Caches are organized in Harvard architecture (separate
I-cache and D-Cache
Basic Units: MDR, Internal Bus, Data bus, Address
bus, control bus, Bus Interface Unit, Instruction fetch
register, Instruction decoder, Control unit, Instruction
Cache, Data Cache, multistage pipeline processing,
multi-line superscalar processing for obtaining
processing speed higher than one instruction per clock
cycle, Program counter

2008

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education

Internal Bus

Instruction
Fetch
Unit

Test Unit

Emulation
Unit

Instruction
Dispatch
Unit

Control
Registers

Instruction
Decoder
Unit

2-Level
Caches

Interrupt
Control
Unit

Control
Logic

Bus
Interface
Unit
Register File
A15
A0
A31
A15
L1

S1
+

M1

Register File
B15
B0
B31
B16
D2

D1

M2

S2

L2

+
X

Four 16-Bit MACs/Eight

8-Bit MACs
Serialism
L1 : ALU Auxiliary Logic Unit

L2 : ALU

M1: Multiplier Unit

D1 :Divider Unit

M2: Multiplier
D2 :Divider Unit

S2 : Auxiliary

Core and Special

Structure units in an
Exemplary DSP,
TMS320C64x DSP

Eight 32-Bit
Instruction

2008

RIS Parallelism/
Note: Floating Point Units in C67x

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education

DSP special structural units

2008

Packed Data processing

Parallel Execution MAC units
Special Instructions
Instruction Packing unit

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education

Parallel Processing features

Supports processing instruction level
parallelism as well as memory access
parallelism.

Multiple data accesses in a single
instruction

2008

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education

Summary
We learnt

DSP for digital signal processing

Harvard architecture
MAC (Multiply and Accumulate) unit
VLIW (instruction packaging unit)
TMS320C64x

2008

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education

End of Lesson 15 of Chapter 2

2008

Chapter-2 L15: "Embedded Systems - " , Raj Kamal,

Publs.: McGraw-Hill Education