Chipscope 6 Rev1

ChipScope Pro 6.
1i
2003 Xilinx, Inc. All Rights Reserved
NOTES
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Objectives
After completing this module, you will be able to:
Describe the ChipScope Pro tool and the on-chip debugging and verification
strategy of Xilinx
Specify how to include ChipScope Pro cores into a design
Describe how the ChipScope Pro Analyzer can help you analyze your design
ChipScope Pro - 1 - 3
NOTES
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Outline
Introduction
ChipScope Pro Design Flow
Core Generation
Core Insertion
Analyzer
Summary
NOTES
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Need for On-Chip Debug

Limited internal visibility
Increases overhead
Late in the design cycle
Cannot get internal access
Full scan insertion
IP
Core
Hard IP cores
Pads
IOIO
Pads
How do I access the embedded

system bus?
Custom
Logic
Embedded System Bus
CPU
Core
Custom
Core
IO Pads
IO Pads
Memory
Array
Respins are ENORMOUSLY

expensive
Co-verification
Tools are cumbersome and slow

Modeling issues
Logic BIST Memory BIST Access

Custom Boundary Scan TAP Controller
NOTES
Traditional board-level testing methods are not enough. You need internal access to signals,
nodes, and system buses.
Integrated IP means wider, faster buses, which means you need more I/O pins dedicated to
debug.
You have no direct access to IP within the FPGA. It is difficult to drive high-speed clocks and
signals off-chip without introducing new problems.
The high pin count and the fine-pitch packaging makes accessing pins nearly impossible.
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ChipScope Pro System

FPGA fabric provides full internal visibility
Debug occurs at (or near) system speeds
Access all of the internal signals and

nodes within the FPGA
Access system buses implemented in the
FPGA
Debug on-chip by using the system clock
Minimize pins required for debug
IP
Core
ILA
IBA Custom
Logic
Embedded System Bus
PPC405
Core
Custom ILA
Core
Memory
Array
IO Pads
Pads
IOIO
Pads
ILA
IO Pads
ILA
ICON
Boundary Scan TAP Controller
Access via the JTAG interface

Target
Connection
NOTES
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Core Resource Utilization
For what?
Block Ram Utilization for Virtex-II/-II Pro, Spartan-3
ChipScope Pro cores

utilize FPGA resources
Block RAM: trigger
and data storage
Slice logic: trigger
comparisons
You must leave room for

the ChipScope cores in
the FPGA
Slice Logic Utilization for Virtex-II/-II Pro, Spartan-3
This may require using

a larger part in the same
package than you will
use in production
NOTES
This example shows a single ILA core with a single trigger port, a single basic match unit,
data same as trigger, and 512 data samples.
For block RAM utilization, also note that one extra bit per sample is required for the trigger
mark (e.g., a trigger/data width of 8 bits requires a sample width of 9 bits, etc.).
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System Requirements
Download cables supported:
Parallel Cable III

Parallel Cable IV
MultiLINX (JTAG mode only)
Agilent E5904B TPA
Cables connect to a JTAG header, which is connected to the JTAG pins

of the FPGA device
NOTES
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Outline
Introduction
Core Generation
Core Insertion
Analyzer
Summary
NOTES
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1-9
Using ChipScope Pro
Place the ChipScope Pro cores

into the design
Attach internal nodes for viewing

into the ChipScope Pro core
Generate the ChipScope Pro
cores by using the ChipScope
Pro Core Generator or the
ChipScope Pro Core Inserter
tools
Place and route your design by

using the Xilinx ISE
implementation tools
Download the bitstream into the
device under test, and analyze
the design with the ChipScope
Pro Analyzer software
Core
Generator
Or
Core
Inserter
ChipScope
ChipScopePro
Pro
Core
CoreGenerator
Generator
Instantiate
InstantiateCores
Coresinto
into
Source
SourceHDL
HDL
Connect
ConnectInternal
InternalSignals
Signals
to
toCore
Core(in
(inSource
SourceHDL)
HDL)
Synthesize
Synthesize
ChipScope
ChipScopePro
ProCore
Core
Inserter
Inserter(into
(intonetlist)
netlist)
Synthesize
Synthesize
Implement
Implement
Download
Download&&Debug
Debug
Using
UsingChipScope
ChipScopePro
ProAnalyzer
Analyzer
NOTES
ChipScope Pro in-circuit verification may require that your verification be run at slower
speeds to accommodate the ChipScope Pro cores. This still provides faster functional
verification than simulation and greater internal visibility than traditional board-level in-circuit
verification.
Timing will change when the cores are removed. There is no way to predict how the timing
will change, but due to the removal of the ChipScope Pro core resources, the timing results
will change. If you were meeting timing while using ChipScope Pro cores, you must still be
able to meet timing. If you were not meeting timing while using ChipScope Pro cores, your
timing may improve. However, it should be noted that there is no way to accurately state what
will happen for certain. That is, your timing may get worse.
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Core Generator Flow
The Core Generator generates

cores that are instantiated
directly into the HDL
ChipScope
ChipScopePro
Pro
Core
CoreGenerator
Generator
Allows access to all HDL

nodes
Requires changes to the code
Must comment-out cores to
remove them
Standard implementation flow
Core generation and insertion
are performed separately
All cores are available
Instantiate
InstantiateCores
Coresinto
into
Source
SourceHDL
HDL
Connect
ConnectInternal
InternalSignals
Signals
to
toCore
Core(in
(inSource
SourceHDL)
HDL)
Synthesize
Synthesize
Implement
Implement
Download
Download&&Debug
Debug
Using
UsingChipScope
ChipScopePro
ProAnalyzer
Analyzer
NOTES
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Core Inserter Flow
The Core Inserter inserts cores

directly into the netlist
HDL code is untouched

Only post-synthesis nodes are
available
Bypass this tool to remove
cores
The Core Inserter must
perform the first portion of
translate
Core generation and insertion
are performed together
The ChipScope Pro Core
Inserter is run from within ISE
Only ICON, ILA, and ILA/ATC
cores are currently supported
Synthesize
Synthesize
ChipScope
ChipScopePro
ProCore
Core
Inserter
(into
Inserter (intonetlist)
netlist)
Implement
Implement
Download
Download&&Debug
Debug
Using
UsingChipScope
ChipScopePro
ProAnalyzer
Analyzer
NOTES
The IBA/OPB, IBA/PLB and VIO cores are currently not supported in the Core Inserter.
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Core Types
ICON (Integrated Control core): This core controls up to fifteen capture

cores (below)
The ICON core interfaces between the JTAG interface and the capture cores
Capture cores: Customizable cores for creating triggers and data storage
Customizable number, width, and storage of trigger ports
ILA (Integrated Logic Analyzer core): Capture core for HDL designs
ILA/ATC (Integrated Logic Analyzer with Agilent Trace Core): Similar to the ILA
core, but data is captured off-chip by the Agilent Trace Port Analyzer
IBA/OPB (Integrated Bus Analyzer for the IBM CoreConnect On-Chip
Peripheral Bus core): This is the capture core for debugging CoreConnect OPB
buses
IBA/PLB (Integrated Bus Analyzer for CoreConnect Processor Local Bus core):
Similar to the IBA/OPB core, except for the PLB bus
VIO (Virtual Input/Output core): Defines and generates virtual I/O ports
NOTES
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ILA Pro Cores
You can select 1 to 16 trigger ports
Up to 256 channels per trigger port
Multiple match units on the same

trigger port
Up to 16 match units
( No more than 16 total)
For example, 4 trigger ports with

4 match units each = 16 match
conditions
You can define the trigger ports
Control signal triggers

Address trigger (bit-masking and
range)
External trigger port
Cascading multiple cores
Trigger time stamps

Window gap information
Match and trigger counters
Multi-state trigger sequencing
NOTES
Ports and match units are more flexible than they were in 4.2i. The total can be up to 16, in
ANY configuration.
Gap information is the amount of time elapsed between triggers. There is a 32, 40, or 48 bit
counter that you can set. Time begins at the first trigger. Max value is about a weekend, give
or take.
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ATC (Agilent Trace Cores)
Agilent Trace Core
Out of Block RAM? Need more than 16K

samples?
ATC provides a capture depth of up to twomillion samples at 200 MHz

As easy to use as ILA Pro cores
Create a core with the same set of ILA Pro

parameters
Specify Time-Division Multiplexing details for the

Agilent FPGA Trace Port Analyzer
Transmit rate (1X, 2X, 4X), number of data

pins (4, 8, 12, 16, 20)
Data width (up to 75 channelsrelative to

rate and pins)
JTAG
Trace
FPGA TPA
LAN
ChipScope
Pro
NOTES
The ATC data sheet and the user manual are available on the Web at
www.xilinx.com/chipscope.
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ChipScope VIO Core
VIO (Virtual I/O) core
Insert virtual pins into your design
VIO
ASYNC_IN
ASYNC_OUT
SYNC_IN
SYNC_OUT
CLK
Outputs of the VIO core are used

to drive internal design signals
Outputs are virtual DIP switches
Force value or pulse train into FPGA

Inputs to the VIO core are used to monitor internal signals
Inputs are virtual LEDs
Different refresh rates available

Synchronous or Asynchronous I/O
Up to 256 bits each
Available only with the ChipScope Pro generator flow
NOTES
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Outline
Introduction
Core Generation
Core Insertion
Analyzer
Summary
NOTES
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ICON Core
ChipScope Pro Core Generator
1 Start the ChipScope Pro Core
Generator, select Core Type
2 Set General Options
NOTES
Number of Control Portsup to 15.
Disable Boundary Scan Component Instance: The boundary scan component extends the
JTAG interface of the FPGA device so that up to two internal scan chains can be created. The
ChipScope Pro Analyzer communicates with the ChipScope Pro cores by using one of the two
internal scan chains (USER1 or USER2).
The boundary scan component is instantiated inside the ICON core by default. Use the
Disable Boundary Scan Component Instance checkbox to disable the instantiation of the
boundary scan component.
Disabling JTAG Clock BUFG Insertion: By default, this clock is placed on a global clock
resource (BUFG). To disable this BUFG insertion, check the Disable JTAG Clock BUFG
Insertion checkbox. This must checked only when global resources are very scarce; placing
the JTAG clock on regular routing introduces skew. Ensure the design is adequately
constrained to minimize this skew.
Including Boundary Scan Ports: The ICON core uses only one of the USER1 or USER2
scan chain ports. The unused USER2 or USER1 port signals are available for use by other
design elements. If the boundary scan component is instantiated inside the ICON core, then
selecting the Include Boundary Scan Ports checkbox provides access to the unused USER1
or USER2 scan chain interfaces. Note: The boundary scan ports must be included only if the
design needs them. If they are included and not used, it can cause errors during synthesis or
implementation.
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Generate ICON Core

3 Set Template Options
ICON
control0
control1
control2
control3
control4
control5
...
control15
NOTES
You can create a batch mode argument example file (for example, icon.arg) by selecting the
Generate Batch Mode Argument Example File (.arg) checkbox. The icon ARG file is used
with the command line program called generate.exe. The icon ARG file contains all of the
arguments necessary for generating the ICON core, without using the ChipScope Pro Core
Generator GUI tool.
Note: An ICON core can be generated by running generate.exe icon_pro -f=icon.arg at the
command prompt on Windows systems or by running generate.sh icon_pro -f=icon.arg
at the UNIX shell prompt on Solaris systems.
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ILA Core Generation

ChipScope Pro Core Generator
Generator, select Core Type
2 Set General Options
NOTES
Output Netlist: Browse to set the location where the netlist must be saved.
Device Settings: Use SRL16s will reduce the amount of logic used. Use RPMs will create a
faster core.
Clock Settings: Trigger on the rising or falling edge of the clock.
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Trigger Options
Number of input trigger ports:

1 to 16
Equals: TRIG0TRIGn
#Trigger Ports * #Match Units
Trigger Width: number of inputs

for each trigger
TRIG0, TRIG1, TRIG15
Number of Match Units Used: 1 to

16 per core
3 Set Trigger Options
From 1 to 256
Match Units: number of matching

triggers for TRIGn input
NOTES
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Match Type
3
Set Trigger Options
NOTES
Trigger width: The number of input signals used in the triggerfrom 1 to 256.
Counter Width: The match unit counter is a configurable counter on the output of the each
match unit in a trigger port. This counter can be configured at run time to count a specific
number of match unit events. To include a match counter on each match unit in the trigger
port, select a counter width from 1 to 32. The match counter will not be included on each
match unit if the Counter Width combo box is set to Disabled. The default Counter Width
setting is Disabled.
Enable Trigger Output Port : The output of the ILA-trigger-condition module can be
brought out to a port signal by checking the Enable Trigger Output Port checkbox. The
trigger output port is used to trigger external test equipment by attaching the port signal to a
device pin in the HDL design. The trigger output port can also be attached to other logic or to
ChipScope Pro cores in the design to be used as a trigger, an interrupt, or another control
signal. The shape (level or pulse) and sense (active-High or active-Low) of the trigger output
can also be controlled at run time. The clock latency of the ILA trigger output port is 10 clock
(CLK) cycles, with respect to the trigger input ports.
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Trigger Sequencer
The trigger condition can be either

a Boolean equation or an optional
trigger sequencer
The transition from one level to the
next is caused by an event on one
of the match units that is
connected to the trigger sequencer
Set Trigger Options
Maximum of 16 levels
NOTES
The sequencer match units and states are set in ChipScope Pro Analyzer.
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Data Storage Options
Data Depth: number of samples to

store: 512 to 16384
Aggregate Data Width: up to 256
bits (total of all trigger port widths)
Data Same As Trigger: data and
trigger ports are identical
Set Data Options
If data is not same as trigger, a 32bit data port is created for storing
data
NOTES
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Generate Core
5 Set Template Options
control
clk
trig0
trig1
trig2
trig3
ILA
...
trig15
NOTES
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Example Core Template

- ------------------------------------------------------------------------------------------------------------------------------------ -- - ILA
ILAcore
corecomponent
componentdeclaration
declaration
- -----------------------------------------------------------------------------------------------------------------------------------component
componentila
ila
port
port
( (control
control : :inin std_logic_vector(35
std_logic_vector(35downto
downto0);
0);
clk
: :inin std_logic;
clk
std_logic;
trig0
:
in
std_logic_vector(7
downto
0);
trig0
: in std_logic_vector(7 downto 0);
trig1
: :inin std_logic_vector(7
trig1
downto0);
0);
trig2
trig2
downto0);
0);
trig3
trig3
downto0);
0);
trig4
trig4
downto0);
0);
trig5
trig5
downto0);
0);
trig6
trig6
downto0);
0);
trig7
trig7
downto0));
0));
end
endcomponent;
component;
- ------------------------------------------------------------------------------------------------------------------------------------ -- - ILA
ILAcore
coreinstance
instance
- -----------------------------------------------------------------------------------------------------------------------------------i_ila
i_ila: :ila
ila
port
portmap
map
(control
(control =>
=>control,
control,
clk
=>
clk
=>clk,
clk,
trig0
=>
trig0,
trig0
=> trig0,
trig1
=>
trig1
=>trig1,
trig1,
trig2
=>
trig2
=>trig2,
trig2,
trig3
=>
trig3
=>trig3,
trig3,
trig4
=>
trig4
=>trig4,
trig4,
trig5
=>
trig5
=>trig5,
trig5,
trig6
=>
trig6
=>trig6,
trig6,
trig7
=>
trig7
=>trig7);
trig7);
NOTES
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Using ICON/ILA Core

6
Instantiate cores
Connect the CONTROL port signal of the ILA core to an unused control
port of the ICON core instance in the design
Connect the triggers and the CLK to the ILA core
Connect all unused bits of the data and trigger port signals of the ILA core to
0
This prevents the mapper from removing the unused trigger or data
signals, and it avoids any DRC errors during the implementation process
Ensure the data and trigger source signals are synchronous to the ILA clock
signal (CLK)
NOTES
Other cores (ILA/ATC, IBA/OPB, IBA/PLB, and VIO), similarly, must be connected to the
ICON control ports.
Similarly, for other cores, connect inputs to 0 so that the mapper does not remove the unused
inputs.
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Outline
Introduction
Core Generation
Core Insertion
Analyzer
Summary
NOTES
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Using Inserter from ISE

1 Create a CDC file (ChipScope
Definition and Connection file)
Project New Source, select

ChipScope Definition and
Connection File
Click Next, associate with the
appropriate top-level design file
2 To open the ChipScope Pro Core

Inserter, double-click the CDC file in
the Sources in Project window
For the greatest ease in connecting

cores, preserve hierarchy during
synthesis
NOTES
The ChipScope Pro Inserter tool can be used with an HDL-based design or used with an
existing EDIF netlist.
ChipScope Pro Inserter can also be used separately from ISE. That is, you can create the core
by starting ChipScope Pro Core Inserter outside of ISE.
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ICON Core Insertion

Inserter, set Device Options
4 Select setup options, then click New

ILA Unit or New ILA/ATC Unit
NOTES
Disabling JTAG Clock BUFG Insertion: By default, this clock is placed on a global clock
resource (BUFG). To disable this BUFG insertion, check the Disable JTAG Clock BUFG
Insertion checkbox. This should be done only when global resources are very scarce; placing
the JTAG clock on regular routing introduces skew. Ensure the design is adequately
constrained to minimize this skew.
Useful Project Navigator Settings when using ChipScope Pro Core Inserter
The following are useful Project Navigator settings to help you implement a design with the
ChipScope Pro Core Inserter (not required with the Core Generator):
1. If you use the XST synthesis tool, enable the Keep Hierarchy option, to preserve the
design hierarchy. Using the Keep Hierarchy option preserves the names of nets and other
recognizable components, which otherwise could be optimized away. To keep the design
hierarchy:
a. Right-click Synthesize and select the Properties option.
b. Ensure the Keep Hierarchy option is checked, and click OK.
2. Prior to using the ChipScope Pro Analyzer to download your bitstream into your device,
ensure the Bitstream Generation options are set properly:
a. In the Project Navigator, right-click Generate Programming File and select the
Properties option.
b. Select the Startup options tab.
c. Set the FPGA Start-Up Clock dropdown to JTAG Clock.
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Trigger and Capture Parameters

5 Click Next, then select the
Trigger Parameters tab
6 Select the Capture Parameters tab
NOTES
These parameters are the same as those shown for the ChipScope Pro Core Generator flow.
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Modify Connections
7 Click the Net Connections tab, then click Modify Connections
NOTES
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Connect Triggers and Data

8
Specify the signal connections to the Trigger/Data ports of the capture core
A Select triggers
B Select internal signals
C Click Make Connections
NOTES
For the Core Generator flow, complete this step when you instantiate the ILA core into the
design and connect the internal signals to the instantiated component.
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Implement with
Inserted Cores
9 Click Return to Project Navigator to implement the design
with inserted cores
NOTES
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Comparing the Two Flows

Flow #1 (Core Generation) Flow #2 (Core Inserter)
HDL code is modified
Only post-synthesis nodes

are available
Cores must be commented out Bypass ILA Inserter tool
of HDL to be removed
to remove cores
Standard implementation Inserter performs first
flow is used
portion of Translate
Core generation and insertion Core generation and
are done separately
insertion are done
together
All cores available for
Only ICON, ILA, and
instantiation
ILA/ATC cores available
Every node is available
NOTES
Given that you only need ICON, ILA, and ILA/ATC cores, the Core Inserter flow is the
simpler flow to use.
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Outline
Introduction
Core Generation
Core Insertion
Analyzer
Summary
NOTES
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ChipScope Pro Analyzer
Provides an easy-to-use graphical interface
Communicates via Parallel Cable III / IV and MultiLINX

Match types
FPGA download
ILA capture setup and trigger modifications
Waveform display for captured traces
Can write the waveforms to VCD format for other waveform viewers
= (equal to), <> (not equal to), > (greater than), >= (greater than or
equal to), < (less than), <= (less than or equal to)
Match values
X (any value), 0 (zero), 1 (one), R (rising edge), F (falling edge),B

(any edge)
NOTES
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Start ChipScope Pro Analyzer

1 Start the ChipScope
Pro Analyzer
2 Power-on the board. Open the

Cable/Search JTAG Chain
The software searches the JTAG chain

for devices in the chain, click OK
NOTES
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Configure the Device

3 Select Device Configure
<device to configure>
4 Select the file (BIT) to download, click

OK
The bitstream is downloaded
NOTES
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Setup Trigger Match Values

5 Double-click Trigger Setup
6 Select the Match Unit, Function

type, and Value for the trigger
NOTES
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Specify Active Triggers

7 Click Add to specify Triggers
Click Add again for each

additional trigger
Only ONE Trigger can be

active at a time
8 Double-click Trigger
Condition Equation to
enable additional
Boolean equations or
sequence of events for
a trigger condition. Click
OK
NOTES
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Specify Capture Settings

9 Specify N Samples, or Window
settings for capture data display
N Samples defines the

number of samples to
show for each trigger
Window defines the
number of windows and
data samples (Depth) per
trigger
NOTES
Type: The Type combo box in the capture settings defines the type of windows to use. If
Window is selected, the number of samples in each window must be a power of two.
However, the trigger can be in any position in the window. If N Samples is selected, the
buffer will have as many windows as possible, with the defined samples per trigger. The
trigger will always be the first sample in the window if N Samples is selected.
Windows (Windows): The number of windows is specified in this field and can be any
positive integer from 1 to the depth of the capture buffer.
Windows Depth: The Depth combo box defines the depth of each capture window. It is
automatically populated with valid selections when values are typed into the Windows text
field. Only powers of two are available.
Windows Position: The Position field defines the position of the trigger in each window.
Valid values are integers from 0 to the depth of the capture buffer minus 1.
N Samples Samples Per Trigger: Samples per trigger defines how many samples to capture
once the trigger condition occurs. Valid values are any positive integer from 1 to the depth of
the capture buffer. The trigger mark will always appear as sample 0 in the window. There will
be as many sample windows captured as possible, given the overall sample depth.
Note: When occurring in at least n cycles or occurring for at least n consecutive cycles is
selected for a match unit, and that match unit is a part of the overall trigger condition, the
Window Depth or Samples Per Trigger cannot be less than 8. This is due to pipeline effects
inside the ILA, ILA/ATC, or IBA core.
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Setup Waveform
10
Double-click Waveform
Signals can be
renamed and
grouped, right-click
and select
{Rename | Add to
Bus}
NOTES
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Begin Acquisition
11 Select Trigger Setup Run (or F5) to begin acquisition
Triggers are shown, , with
corresponding data values
NOTES
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Bus Plotting and Data Lists
Bus Plotting
Data versus time

Data versus data
The Bus Plot
window displays
buses as a graph
of the values of
the bus over time,
or one the values
one bus versus
another bus
Listing
The Listing
window displays
the sample buffer
as a list of values
in a table
NOTES
ChipScope Pro
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VIO Console in Analyzer
VIO Console provides control over Virtual I/O ports
Right-click input signals to change input type
View
activity
View
internal
signal
values
Note, to use VIO cores, you must use the Core Generator Flow
NOTES
Whenever a new input value is entered, it is updated at once. However, if you want all inputs
updated simultaneously (except pulse train), select Update Static button.
Input Types
Text Field: Enter the text value of the input.
Push Button: Select either high or low as default value. Click and hold the button to toggle
the value.
Toggle Button: Click button to toggle the value.
Pulse Train: Enter the train of values to run through on each clock cycle:
Single Pulse: Pulse high for single clock cycle.
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Outline
Introduction
Core Generation
Core Insertion
Analyzer
Summary
NOTES
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Review Questions
What are some advantages to using ChipScope Pro for debug?
What are the two flows for including ChipScope Pro cores into a design?
What are the differences in the two flows?
For each flow, how do you include the cores in the design?
What can you do with the ChipScope Pro Analyzer?
NOTES
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Answers
What are some advantages to using ChipScope Pro for debug?
You can view any internal signal

Circumvents traditional debugging, which requires more I/O
Functional debug at (or near) system speed
Required I/O for ChipScope Pro? JTAG Pins
What are the two flows for including ChipScope Pro cores into a design?
Core Inserter
Core Generator
NOTES
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Answers
What are the differences in the two flows?
Flow #1 (Core Generation) Flow #2 (Core Inserter)

HDL code is modified
Only post-synthesis nodes

are available
Cores must be commented out Bypass ILA Inserter tool
of HDL to be removed
to remove cores
Standard implementation Inserter performs first
flow is used
portion of Translate
Core generation and insertion Core generation and
are done separately
insertion are done
together
All cores available for
Only ICON, ILA, and
instantiation
ILA/ATC cores available
Every node is available
NOTES
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Answers
For each flow, how do you include the cores in the design?
Core Generator:
Core Inserter:
Instantiate cores into HDL

The software inserts the cores into the netlist
What can you do with the ChipScope Pro Analyzer?
Configure the device

Setup and activate triggers
View the waveforms of internal data
Use the VIO console to drive internal signals and view virtual outputs
NOTES
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Review Question
Given this simple FSM, buried deep in the design, answer the questions on the
following page:
Simple bitstream pattern search

for 101
If the input signal find is 1,

search for 101 in the bitstream
In-circuit verification requirements:
We need to monitor the

output fnd_seq
We would like to set a sequence
trigger for fnd_seq and bitstream
but store the value of the state registers
That is, data is NOT equal to triggers

Assume OHE FSM
We would like to control the state machine by driving the inputs find, bitstream,
and arst
NOTES
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Review Questions
Which flow (Core Inserter or Core Generator) is required? Why?
What type of cores are required and how many of each? Why?
How many control ports are required?
How many trigger ports are required? Why? What is the width of each
trigger port?
NOTES
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Answers
Which flow (Core Inserter or Core Generator) is required? Why?
Core Generator, because we would like to drive the input signals, thus
requiring a VIO core, which can only be used through the Core Generator
What type of cores are required and how many of each? Why?
ICON: controls the other cores

ILA: used to set triggers and store data
VIO: used to drive inputs to the FSM
One of each
NOTES
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Answers
How many control ports are required?
Two. One for the ILA core and one for the VIO core
How many trigger ports are required? Why? What is the width of each
trigger port?
Two. We would like to create a trigger sequence

Width:
TRIG0: 1 bit for bitstream

TRIG1: 1 bit for fnd_seq
A 32-bit (default size) data port is also created for storing state register data
NOTES
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Summary
Debug and verification is often the largest part of a design process

On-chip tools are required to verify complex designs
ChipScope Pro provides tools for on-chip access to signals, nodes,
and system buses
ChipScope Pro is integrated with the ISE software, allowing designers to
design with verification in mind at each step of the design process
NOTES
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Where Can I Learn More?
To purchase ChipScope Pro tools:

www.xilinx.com/ise/verification/cs_pro_get.htm
With Parallel Cable IV, ~$800 (as of 02/2004)
ChipScope Pro page: www.xilinx.com/chipscope

ChipScope Pro Documentation: mysupport.xilinx.com Documentation
ChipScope User Manuals
NOTES
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Trademark Information
"Xilinx" and the Xilinx logo are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.
The shadow X shown above is a trademark of Xilinx, Inc.
CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064,XC3090, XC4005, XC5210 are registered Trademarks of
Xilinx, Inc.
ACE Controller, ACE Flash, A.K.A Speed, AllianceCORE, Alliance Series, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX,
Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL
Bencher, IRL, JBits, J Drive, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze,
PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, Rocket I/O, SelectI/O, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP,
SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Wave Table, WebPACK,
WebFITTER, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +,
XChecker, XDM, XEPLD, XSI, XtremeDSP, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XC designated products and ZERO+ are trademarks of Xilinx,
Inc.
The Programmable Logic Company is a service mark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under
its trademarks, patents, copyrights, or maskwork rights or any rights of others.
Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx,
Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx, Inc. devices and
products are protected under one or more of the Patents in the United States and other foreign countries.
Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx,
Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc.
will not assume any liability for the accuracy or correctness of any engineering or software support or
assistance provided to a user.
Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx
product in such applications without the written consent of the appropriate Xilinx officer is prohibited.
Copyright 1991-2004 Xilinx, Inc. All Rights Reserved.
NOTES
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ChipScope Pro
Labs
Introduction
NOTES
ChipScope Pro Lab Intro
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Objectives
After completing these labs, you will be able to:
Use the ChipScope Pro Core Generator

Instantiate ChipScope Pro Cores into an HDL design
Verify a design by using the ChipScope Pro Analyzer
Use the ChipScope Pro Core Inserter
ChipScope Pro Lab Intro - 2a - 3
NOTES
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Lab Design: Simple

Binary Counter
The lab design is a simple four-bit binary counter
Two clock dividers are used to reduce the four-bit counter frequency, such
that each bit can be viewed on LEDs
Inputs: clk, reset, sync_reset, load, load_data(3:0)
Outputs: cnt4(3:0)
NOTES
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Lab Design:
System Requirements
System requirements for this lab
ISE 6.1, ChipScope Pro 6.1
ISE 6.1 sp1, sp2, and sp3 are also ok
Compatible ChipScope Pro devices: Virtex, Virtex-E, Virtex-II, Virtex-II

Pro, Spartan -II, Spartan_IIE, and Spartan-3
JTAG header is connected to compatible device
Compatible cable: MultiLINX (JTAG mode only), Parallel Cable III,
Parallel Cable IV, Agilent E5904B TPA
Lab instructions are written for Windows users
NOTES
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Lab Overview
Two lab versions: Core Generator OR Core Inserter
Core Generator:
Create and instantiate ChipScope Pro cores

Implement
Open the ChipScope Pro Analyzer to configure the device
Perform in-circuit verification
Core Inserter:
Create ChipScope Pro cores

Implement
Open the ChipScope Pro Analyzer to configure device
Perform in-circuit verification
NOTES
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Lab 1: ChipScope Pro

Core Generator
General Flow
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Create ISE design

Generate cores
Instantiate cores in the design
Implement the design
In-circuit verification (ChipScope Pro Analyzer)
NOTES
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General Flow
Step 1:
Step 2:
Step 4:
Step 5:
Create ISE design

Generate cores
Implement design
In-circuit verification (ChipScope Pro Analyzer)
NOTES
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Evaluation
Thank you for viewing this recorded e-Learning (REL)

Please give us your feedback on this module
Go to the Enrollments window, where you see a list of your enrollments
Click Class Evaluation
A list of evaluations awaiting your response appears
Click Evaluation for ChipScope Pro

Simply follow the instructions and submit the evaluation
To complete the evaluation later and go directly to the lab, go to
ftp://ftp.xilinx.com/pub/documentation/education/chipscope-6-rev1-prnt.zip
NOTES
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ChipScope Pro Lab

Core Generator
ChipScope Pro Lab: Core Generator

Introduction
This lab will take you through the primary steps required to use ChipScope Pro to functionally
verify your design in-circuit. You can choose to perform either a Verilog-based or VHDL-based
design.
System requirements for this lab
Compatible software

Compatible ChipScope Pro device
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan_IIE, and Spartan-3
JTAG header is connected to compatible device

Compatible cable
MultiLINX (JTAG mode only), Parallel Cable III, Parallel Cable IV, Agilent E5904B
TPA
Lab instructions are written for Windows users.
Objectives
After completing this lab, you will be able to:
Use the ChipScope Pro Core Generator
Instantiate ChipScope Pro cores into an HDL design
Procedure
This lab comprises five primary steps: you will create an ISE design, generate cores, instantiate
cores into the design, implement the design, and finally perform in-circuit verification. Below
each general instruction for a given procedure, you will find accompanying step-by-step directions
and illustrated figures providing more detail for performing the general instruction. If you feel
confident about a specific instruction, feel free to skip the step-by-step directions and move on to
the next general instruction in the procedure.
Note: You can download the lab files for this module from the Xilinx FTP site at
ChipScope Lab: Core Generator
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Create ISE Design
Step 1
Create a new ISE project named cs_pro in

c:\training\chipscope_pro\labs\CSPro_CoreGen. Specify the device you are using
on your board (must be one of the following device families: Virtex, Virtex-E,
Virtex-II, Virtex-II Pro, Spartan-II, Spartan_IIE, and Spartan-3). Add a
counter (V or VHD) and a counter (UCF) to the project from
c:\training\chipscope_pro\labs\CSPro_CoreGen.
Click Start Programs Xilinx ISE 6 Project Navigator
Click File New Project. Use the following settings:
Project Location: Browse to c:\training\chipscope_pro\labs\CSPro_CoreGen

Project Name: cs_pro
Top Level Module Type: HDL
Click Next. Enter your device information, select XST as the synthesis tool, and select
VHDL or Verilog as your simulation language
Click Next two times. Under Add existing sources, click Add Source.
Browse to c:\training\chipscope_pro\labs\CSPro_CoreGen and select counter.v/.vhd and
counter.ucf. Click Open
When the Choose Source Type window pops up, select VHDL/Verilog Design File, and
click OK
Click Next, click Finish
Generate Cores
Step 2
Start the ChipScope Pro Core Generator. Create an ICON core with the following
parameters:
Output netlist: c:\training\chipscope_pro\labs\CSPro_CoreGen
Device Family: This is dictated by the device you are using
Number of Control Ports: 2
Generate HDL Example File: Checked
HDL Language: Based on your design preferences
Synthesis Tool: Xilinx XST
Click Start Programs ChipScope Pro 6.1 ChipScope Pro Core Generator
Under Select Core Type To Generate, select ICON, click Next
For Design Files Output Netlist, click Browse and browse to
c:\training\chipscope_pro\labs\CSPro_CoreGen. Click Save
Select the correct Device Family based on your device
Under Icon Parameters, Number of Control Ports, select 2. Click Next
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Check Generate HDL Example File. Select the correct HDL Language for your design
(VHDL or Verilog). For Synthesis Tool, select Xilinx XST.
Click Generate Core. Click Start Over
This will start this tool over again for the next core we create.
Create an ILA core with the following parameters:

Output netlist: c:\training\chipscope_pro\labs\CSPro_CoreGen
Use SRL16s and RPMs: Checked
Number of Input Trigger Ports: 3
TRIG0 Trigger Width: 1
Data Depth: 512
Data Same as Trigger: Checked
Under Select Core Type To Generate, select ILA, click Next
Select the correct Device Family, based on your device. Leave User SRL16s and User
RPMs checked
For Clock Settings, select Sample On Rising Edge of Clock. Click Next
For Number of Input Trigger Ports, select 3
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Edit each trigger to match the following settings (also shown in Figure 1):

Leave all the other settings at their default values
Figure 1. Trigger Port Settings
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Click Next. For Data Depth, select 512 Samples. Check Data Same As Trigger. Results
are as shown in Figure 2. Click Next
Figure 2. Data Port Settings

(VHDL or Verilog). For Synthesis Tool select Xilinx XST
Click Generate Core. Click Start Over
This will start this tool over again for the next core we create.
Create a VIO core with the following parameters:

Output Netlist: c:\training\chipscope_pro\labs\CSPro_CoreGen
Use SRL16s: Checked
Enable Synchronous Input Port: Checked
Enable Synchronous Input Port Width: 28
Enable Synchronous Output Port: Checked
Enable Synchronous Output Port Width: 6
Sample on Rising Edge of Clock
Under Select Core Type To Generate, select VIO, click Next
Select the correct Device Family, based on your device. Leave User SRL16s checked
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For Input/Output Port Settings, select the following settings (shown in Figure 3):
Enable Synchronous Input Port: Checked

Enable Synchronous Input Port Width: 28
Enable Synchronous Output Port: Checked
Enable Synchronous Output Port Width: 6
Figure 3. VIO Input/Output Port Settings

Select Sample on Rising Edge of Clock. Click Next
(VHDL or Verilog). For Synthesis Tool select Xilinx XST
Click Generate Core
Instantiate Cores in the Design
Step 3
Using your favorite HDL editor, copy and paste the ICON module (Verilog only),
component (VHDL only), signal or wire declarations, and instance from
c:\training\chipscope_pro\labs\CSPro_CoreGen\icon_xst_example(.v/.or .vhd) to
the file c:\training\chipscope_pro\labs\CSPro_CoreGen\counter(.v/.vhd).
Use your favorite HDL editor to open the file
c:\training\chipscope_pro\labs\CSPro_CoreGen\counter.v/.vhd
c:\training\chipscope_pro\labs\CSPro_CoreGen\icon_xst_example.v/.vhd
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Copy and paste
For Verilog users: copy and paste the ICON module to the top of the counter.v file.
For VHDL users: copy and paste the ICON component to the declarative region of the
counter architecture (rtl).
Copy and paste
For Verilog users: copy and paste the ICON wire declarations to the module.
For VHDL users: copy and paste the ICON signal declarations to the declarative region
of the counter architecture (rtl).
Copy and paste
For Verilog users: copy and paste the ICON instance to the module.
For VHDL users: copy and paste the ICON instance into counter architecture (rtl).
Save counter.v/.vhd
Using your favorite HDL editor, copy and paste the ILA module (Verilog only),
component (VHDL only), and instance from
c:\training\chipscope_pro\labs\CSPro_CoreGen\ila_xst_example(.v/.vhd) into the
file c:\training\chipscope_pro\labs\CSPro_CoreGen\counter(.v/.vhd). Edit the
VHDL and Verilog port connections to match the code snippets shown in Figure
4 (Verilog) and Figure 5 (VHDL).
c:\training\chipscope_pro\labs\CSPro_CoreGen\ila_xst_example.v/.vhd
Copy and paste
For Verilog users: copy and paste the ILA module to the top of the counter.v file.
For VHDL users: copy and paste the ILA component to the declarative region of the
Copy and paste
For Verilog users: copy and paste the ILA instance to the module
For VHDL users: copy and paste the ILA instance into counter architecture (rtl).
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Edit the Verilog and VHDL port connections to match those below, in Figure 4 (Verilog) or
Figure 5 (VHDL)
Figure 4. Verilog ILA Core Instance
Figure 5. VHDL ILA Core Instance

Save counter.v/.vhd
Using your favorite HDL editor, copy and paste the VIO module (Verilog only),
component (VHDL only), and instance from
c:\training\chipscope_pro\labs\CSPro_CoreGen\vio_xst_example(.v/.vhd) into the
file c:\training\chipscope_pro\labs\CSPro_CoreGen\counter(.v/.vhd). Edit the
VHDL and Verilog port connections to match the code snippets shown in Figure
6 (Verilog) and Figure 7 (VHDL).
c:\training\chipscope_pro\labs\CSPro_CoreGen\vio_xst_example.v/.vhd
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Copy and paste
For Verilog users: copy and paste the VIO module to the top of the counter.v file.
For VHDL users: copy and paste the VIO component to the declarative region of the
Copy and paste
For Verilog users: copy and paste the VIO instance to the module
For VHDL users: copy and paste the VIO instance into counter architecture (rtl).
Edit the Verilog and VHDL port connections to match those below, in Figure 6 (Verilog) or
Figure 7 (VHDL)
Figure 6. Verilog VIO Core Instance
Figure 7. VHDL VIO Core Instance

Save counter.v/.vhd
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Add the signal declarations shown in Figures 8 (Verilog) and 9 (VHDL) to

counter(.v/.vhd). Edit the signal assignments as shown in Figures 10 (Verilog)
and 11 (VHDL). Save counter(.v/.vhd).
Scroll and add
Verilog users: In the counter.v file, scroll to the top of the module (declarative region)
and add the following core wire declarations, as shown in Figure 8.
VHDL users: In the counter.vhd file, scroll to the end of the architecture declarative
region and add the following core signal declarations, as shown in Figure 9.
Figure 8. Verilog Core Wire Declrations
Figure 9. VHDL Core Signal Declarations

Scroll and edit
Verilog users: In the counter.v file, scroll to the continuous assignments, and edit the
assignments to match the following figure, Figure 10.
Figure 10. Verilog Assignment Edits

These edits are made to allow the virtual inputs from the VIO core to control the input
signals to the counter.
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VHDL users: In the counter.vhd file, scroll to the beginning of the architecture (after the
begin statement), and edit the signal assignments to match the following figure, Figure
11.
Figure 11. VHDL Assignment Edits

These edits are made to match the VIO and ILA core signal types. The reset conversion
must be converted to a std_logic_vector (0 downto 0). The sync_in and sync_out signals
must be concatenated before being assigned to the VIO ports. Additionally, the
sync_reset, load_data, and load signals are ORd with the inputs to allow the virtual
inputs to control the counter.
Save counter.v/.vhd
Implement the Design
Step 4
Edit the UCF file to match your board I/O and clock speed. Implement the design
and generate the programming file.
In the Project Navigator Sources in Project window, select counter.ucf
In the Processes for Source window, expand User Constraints, double-click Edit
Constraints (Text)
Edit the I/O pin constraints to match your board-level I/O
Edit the Period and Offset In/Out constraints to match your clock period. Generally, the
Offset In/Out should be safe if set and one-half of the period of the clock
In the Sources in Project window, select counter.vhd
In the Processes for Source window, double-click Generate Programming File
This will synthesize the design, implement the design, and generate the programming file.
Now you are ready to start using the ChipScope Pro Analyzer.
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In-Circuit Verification (ChipScope Pro Analyzer)
Step 5
Open the ChipScope Pro Analyzer, and program your device.

In the Project Navigator Processes for Source window, double-click Analyze Design Using
Chipscope to open the ChipScope Pro Analyzer console
Click the Open Cable/Search JTAG Chain button in the top-left corner of the ChipScope
Pro Analyzer window, as shown in Figure 12. Click OK in the JTAG pop-up window
Figure 12. Open Cable/Search JTAG Chain Button

ChipScope Pro Analyzer will poll the JTAG chain and find the parts available for
programming. It will also report these results.
Select Device (menu) Configure <Device to program>
In the JTAG Configuration window, click Select New File. Browse to
c:\training\chipscope_pro\labs\CSPro_CoreGen, and select counter.bit. Click Open
In the JTAG Configuration window, click OK
This will program the device and initialize the Trigger Setup window and the Waveform
window.
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Setup Trigger values as shown in Figures 14 to 16, below.

If the Trigger Setup window is not open, in the New Project window (upper-left corner),
expand JTAG Chain, expand Device (your device number), expand ILA Unit, and doubleclick Trigger Setup, as shown in Figure 13
Figure 13. Open Trigger Setup Window

In the Trigger Setup window, Match console, edit the trigger values to match those shown in
Figure 14, below
MO: TriggerPort0 is attached to the asynchronous reset.

M1: TriggerPort1 is attached to the cnt4 outputs.
M2: TriggerPort2 is attached to the eight-bit counter div_cntr2 (used as the clock enable
when it reaches hex value FF).
Figure 14. Trigger Values

In the Trigger Setup window, Trigger console, click Trigger condition M0. This opens the
Trigger Condition editor. Note the available settings. Click OK
In the Trigger Setup window, Trigger console, click the Add button. This will create
Trigger Condition1 (you can edit this name by clicking it). Click M0 for trigger
Condition1 to edit the Trigger Condition editor
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Deselect Enable for M0 Match Unit and Enable the M1 Match Unit (result shown in
Figure 15). Click OK
Figure 15. Trigger Conditions for Trigger Condition1

Note: You can create Boolean equations by combining multiple match units to create a
trigger.
Repeat instructions 4 and 5 and create a trigger for Match Unit M2. Click the Active button
for Trigger Condtion2. Your Trigger Setup window should now look like that shown in
Figure 16
This will make this the active triggeronly one trigger can be active at any one timewhen
we setup and run the triggers.
Figure 16. Final Trigger Setup Window Values
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Edit Waveform signal names and create buses, as shown in Figure 18. Save the
ChipScope Pro Analyzer project as cs_analyzer.cpj.
If the Waveform window is not open, in the New Project window (upper-left corner),
expand JTAG Chain, expand Device (your device number), expand ILA Unit, and doubleclick Waveform window.
The DataPorts represent the following HDL connections:
DataPort[0]: reset
DataPort[4:1]: cnt4
DataPort[12:5]: div_cntr2
To edit the names, in the Signals window, in the left-hand pane of the Analyzer window,
expand Trigger Ports, and expand each trigger port. For Trigger Port 0, right-click CH: 0,
and select Rename. Enter reset and click Enter (or Return) on your keyboard
Repeat instruction 2 for Trigger Port1 and Trigger Port 2, using the names shown below in
Figure 17
Figure 17. Signal Names Pane

In the Waveform window, use click-shift-click to select all of the cnt4 signals, right-click
one of the cnt4 signals and select Add to Bus New Bus. Right-click the newly created bus
(BUS_0), and select Rename. Enter cnt4[3:0] and click OK

Select the individual cnt4 signals and press Delete on your keyboard
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Repeat instructions 4 and 5 for div_cntr2, creating a bus named div_cntr2[7:0]. The
resulting Waveform Bus/Signal pane should look like that shown in Figure 18
Figure 18. Resulting Bus/Signal Pane

Save the project settings (this will allow these changes to be loaded again at a later date) by
selecting File Save Project. Browse to c:\training\chipscope_pro\labs\CSPro_CoreGen.
Enter the name cs_analyzer.cpj. Click Save
Activate and run triggers. Experiment with triggers.

Select Trigger Setup (menu) Run, or simply press F5 button on the keyboard. This will
activate the Active trigger and update the Waveform window when the trigger is satisfied.
Figure 19. Resulting Waveform Window

Press F5 several more times to view the changes to cnt4
Experiment with trigger values and settings, and re-run the triggers. You can also try Ctrl-F5
or select Trigger Setup (menu) Trigger Immediate (this will immediately active the
trigger and update the Waveform window)
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1-877-XLX-CLAS
2b-18
Edit VIO Console signal names to match those shown in Figure 21, on page 20.
Open the VIO console by double-clicking VIO Console in the Project pane, as shown below
in Figure 20
Figure 20. Open VIO Console

The SyncIn inputs represent the following HDL signals:
SyncIn[3:0]: cnt4[3:0]
SyncIn[11:4]: div_cntr2[7:0]
SyncIn[27:12]: div_cntr1[15:0]
The SyncOut outputs represent the following HDL input signals:
SyncOut[3:0]: load_data
SyncOut4: load
SyncOut5: sync_reset
Shift-click SyncIn[0] to SyncIn[3]. Right-click and select Add to Bus New Bus. Rightclick the newly created bus, BUS_0, and select Rename. Enter cnt4 and select OK
Repeat instruction 2 for SyncIn[4] to SyncIn[11]. Name this bus div_cntr2
Repeat instruction 2 for SyncIn[12] to SyncIn[27]. Name this bus div_cntr1
Repeat instruction 2 for SyncOut[0] to SyncOut[3]. Name this bus load_data
Right-click SyncOut[4] and select Rename. Enter load and click OK
Repeat instruction 6 for SyncOut[5]. Name this signal sync_reset
Right-click Load and select Type Toggle Button
This will allow you to toggle the value of load by clicking the button to the right.
Right-click sync_reset and select Type Push Button High
This creates a push button that will toggle the value of this signal while you click and hold
this signal. The active value of this signal is High. The default, therefore, is Low.
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2b-19

Click-and-drag the signals to match what is shown below, in Figure 21
Figure 21. VIO Console
Change the values of the VIO signals and view the results in the console.
Edit the load_data text value to hex F. Click Load. View the change to cnt4. It should now
have the value hex F. Click the Load value again to enable the counter to count up
Click and hold the sync_reset value button. This should reset the cnt4 value to 0. Release
sync_reset, and cnt4 should continue to count
Experiment with different values of load data. Experiment with different types for the
sync_reset, load, and load_data signals
Click File Save Project
For more experimenting, change the code to create an up/down counter, or count by 2, or
various other things. Add an up/down control signal to the VIO core and experiment.
Conclusion
ChipScope Pro is an extremely powerful tool that will you save time and money. The
capabilities covered in this lab are just the tip of the iceberg. Have fun with this powerful tool!
www.xilinx.com
1-877-XLX-CLAS
2b-20
ChipScope Pro Lab

Core Inserter
ChipScope Pro Lab: Core Inserter

Introduction
This lab will take you through the primary steps required to use ChipScope Pro to functionally
verify your design in-circuit. You can choose to perform either a Verilog-based or VHDL-based
design.
System requirements for this lab:
Compatible Software

Compatible ChipScope Pro device
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan_IIE, and Spartan-3
JTAG header connected to a compatible device

Compatible cable
MultiLINX (JTAG mode only), Parallel Cable III, Parallel Cable IV, Agilent E5904B
TPA
Lab instructions are written for Windows users
Objectives
After completing this lab, you will be able to:
Use the ChipScope Pro Core Inserter
Make ChipScope Pro Core connections
Procedure
This lab comprises four primary steps: you will create an ISE design, generate the cores,
implement the design, and finally perform in-circuit verification. Below each general instruction
for a given procedure, you will find accompanying step-by-step directions and illustrated figures
providing more detail for performing the general instruction. If you feel confident about a specific
instruction, feel free to skip the step-by-step directions and move on to the next general instruction
in the procedure.
Note: You can download the lab files for this module from the Xilinx FTP site at
www.xilinx.com
1-877-XLX-CLAS
2c--3
Create ISE Design
Step 1
Create a new ISE project named cs_pro in

c:\training\chipscope_pro\labs\CSPro_CoreIns. Specify the device you are using
on your board (must be one of the following device families: Virtex, Virtex-E,
Virtex-II, Virtex-II Pro, Spartan-II, Spartan_IIE, and Spartan-3). Add
counter(.v/.vhd) and counter.ucf to the project from
c:\training\chipscope_pro\labs\CSPro_CoreIns.
Click Start Programs Xilinx ISE 6 Project Navigator
Click File New Project. Use the following settings:
Project Location: Browse to c:\training\chipscope_pro\labs\CSPro_CoreIns

Project Name: cs_pro
Top Level Module Type: HDL
Click Next. Enter your device information, select XST as the synthesis tool, and select
VHDL or Verilog as your simulation language.
Click Next two times. Under Add existing sources, click Add Source. Browse to
c:\training\chipscope_pro\labs\CSPro_CoreIns and select counter.v/.vhd and counter.ucf.
Click Open. When the Choose Source Type window pops up, select VHDL/Verilog Design
File, and click OK
Click Next, click Finish
Generate Cores
Step 2
Create a ChipScope Definition and Connection File for counter(.v/.vhd). Use

the file name cs_pro.
Select the counter.v file in the Sources in Project window of ISE
Click Project New Source
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1-877-XLX-CLAS
2c--4
In the New Source window, select ChipScope Definition and Connection File in the lefthand pane. Enter a File Name of cs_pro. The location should be
c:\training\chipscope_pro\labs\CSPro_CoreIns. Make sure Add to project is checked, click
Next (Figure 1)
Figure 1. New ChipScope Definition and Connection File

In the Select source file window, select counter and click Next
In the New Source Information window, select Finish
Generate ChipScope cores through the Core Inserter. Create an ILA core with
the following parameters:
Use SRL16s and RPMs: Checked
Number of Input Trigger Ports: 3
Data Depth: 512
Data Same as Trigger: Checked
In the Sources in Project window, double-click cs_pro.cdc
This will open the ChipScope Pro Core Inserter after it has synthesized the design.
In the ChipScope Pro Core Inserter window, select ICON in the left-hand pane. Click Next
This will start the creation process for generating an ILA core.
For Number of Input Trigger Ports, select 3
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2c--5
Edit each trigger to match the following settings (also shown in Figure 2):


Leave all the other settings at their default values
Figure 2. Trigger Parameters
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2c--6
Click Next. For Data Depth, select 512 Samples. Check Data Same As Trigger. Results
are as shown in Figure 3, below. Click Next
Figure 3. Data Port Settings
Modify core connections to match the following:

Clock CH: 0 - clk_bufg

Trigger/Data TP0, CH:0 - reset1
Trigger/Data TP1, CH:[3:0] - cnt4[3:0]
Trigger/Data TP2, CH:[7:0] - div_cntr2[7:0]
Click Modify Connections

In the right-hand side of the Modify Connections window, select the Clock tab, at the top. In
the lower-left hand pane in the Pattern filter box, enter clk*, click Filter
Select clk_bufg, then click the Make Connections button, in the lower right-hand corner
Click the Trigger/Data tab, in the top right-hand corner of the Net Selections pane. Select
the TP0 tab, in the lower left-hand corner of the Net Selections pane
In the lower left-hand pane in the Pattern filter box, enter reset1, click Filter. Select reset1,
then click the Make Connections button, in the lower right-hand corner
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2c--7
Repeat instructions 4 and 5, with the following settings:

Select the TP1 tab
Pattern filter: cnt4*
Make the following connections:
cnt4_0: CH:0
cnt4_1: CH:1
cnt4_2: CH:2
cnt4_3: CH:3
Repeat instructions 4 and 5, with the following settings:
Select the TP2 tab
Pattern filter: div_cntr2<?>
Make the following connections. Click the Net Name header to properly align all of the
bits, then you can use click-shift-click to select all of elements and make the connections
as shown in Figure 3:
div_cntr2<0>: CH:0
div_cntr2<1>: CH:1
div_cntr2<2>: CH:2
div_cntr2<3>: CH:3
div_cntr2<4>: CH:4
div_cntr2<5>: CH:5
div_cntr2<6>: CH:6
div_cntr2<7>: CH:7
Figure 3. Modifying Connections

Click OK
In the ChipScope Pro Core Inserter window, click Return to Project Navigator. Click
Yes to save the project
This will save to appropriate cores and insert them into the netlist.
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1-877-XLX-CLAS
2c--8
Implement Design
Step 3
Edit the UCF file to match your board I/O and clock speed. Implement the design
and generate the programming file.
In the Project Navigator Sources in Project window, select counter.ucf. In the Processes
for Source window, expand User Constraints, double-click Edit Constraints (Text)
Edit the I/O pin constraints to match your board-level I/O
Edit the Period and Offset In/Out constraints to match your clock period
Generally, the Offset In/Out should be safe if set and one-half the period of the clock.
In the Sources in Project window, select counter.vhd
In the Processes for Source window, double-click Generate Programming File
This will implement the design and generate the programming file. Now we are ready to start
using the ChipScope Pro Analyzer.
In-Circuit Verification (ChipScope Pro Analyzer)
Step 4
Open the ChipScope Pro Analyzer and program your device.

In the Project Navigator Processes for Source window, double-click Analyze Design Using
Chipscope to open the ChipScope Pro Analyzer console
Click the Open Cable/Search JTAG Chain button in the top-left corner of the ChipScope
Pro Analyzer window, as shown in Figure 4. Click OK in the JTAG pop-up window
The ChipScope Pro Analyzer will poll the JTAG chain and find the parts available for
programming. It will also report these results. Your board must be powered on for your
device to be recognized.
Figure 4. Open Cable/Search JTAG Chain Button

Select Device (menu) Configure <Device to program>
In the JTAG Configuration window, click Select New File. Browse to
c:\training\chipscope_pro\labs\CSPro_CoreIns and select counter.bit. Click Open
In the JTAG Configuration window, click OK
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1-877-XLX-CLAS
2c--9
This will program the device and initialize the Trigger Setup window and the Waveform
window.
Setup Trigger values as shown in Figures 6 and 7, below.

If the Trigger Setup window is not open, in the New Project window (upper-left corner)
expand JTAG Chain, expand Device (your device number), expand ILA Unit, double-click
Trigger Setup, as shown in Figure 5
Figure 5. Open Trigger Setup Window

In the Trigger Setup window, Match console, edit the trigger values to match those shown in
Figure 6, below

MO: TriggerPort0 is attached to the asynchronous reset.

M1: TriggerPort1 is attached to the cnt4 outputs.
M2: TriggerPort2 is attached to the eight-bit counter div_cntr2 (used as the clock enable
when it reaches hex value FF).
Figure 6. Trigger Values

In the Trigger Setup window, Trigger console, click Trigger condition M0. This opens the
Trigger Condition editor. Note the available settings. Click OK
In the Trigger Setup window, Trigger console, click the Add button. This will create
Trigger Condition1 (you can edit this name by clicking it). Click M0 for trigger
Condition1 to edit the Trigger Condition editor
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2c--10
Deselect Enable for M0 Match Unit and Enable the M1 Match Unit (result shown in
Figure 7). Click OK
Note: You can create Boolean equations by combining multiple match units to create a
trigger. You can also create a sequence of events for the trigger by selecting the Sequencer
tab.
Figure 7. Trigger Conditions for Trigger Condition1
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1-877-XLX-CLAS
2c--11
Repeat instructions 4 and 5 and create a trigger for Match Unit M2. Click the Active button
for Trigger Condtion2
This will set this as the active triggeronly one trigger can be active at any one timewhen
we setup and run the triggers.
Your Trigger Setup Window should now look like Figure 8.
Figure 8. Final Trigger Setup Window Values
Edit the Waveform signal names and create buses as shown in Figure 9. Save
the ChipScope Pro Analyzer project as cs_analyzer.cpj.
If the Waveform window is not open, in the New Project window (upper-left corner),
expand JTAG Chain, expand Device (your device number), expand ILA Unit, double-click
Waveform window. (If only DataPort[0] is available, you will have to go back and open the
Core Inserter and ensure all of the Trigger ports are included as Data (checked) in the
Capture Parameters tab, as shown in Figure 2.)
The DataPorts represent the following HDL connections:
DataPort[0]: reset
DataPort[4:1]: cnt4
DataPort[12:5]: div_cntr2
To edit the names, in the Signals window in the left-hand pane of the Analyzer window,
expand Trigger Ports, and expand each trigger port. For Trigger Port 0, right-click CH: 0,
and select Rename. Enter reset and click Enter (or Return) on your keyboard
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2c--12
Repeat instruction 2 for Trigger Port1 and Trigger Port 2, using the names shown in Figure
9, below
Figure 9. Signal Names Pane

In the Waveform window, use click-shift-click to select all of the cnt4 signals, right-click
one of the cnt4 signals and select Add to Bus New Bus. Right-click the newly created
bus, BUS_0, and select Rename. Enter cnt4[3:0] and click OK
Note: You can click-and-drag signals from the Signals pane into the Waveform window if
some signals are not available.

Select the individual cnt4 signals and press Delete on your keyboard
Repeat instructions 4 and 5, for div_cntr2, creating a bus named div_cntr2[7:0]. The
resulting Waveform Bus/Signal pane, should look like that shown in Figure 10
Figure 10. Resulting Bus/Signal Pane

Save the project settings (this will allow these changes to be loaded again at a later date) by
selecting File Save Project. Browse to c:\training\chipscope_pro\labs\CSPro_CoreIns.
Enter the name cs_analyzer.cpj. Click Save
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1-877-XLX-CLAS
2c--13
Activate and run triggers. Experiment with triggers.

Select Trigger Setup (menu) Run, or simply press the F5 button on your keyboard.
This will activate the Active trigger and update the Waveform window when the trigger is
satisfied.
Figure 11. Resulting Waveform Window

Press F5 several more times to view the changes to cnt4
Experiment with trigger values and settings, and re-run the triggers. You can also try Ctrl-F5
or select Trigger Setup (menu) Trigger Immediate (this will immediately active the
trigger and update the Waveform window). You could also set up a trigger sequence (Use
M2 M1)
Conclusion
ChipScope Pro is an extremely powerful tool that will save you time and money. The
capabilities covered in this lab are just the tip of the iceberg. Have fun with this powerful tool!
www.xilinx.com
1-877-XLX-CLAS
2c--14

Chipscope 6 Rev1

Diunggah oleh

Informasi Dokumen

Judul Asli

Hak Cipta

Format Tersedia

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Chipscope 6 Rev1

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ChipScope Pro 6.

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Need for On-Chip Debug

Late in the design cycle

Cannot get internal access

Full scan insertion

How do I access the embedded

Respins are ENORMOUSLY

Tools are cumbersome and slow

Logic BIST Memory BIST Access

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ChipScope Pro System

Debug occurs at (or near) system speeds

Access all of the internal signals and

Minimize pins required for debug

Access via the JTAG interface

2004 Xilinx, Inc. All Rights Reserved

Core Resource Utilization

Block Ram Utilization for Virtex-II/-II Pro, Spartan-3

ChipScope Pro cores

You must leave room for

Slice Logic Utilization for Virtex-II/-II Pro, Spartan-3

This may require using

2004 Xilinx, Inc. All Rights Reserved

Download cables supported:

Parallel Cable III

Cables connect to a JTAG header, which is connected to the JTAG pins

2004 Xilinx, Inc. All Rights Reserved

2004 Xilinx, Inc. All Rights Reserved

Using ChipScope Pro

Place the ChipScope Pro cores

Attach internal nodes for viewing

Place and route your design by

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Core Generator Flow

The Core Generator generates

Allows access to all HDL

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Core Inserter Flow

The Core Inserter inserts cores

HDL code is untouched

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ICON (Integrated Control core): This core controls up to fifteen capture

Customizable number, width, and storage of trigger ports

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ILA Pro Cores

You can select 1 to 16 trigger ports

Up to 256 channels per trigger port

Multiple match units on the same

For example, 4 trigger ports with

You can define the trigger ports

Control signal triggers

Trigger time stamps

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ATC (Agilent Trace Cores)

Agilent Trace Core

Out of Block RAM? Need more than 16K

ATC provides a capture depth of up to twomillion samples at 200 MHz

Create a core with the same set of ILA Pro

Specify Time-Division Multiplexing details for the

Transmit rate (1X, 2X, 4X), number of data