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Sri Lanka Institute of Information Technology

BSc. Eng. Honours Degree

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lll

Engineering
Midterm Examination
Year 2, Semester II (20 15)

EC31 01 -Advanced Digital Design

Duration: 1 Hour
October 2015

Instructions to Candidates:

This paper has 04 questions on 6 pages including the cover page.

Answer all the questions.

Calculators are allowed.

Write the answers on the same paper.

. Write the index number on each page.
This examination accounts for 10% of final module assessment.

Question 1

15 Marks
+V

Figure Q1
a) What logic function is implemented by the CMOS circuit shown in Figure Q 1?

b) Write the Boolean Equation of function F

c) The logic levels given in the data sheet ofthe above CMOS family are as follows.
VIL = 0.9 V, Vrn = 1.8 V, VoL= 0.36 V, VoH =2.7 V.
What is the Low level noise margin (NML) ofthis logic family?

d) How much noise can be added to an output signal of the above CMOS family before it
stops being recognize as a 1 by an input of the same family?

e) Draw a schematic diagram of a CMOS circuit suitable to complement the function F in

part (b)

Index Number
10 Marks

Question 2
Identify the models and architectures shown in the Figure Q2.

Figure Q2

Figure a). _ __

a. VLIW datapath

Figure b). _ __

b. Mealy-type FSM

Figure c). _ __

c. Dataflow Graph

Figure d). _ __

d. Moore-type FSM

Figure e). _ __

e. Generic controller design

Question 3

15 Marks
A
B

c
D

~=[)-'
s_:]

Sell
SeiO

Mux2to1

Mux4to1
Figure Q3a

Mux4to 1 in Figure Q3 shows a block diagram of 4 to 1 multiplexer designed using a 2 to 1

multiplexer. Complete the hardware description written in VHDL for above hierarchical design.

Library ieee;
__

-~_.std_logic_1164.all;

Entity Mux4to1 is
Port (A, B, C, D : In std_logic;
Sel: in std_logic_vector (1 downto 0);
F : __ Std_logic );
end - - - - - Architecture Structure of - - - - - - 1s
Signal Il,I2 : std_logic;
Component Mux2to 1 is
Port {x, y : In std_logic ;
S : in std_logic;
z: Out Std_logic );
end Component Mux2to 1;
4

Begin
Mux1: Mux2to1 port map (x =>A, y => B, S => Sel(O), z => Il);
Mux2: Mux2to1 port map (x => _, y => _, S => Sel(O), z => _);
Mux3: Mux2to 1 port map (x => _, y => _, S => _ _, z => F);
end Architecture Structure;

Library ieee;
_ _ _ .std_logic_1164.all;
Entity Mux2to 1 is
Port (x, y: In std_logic;
S: in std_logic;
z: Out Std_logic );
end Mux2to1;
Architecture - - - - of Mux2to 1 is
Begin
with (S) Select

z<= x
y

When '0'

'
When others;

End Architecture _ _ _ _ __

Question 4

20 Marks

Use your knowledge and common sense to determine if the following statements are TRUE or
FALSE.
Most phenomena in the world are .of analogue nature.
Digital signals need to be converted to analogue before being processed by computers. - - Digital signals are discrete in time but continuous in amplitude.
In binary signals, 0 and 1 represent two values of a physical phenomenon (temperature, voltage,
current, etc.)
The DC transfer characteristics of a gate describe the input voltages as a function of the output
voltage.
The same FPGA chip can be used in several different designs
System design is the process of implementing a desired functionality using a set of physical
components . _ __
Partitioning a complex system into smaller subsystems very rarely simplifies the design
task. _ __
Hardware description languages can be used to design at any level of abstraction. _ __

Structural models are related to specific pieces of hardware. _ _ __

End of the Question Paper