Performa for submission of proposal under

INDUSTRY-ACADEMIA FACULTY DEVELOPMENT PROGRAMME

DETAILS OF THE ACADEMIC PARTNER
Name of the institute
JSS Academy Technical Education
Address of the Institution
Uttarahalli-Kengeri Main Road,
Srinivasapura, Bangalore-60.
Email: info@jssateb.ac.in
Telephone:- 28602565,2575,3425,3702
Fax:- 080-28603706
Title of the Program
Internet of Things(IoT)
Program intended for
To Enhance Recent Technical Skills in Staff Members
Name of the Program
Dr. B. G. Shivaleelavathi
Coordinator
Designation
Department
Research Area and

Professor
Electronics & Communication Engineering Dept.,
Power Electronics & Drives.

Specializations
No. of Publications/Patents
Teaching Experience
Industrial Experience, If any
Broad Area of the Proposal
Duration of the Program
Sessions per day
Proposed dates for the

16 publications
28 Years
-Real Time Embedded Systems
4 days
4 Sessions per day
5th, 6th, 7th and 8th Dec 2016

program(Provide 3 different

26th, 27th, 28th, and 29th Dec 2016

dates)
Total number of participants

16th, 17th, 18th and 19th Jan 2017

50 Nos.

anticipated
Signature of the Program
Coordinator

(Dr. B. G. Shivalelavathi)

DETAILS OF THE INDUSTRIAL PARTNER

Name(s) of the Industry

FOUNDATION FOR INNOVATION AND

COLLABORATIVE EDUCATION(FICE)-Intel

Address

F-2, LXY Aura, 99D, KHB Colony, 5th Block, Koramangala,

Bangalore-560095

Website Address
Name(s) of the Contact Person
Designation

Email: info@fice.in
Telephone: (080) 41751855/56
Fax:Website: http://www.fice.in
Pradeep. G
9980136933
Associate Vice President
FICE- Intel Program.

Technical Expertise
Embedded systems and IoT
Financial Commitment, if any
----Role of the Industrial Partner(s) To drive latest technology and concepts to academicians
Attach copy of letters received from participating industry showing intent finance commencement
etc.

Specific Field of the Proposal:

1) Real Time Embedded Systems and IoT for Real time applications.
2) Designing complex signal processing applications using Intel Gelileo processor

Brief Summary of the Proposal:

This FDP is an initiative program enabling the teaching faculty towards enhancing the
effectiveness of their teaching - learning process on the latest technology, bringing in the practical
application perspective and practices in teaching/ learning pertaining to the present technology.
Through this program we bring experts from the relevant domain who share their experience and
impart the practical hands-on to the participants starting from the first principles in order to bridge
the concepts of the practices.
The faculty after attending the 4 days FDP will train students, help them develop prototypes and
nurture the same to project. The students may consider this as their final year innovative project.
FICE has worked with Intel Corporation and faculty at the Indian Institute of Science, Bengaluru.
We believe that the faculty will be immensely benefited by availing the opportunity to attend the
FDP.
In the proposal, we are providing hands on training on Intel Galileo which as higher capabilities.
Galileo can be the platform for working projects on Internet of Things (IoT).
The proposal talks about 4 days of lecture series and rigorous hands-on training for faculty
followed by certification from Intel and FICE.
Objectives:
1)To bridge the Gap between industry and academia.
2)To build the relevant technical skills in faculty in the Latest Technology.
3) Nurture the students to work on the present technology industrial standards.
Project Impact-Expected outcome:
To impart the IoT skills to faculty so that they can:
Create large pool of highly skilled people, mostly developers and engineers, to work on
IoT.
These developers will create the ecosystem that will produce and sustain the Internet of
Things which can then be used by people for better lives (work on projects for
agriculture/smart city/smart village/smart cars/smart homes).
Level of activity (Regional/National/International) and target audience:
National Level:

Target audience:- Faculty from various Engineering Colleges, Research Scholars, Industry
Professionals, .
Concepts expected to evolve for Project Proposal Development
1.
2.
3.
4.
5.

Concepts of Communication on Real Time Embedded systems.

Hardware concepts for Real Time Embedded systems implementation.
Concepts of Signal processing.
Concepts of developing software modules for Real Time Applications.
Project based learning.

Programme details
Date
Day 1:
5th, Dec 2016

Time

Activity

9:00am
To
5:30pm

Key note address:

Lecture 1, Lecture 2:
Seminar hall:

26th, Dec 2016

Lecture 3, 4:
Demonstration in
Lab/hands on in lab

16thJan 2017

Day 2:
6thDec 2016

9:00am
To
5:30pm

27th, Dec 2016

Lecture 7, 8:
Demonstration in
Lab/hands on in lab

17thJan 2017
Day 3

Day 4:
7th Dec 2016
28th Dec 2016
18th Janc 2017

Demonstration in lab
Lecture 5, Lectur6
3:Seminar hall

9:00am
To
5:30pm
9:00am
To
5:30pm

Industry visit to
Wipro/Cisco/FICE/BOS
CH/ARM/General
Electric
Lecture 9, Lecture 10
Seminar hall
Lecture 11, 12:
Demonstration in
Lab/hands on in lab,
Valedictory function

Venue

Infrastructural
requirements
and availability

Seminar
hall 1
Research
lab/ VLSI
Lab

Seating
arrangement for
75 persons,
50 computers,
LCD projector.

Library
Seminar
hall
Research
lab/ VLSI
Lab

Seating
arrangement for
75 persons,
50 computers,
LCD projector

Bangalore

Transport will
be arranged by
institute.
Seating
arrangement for
75 persons,
50 computers,
LCD projector

Library
Seminar
hall
Research
lab/ VLSI
Lab

Resource Persons expected to participate

Name
Designation
Organization
INTEL-FICE
Pradeed .G
Associate Vice
Program
President

Activity
Inauguration Keynote address

Raghav Ankur

National ManagerTechnical

INTEL-FICE
Program

Lecture 1: Embedded Linux and Intel

Galileo- project case studies, platforms and
various IOT applications

Suryender Sharma

Asst. ManagerTech support

INTEL-FICE
Program

Lecture 2 (Lab): Setting up the Galileo

Board and the Arduino environment

Raghav Ankur,

National ManagerTechnical

INTEL-FICE
Program

Lecture 3: Accessing Linux terminal using

virtual serial/Ethernet interface like
PUTTY/Tera term (commands, utilities and
shell )

Raghav Ankur,

National ManagerTechnical

INTEL-FICE
Program

Lecture 4: Programming using Arduino API

and its role in building embedded
applications

Suryender Sharma

Asst. ManagerTech support

INTEL-FICE
Program

Lecture 5 (Lab): Interfacing various

Digital/Analog Sensors (GPIO, PWM,
Analog)

Raghav Ankur,

National ManagerTechnical

INTEL-FICE
Program

Lecture 6: Serial communication protocol

(UART/I2C)

Suryender Sharma

Asst. ManagerTech support

INTEL-FICE
Program

Lecture 7 (Lab):Case Study: Data logging

using SD library

Suryender Sharma

Asst. ManagerTech support

INTEL-FICE
Program

Lecture 8 (Lab): Programming GSM-GPRS

Shields and related case studies

Suryender Sharma

Asst. ManagerTech support

INTEL-FICE
Program

Lecture 9 (Lab):Building IoT SD card

image and related components.

Setting up Networking (*Ethernet

and *Wi-Fi).

Raghav Ankur,

National ManagerTechnical

INTEL-FICE
Program

Lecture 10 (Lab): Embedded Linux based

Networking application demonstration using
POSIX based API

Raghav Ankur,

National ManagerTechnical

INTEL-FICE
Program

Lecture 11: 3-Tier architecture of IoT

applications and related protocols

Raghav Ankur,

National ManagerTechnical

INTEL-FICE
Program

Lecture 12(Lab)Building IoT applications:

Thingspeak cloud management framework
for data logging and data visualization

Similar event organized by the Institute earlier, if any.

Title of
the
activity

Subject

Date
from
to
(latest
first)

Workshop Advanced
on GNU Communication
Radio and
Software
defined
Radio

Level
(Regional/National/
International)

5 days National
27th
June to
1st
July
2016

Workshop Communication 3days

on Signal,
22nd to
Image
24th
processin
June
g & SDR
2015
using Lab
View

National

FDP on VLSI Design

Advance
VLSI
Design
Using
Cadence
Tool
Suite

3 days

National

FDP on
Low
power
Embedde
d system
using
MSP430

02
Days

Embedded
Systems

Budget Estimates

16th to
18th
July
2014

4th &
5th
March
2013

National

Name of
external
body
involved, if
any

Grants received
by funding
agency (Rs.)

Tenet
Rs.1,38,000/Technetronics finance approved
from JSSMVP.
and
Academic
Organization
Texas
Instruments
Reva ITM
National
Instruments
Tech Labs

Rs. 71,657/-

Corporate
trainers from
Cadence
Design
Systems

Rs. 71,657/-

Resource
Persons from
Texas
Instruments.
TI university
Programs.
Cranes
International
limited.

Funded by the
Organization-JSS
Mahavidhyapeeta,
Mysore.

Funded by the
Organization-JSS
Mahavidhyapeeta,
Mysore.

Funded by the
Organization-JSS
Mahavidhyapeeta,
Mysore.

Anticipated
Expenditure

Head of Expenditure
Travel and Honorarium for Resource
Persons

Budget Contribution
by Organizing
Institute

60,000/-

TA & Accommodation (outstation) and

Food for Participants

1,00,000/- 30,000/-

External
Sponsorship
s
(Industry)
-----------

FDP preparation and arrangements

40,000/- -----

------

Miscellaneous

30,000/- ------

-------

Total

2,30,000/- 30,000/-

------

Details of previous grants awarded to the Institute under different schemes of VGST in the
last three years.
Schem
e

Name of the
coordinator

Amount
sanctioned

VTUDr. Rathna, Rs. 2 lakhs

VGST Professor.
5 days Dr. Mahesh,
Assoc.
FDP
Professor.

CISEE

Dr. Mahesh, 30lakhs

Assoc. Prof.
and Head,
Chemistry
Dept.,
JSSATEB

Sanctioned
letter details

Funds
Utilization
position as
on today

Utilization Certificate
details/Reason for nonsubmission of Utilization
Certificate

VTU/A7/201112/8161,
dtd.8/10/2011

2 lakhs

UC submitted

VTU/Aca/20112012/A-9/9459.
Dtd.17/11/2011

Ref:JSSATEB/Chemistry/
2012-13/592
Dated:27/06/2012

VGST/CISEE/
01/01/2015 1. UC submitted ref.
JSSATEB/VGSTGRD-326/2014(3
Rs.
10
CISEE/Chemistry/201
15
5-2016/1814,
years)
lakhs
dated. 6/01/2016.
Dated
released
2. Revised UC submitted
01/1/2015
ref.
JSSATE/Chemistry/V
GST-CISEE/201617/823.
Dated.26/07/2016
By signing this certificate, I/We undertake to

Abide by all the rules/regulations regarding utilization of amount that may be granted to the
institute.
Submit detailed reports about grant utilization.
Submit utilization certificate duly authenticated by CA at the time of submitting the report.
Return full/partial unutilized grant amount to KSTePS account.

Note:
Faculty Development Programme should be organized within 6 months after receiving the grant in
collaboration with industries. The maximum budget allowed for each FDP is Rs.2.00 lakhs from
VGST.
(Dr. B. G. Shivaleelavthi)
Name And Signature Of
The Programme Coordinator

(Dr. Mrutyunjaya V. Latte)

Name And Signature Of The Principal

Place: Bengaluru
Date:

ANNEXURE IV(a)

SCHEDULE OF FACULTY DEVELOPMENT PROGRAMME FOR

ENGINEERING COLLEGE (FDP-ENGG) DURING THE FY: 2016-`17
Title of the proposed program under FDP: Internet Of Things (IOT)
Venue: Seminar Hall1, Academic Block 1/Library Seminar Hall Academic Block2
Day 1: 5th, Dec 2016 / 26th, Dec 2016 / 16thJan 2017
TIME

PROGRAMME

9.00 am 10.00 am

Inauguration

10.00 am 11.30 am

Lecture 1: Embedded Linux and Intel Galileo- project

case studies, platforms and various IOT applications
by Raghav Ankur, National Manager-Technical INTELFICE Program

11.30 am 11.45 am
11.45 am 01.15 pm

Tea/Coffee Break
Lecture 2 :
Setting up the Galileo Board and the Arduino
environment.
by Suryender Sharma, Asst. Manager- Tech support
INTEL-FICE Program

1.15 pm -2.15 pm
2.15 pm 3.45 pm

Lunch Break
Lecture 3(lab):
Accessing Linux terminal using virtual serial/Ethernet
interface like PUTTY/Tera term (commands, utilities
and shell )

by Raghav Ankur, National Manager-Technical INTELFICE Program

3.45 pm 4.00 pm
4.00 pm 5.30 pm

Tea/Coffee Break
Lecture 4 :
Programming using Arduino API and its role in building
embedded applications
by Raghav Ankur, National Manager-Technical INTELFICE Program

Day 2: 6thDec 2016 / 27th, Dec 2016 / 17th Jan 2017

TIME
10.00 am 11.30 am

PROGRAMME
Lecture 5:
Interfacing various Digital/Analog Sensors (GPIO,
PWM, Analog)
by Suryender Sharma, Asst. Manager- Tech support
INTEL-FICE Program

11.30 am 11.45 am
11.45 am 1.15 pm

Tea/Coffee Break
Lecture 6:
Serial communication protocol (UART/I2C)
by Raghav Ankur, National Manager-Technical
INTEL-FICE Program

1.15 pm -2.15 pm
2.15 pm 3.45 pm

Lunch Break
Lecture 7 (Lab):
Case Study:Data logging using SD library
by Raghav Ankur, National Manager-Technical
INTEL-FICE Program

3.45 pm 4.00 pm
4.00 pm 5.30 pm

Tea/Coffee Break
Lecture 8 (Lab): Programming GSM-GPRS Shields
and related case studies
by Suryender Sharma, Asst. Manager- Tech support
INTEL-FICE Program

Day 3:, 7th Dec 2016 / 8th, Dec 2016 / 18th Jan 2017
Name(s) of proposed Industries / R & D Institutions to be visited:
TIME

PROGRAMME

Intel-FICE industry visit program.

9.00 am 5.30 pm

The timings of lecture, lunch break etc., can be arranged based

on the convenience of the collaborating/ organizing Industries
/Institutions.

Day 4: 8th Dec 2016 / 29th Dec 2016 / 19th Jan 2017
TIME
9.30 am 11.00 am

PROGRAMME
Lecture 9:

Building IoT SD card image and related

components.
Setting up Networking (*Ethernet and *WiFi).
by Suryender Sharma, Asst. Manager- Tech support
INTEL-FICE Program
11.00 am 11.15 am
11.15 am 12.45 pm

Tea/Coffee Break
Lecture 10: Embedded Linux based Networking
application demonstration using POSIX based API
by Raghav Ankur, National Manager-Technical
INTEL-FICE Program

12.45 pm 1.30 pm

Lunch Break

1.30 pm 3.00 pm

Lecture 11(Lab): 3-Tier architecture of IoT applications

and related protocols
by Raghav Ankur, National Manager-Technical
INTEL-FICE Program

3.00 pm 4.30 pm

Lecture 12(Lab)Building IoT applications:

Thingspeak cloud management framework for data
logging and data visualization
by Raghav Ankur, National Manager-Technical
INTEL-FICE Program

4.30 pm 5.30 pm

Valedictory Function & High Tea

ANNEXURE IV(b)

VGST FDP - ENGG: 2016-17

ESTIMATE OF EXPENDITURE
Sl.
No.

Amount
in Rs.

Particular/Head

Travelling Allowance for outstation participants

to and fro and internal/local transport

including

Food and Accommodation (wherever applicable) for participants

46,000/-

Travel, Honorarium & Food [Honorarium Rs. 2500 per talk (1 hours)]

60,000/-

Folders, Pens, Work books, Stationary, Badge, Brochures, Certificate, Resource

Material for 50 Persons @Rs. 200 per person

10,000/-

Inauguration, Valedictory function: Banner, Invitation, Publicity, Media, Courier,

Postal, Telephone, Documentation & Coordination Expenses.

20,000/-

Contingency fund

10,000/-

Local transport to Industrial Visit & Coordination

15,000/-

Honorarium to support Staff @ Rs. 500/day for 3 persons for 4 days (500x3x4
days)

6,000/-

Honorarium for the Chief Co-ordinator of FDP

TOTAL AMOUNT ALLOCATED FOR ORGANIZING 4 DAYS FDP

25,000/-

8,000/-

2,00,000/-

PS:
(1)Minimum participants shall be 50, out of which 40 shall be from other colleges.
(2)Only 10% of re-appropriation in the Estimated Expenditure under each head is allowed by
VGST for organizing FDP.
(3)Air fare for Resource persons is not allowed from VGST grants. However, this can be
arranged through grants from Parent organization or External agencies.
(4)Institutions and Industrial support is encouraged besides VGST grants.

ANNEXURE V

Applicant Declaration Letter

1 VGST PROGRAMME

2 Period of the

VGST FDP - ENGG: 2016-17

One Year

Two Years

Three Years

VGST Programme
4 COLLEGE/ Institution
Address

JSS Academy of Technical Education,

JSS Campus, Uttarahalli-Kengeri Road.
Bangalore 560060

5 DEPARTMENT

Electronics and Communication Engineering

6 TOPIC/ TITLE

7 Applicants
details

Internet of Things-IoT

Name
Designation
Contact
number

Dr. B. G. Shivaleelavathi
Professor
9986651890

I am aware of all instructions and directions indicated in Guidelines, Terms and Conditions
(GTC) present in the Concept Proposals of VGST.
If my proposal is selected by VGST, I undertake to utilize the VGST grant by strictly adhering to
the GTC of VGST.
If my proposal is selected by VGST and in case of my transfer/ retirement/ deputation/
termination from this Grantee Institution, I shall obtain NOC from VGST office by suggesting
another responsible faculty member as Programme Co-ordinator (PC), who belongs to the
grantee Dept. of this College/ Institution (Not applicable to SMYSR scheme).
If my proposal is selected by VGST, I shall procure the equipment within the allowed cost as
approved by VGST in the Budget Estimate (Both Non-Recurring & Recurring) within the
stipulated period by following due guidelines of KTTP Act.
If my proposal is selected by VGST, I shall obtain the VGST approval of the Budget Estimate
(both Non-recurring & Recurring) before utilizing the VGST grant.
If my proposal is selected by VGST, I will not procure any equipment which is not approved by

VGST. If such procurement of Equipment/Item is made without the VGSTs approval, the
Programme Co-ordinator/College Management/ Grantee Institution will bear the cost of the
equipment/Item.
I shall not seek for further changes in the Original Budget Estimate (Both Non-Recurring &
Recurring) (as indicated in my Original Proposal) submitted by me to VGST.

____________________________
Passport Size
photograph of
Applicant

Date:

Name and Signature of

Applicant (with seal)

Place: