UVM Factory

As the name implies, uvm_factory is used to create UVM objects and component. Object and
component types are registered with the factory using
and components being created.

lightweight proxies to the actual objects

The uvm_object_registry #(T,Tname) and uvm_component_registry #(T,Tname) class are used to

proxy uvm_objects and uvm_components. With create we create factory.

The type_id::create() method returns an instance of the desired type, in below case
it returns instance inherit_bot_h of inherit_bot.
The use of the factory allows the developer to derive a new class extended from inherit_bot
and cause the factory to return the extended type in place of inherit_bot. Thus, the parent component can
use the new type without modifying the parent class.

Using the factory, we can overrite the type of component created by create method
from the higher level component in verification environment or from top level test.
driver = my_driver::type_id::create("driver",this); //it is in build phase of component
For example we create any component or inherit any class inherit_bot in top class top.

Class top extends xyz..

inherit_bot inherit_bot_h
inherit_bot_h= inherit_bot:: type_id::create(inherit_bot_h,this);
endclass

Suppose inherit_bot class is changed to inherit_bot_new, I dont need to change class top. I
will override function in top level component ot test.

https://www.youtube.com/watch?v=BXLyO6s9O3Y
Or suppose any driver in any agent got changed, we dont need to change the code of
agent. We can override the driver in any top level component.

http://www.sunburst-design.com/papers/CummingsSNUG2012SV_UVM_Factories.pdf

https://www.youtube.com/watch?v=BXLyO6s9O3Y
https://verificationacademy.com/verification-methodologyreference/uvm/docs_1.1a/html/files/base/uvm_factory-svh.html

connect phase of component

seq_item_port & seq_item_export

UVM Factory

Sequence Item
The UVM Class Library provides the uvm_sequence_item base class &
uvm_transaction base class.

Data items:
Are transaction objects used as stimulus to the device under test (DUT).
Represent transactions that are processed by the verification environment.

UVM has built-in automation for many service routines that a data item needs. For
example, you can use:
print() to print a data item.
copy() to copy the contents of a data item.
compare() to compare two similar objects.
For That, `uvm_object_utils macro registers the class type with the common factory.

TLM:
https://www.youtube.com/watch?v=a_2uqhgJV3U

TLM1: TLM1 ports provide blocking & non-blocking pass by value transaction level interface. The

semantics of these interfaces are limited to message passing.

TLM2: TLM2 sockets provide blocking & non-blocking transaction level interface with well defined
completion semantic.
Sequencer port: Push/pull port with well defined semantic. It is used to connect sequencers with

drivers and layering sequences.

Analysis port:

The analysis interface is used to perform non-blocking broadcasts of transactions to

connected components.