VASAVI COLLEGE OF ENGINEERING

(Autonomous)
IBRAHIMBAGH, HYDERABAD-500031
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
ASSIGNMENT - II

Date of submission 26-916

Subject : Computer Architecture

Faculty : V.Punnarao

Year : B.E. 2/4 (Sem-I)

Class : CSE B

Group
I
II
III
IV
V
VI
VII
VIII
IX
X

Roll Nos
1602-15-733-061 to 067
1602-15-733-068 to 074
1602-15-733-075 to 081
1602-15-733-082 to 088
1602-15-733-089 to 095
1602-15-733-096 to 102
1602-15-733-103 to 109
1602-15-733-110 to 116
1602-15-733-117 to120 and 313 to
315
1602-15-733-316 to 324

Resource for assignment:

Refer computer system architecture by M.morris mano book.

GROUP-I
1. What is the difference between a microprocessor and a microprogram ? is it

possible to design a microprocessor without a microprogram? Are all

microprogrammed computers also microprocessors?
2. Using table 7.1 give the 9-bit microoperation field for the following
microoperations:
a. ACAC+1, DRDR+1

b. PCPC+1, DR M[AR]
c. DRAC, ACDR
3. A computer has 16 registers , an ALU (arithmetic logic unit) with 32
operations, and a shifter with eight operations, all connected to a common
bus system.
a. Formulate a control word for a microoperation.
b. Specify the number of bits in each field of the control word and gave a
general encoding scheme
c. Show the bits of the control word that specify the microoperation
R4R5+R6.
4. Convert the following arithmetic expressions from infix to reverse polish
notation
a. A*B+C*D +E*F
b. A*B+A*(B*D+C*E)
c. A+B*[C*D+E*(F+G)]
d.

A[B+C( D+ E ) ]
F(G+ H )

5. What must the address field of an indexed addressing mode instruction be to

make it the same as a register indirect mode instruction ?

GROUP-II
1. Explain the difference between hardwired control and microprogrammed
control. Is it possible to have a hardwired control associated with a control
memory?
2. Using table 7.1 convert the following microoperations to register transfer
statements and to binary.
a. READ, INCPC
b. ACTDR, DRTAC
c. ARTPC,DRTAC, WRITE
3. Assume that the input logic of the microprogram sequencer of fig 7.8 has four
inputs, I2,I1,I0,T(test) , and three output, s 1,s0 , and L. the operations that are
performed in the unit are listed in the following table. Design the input logic
circuit using a minimum number of gates.
I2
0
X
1
0
1
0
1

I1
0
0
0
1
1
1
1

I0
0
1
0
0
0
1
1

Operation
Increment CAR if T=1, jump to AD if T=0
Jump to AD unconditionally
Increment CAR unconditionally
Jump to AD if T=1, increment CAR if T=0
Call subroutine if T=1, increment CAR if T=0
Return from subroutine unconditionally
Map external address unconditionally

4. Convert the following arithmetic expressions from reverse polish notation to

infix notation.
a. ABCDE+*-/
b. ABCDE*/-+
c. ABC*/D-EF/+
d. ABCDEFG+*+*+*
5. An instruction is stored at location 300 with its address field at location 301.
The address field has the value 400. A processor register R1 contains the
number 200. Evaluate the effective address if the addressing mode of the
instruction is (a) direct; (b) immediate; (c) relative; (d) register indirect; (e)
index with R1 as the index register.
GROUP-III
1. Define the following i. microoperation ii. Microinstruction iii. Microprogram
iv. Microcode.
2. Suppose that we change the ADD routine listed in table 7.2 to the
following two microinstruction.
ADD : READ I CALL INDR2
ADD U JMP FETCH
What should be subroutine INDR2?
3. Design a 7-bit combinational circuit incrementer for the microproram
sequencer of fig 7.8 (see fig 4.8). modify the incrementer by including a
control input D. when D=0, the circuit increments by one, but when D=1,
the circuit increments by two.
4. Convert the following numerical arithmetic expression into revere polish
notation and show the stack operations for evaluating the numerical
result.
(3+4)[10(2+6)+8]
5. Assuming an 8-bit computer, show the multiple precision addition of the
two 32-bit unsigned numbers listed below using the add with carry
instruction. Each byte is expressed as a two-digit hexadecimal number.
(6E C3 56 7A)+(13 55 6B 8F)
GROUP-IV
1. The microprogrammed control organization shown in fig 7.1 has the
following propagation delay times. 40ns to generate the next address,
10ns to transfer the address into the control address register, 40ns to
access the control memory ROM, 10ns to perform the required
microoperations specified by the control word. What is the maximum clock
frequency that the control can use?

2. The following is a symbolic microprogram for an instruction in the

computer defined
ORG 40
NOP S JMP FETCH
NOP Z JMP FETCH
NOP I CALL INDRCT
ARTPC U JMP FETCH
a. specify the operation performed when the instruction is executed.
b. Convert the four microinstruction into their equivalent binary form.
3. Insert an exclusive-OR gate between MUX and input logic of fig 7.8. one
input to the gate comes from the test output of the multiplexers. The
other input to the gate come from a bit labeled P(for polarity) in the
microinstruction from control memory. The output of the gate goes to the
input T of the input logic. What does the polarity control P accomplish?
4. In FIFO has a memory organization that stores information in such a
manner that the item that is stored first is the first item that is retrieved.
Show a FIFO memory operates with three counters. A write counter WC
holds the address for writing into memory. A read counter RC holds the
address for reading from memory. An available storage counter ASC
indicates the number of words stored in FIFO. ASC is incremented for
every word stored and decremented for every item that is retrieved.
5. Consider the two 8-bit numbers A=01000001 and B=10000100
a. Give the decimal equivalent of each number assuming that the (1)
they are unsigned, and (2)they are signed.
b. Add the two binary numbers and interpret the sum assuming that the
numbers are (1) unsigned, and (1) signed.
c. Determine the values of the c,z,s, and v tatus bit after the addition.
d. List the conditional branch instruction from table 8.11 that will have a
true condition.
GROUP-V
1. The system shown in fig 7.2 uses a control memory of 1024 words of 32 bits
each. The microinstruction has three fields as shown in the diagram. The
microoperations field has 16 bits.
a. How many bits are there in the branch address field and the select field?
b. If there are 16 status bits in the system, how many bits of the branch
logic are used to select a status bit?
c. How many bits are left to select an input for the multiplexers?
2. The computer discussed in chapter 7 has the following binary
microprogram:
address
60
61

Binary microprogram
010000010000010000
11
111100000010110000

00
001001000101001111
11
101110000111101111
00

62
63

a. Translate it to a symbolic microprogram as in table 7.2 (FETCH I in

address 64 and INDRECT in address 67)
b. List all the things that will be wrong when this microprogram is
executed in the computer.
3. A bus-organised CPU similar to fig.8-2 has 16 registers with 32 bits in
each,an ALU, and a destination decoder,
a. How many multiplexers are there in the A bus, and what is the size of
each multiplexer?
b. How many selection inputs are needed for MUX A and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU for data, including
input and output carries?
e. Formulate a control word for the system assuming that the ALU has 35
operations.
4. A computer has 32-bit instructions and 12-bit addresses. If there are 250
two-address instructions, how many one-address instructions can be
formulated?
5. The program in a computer compares two unsigned numbers A and B by
performing a subtraction A-B and updating the status bits. Let A=01000001
and B=10000100.
a. Evaluate the difference and interpret the binary result.
b. Determine the values of status bits C and Z.
c. List the conditional branch instructions from table 8.11 that will have a
true condition.
GROUP-VI
1. The control memory in fig 7. 2 has 4096 words of 24 bits each.
a. How many bits are there in the control address register.
b. How many bits are there in the each of the four inputs shown going
into the multiplexers?
c. What are the number of inputs in each multiplexer and how many
multiplexers needed?
2. Add the following instructions to the computer of chapter 7 dicussed (EA is
the effective address). Write the symbolic microprogram for each routine
as in table 7.2 . ( note that AC must not change in value unless the
instruction specifies a change in AC.)
symbol
AND
SUB
ADM
BTCL

opcode
0100
0101
0110
0111

Symbolic function
ACAC M[EA]
ACAC - M[EA]
M[EA]AC + M[EA]
ACAC

decription
AND
subtract
Add to memory
Bit clear

BZ
SEQ

1000
1001

BPNZ

1010

M[EA]
If (AC=0)then (PCEA)
If (AC=M[EA])then
(PCPC+1)
If (AC>0)then (PCEA)

Branch if AC zero
Skip if equal
Branch if positive and nonzero

3. The bus system of fig. 8.2 has the following propagation delay times:
30ns for the signals to propagate through the multiplexers, 80ns to
perform the ADD operation in the ALU, 20ns delay in the destination
decoder, and 10ns to clock the data into destination register. What is the
minimum cycle time that can be used for the clock?
4. Write a program to evaluate the arithmetic statement
X=

AB+C( DEF)
G+ HK

a.
b.
c.
d.

Using a general register computer with three address instructions.

Using a general register computer with two address instructions.
Using an accumulator type computer with one address instruction.
Using a stack organized computer with zero-address operation
instructions.
5. The program in a computer compares two signed numbers A and B by
performing the subtraction A-B and updating the status bits. Let
A=01000001 and B=10000100.
a. Evaluate the difference and interpret the binary result.
b. Determine the value of status bits ,z, and v.
c. List the conditional branch instructions from table 8.11 that will have a
true condition.
GROUP-VII
1. Using the mapping procedure described in fig 7.3 give the first
microinstruction address for the following operation code: a. 0010 b. 1011
c. 1111.
2. Write a symbolic microprogram routine for the ISZ (increment and skip if
zero) instruction defined in chapter 5(table 5.4). use the microinstruction
format of chapter 7. Note that DR=0 status condition is not available in
the CD field of the computer defined in ec 7.3. however , you can
exchange AC and DR and check if AC=0 with the z bit.
3. Specify the control word that must be applied to the processor of fig 8.2 to
implement the following microoperations.
a. R1R2+R3
b. R4R4
c. R5R5-1
d. R6shl R1
e. R7input
4. The memory unit of a computer has 256k words of 32 bits each. The
computer has an instruction format with four fields: an operation code

field, a mode field to specify one of seven addressing modes, a register

address field to specify one of 60 processor registers, and a memory
address. Specify the instruction format and the number of bit in each field
if the instruction is in one memory word.
5. Three computers use register window with the following characteristics.
Determine the window size and the total number of registers in each
computer

Global registers
Local registers
Common
registers
Number of
windows

Compute
r1
10
10
6

Computer
2
8
8
8

Computer 3

16

16
16
16

GROUP-VIII
1. Formulate the mapping procedure that provides eight consecutive
microinstructions for each routine. The operation code has six bits and the
control memory has 2048 words.
2. Write the symbolic microprogram routine for the BSA (branch and save
address) instruction defined in chapter.5 (table 5.4) use the
microinstruction format of section 7.3. minimize the number of
microinstructions.
3. Determine the microoperations that will be executed in the processor of
fig 8.2 when the following 14-bit control words are applied.
a. 00101001100101
b. 00000000000000
c. 01001001001100
d. 00000100000010
e. 11110001110000
4. A two-word instruction is stored in memory at an address designated by
the symbol w. the address field of the instruction(stored at w+1) is
designated by the symbol Y. the operand used during the execution of the
instruction is stored at an address symbolized by z. an index register
contains the value x. state how z is calculated from the other addresses if
the addressing mode of the instruction is
a) Direct
b) Indirect
c) Relative
d) Indexed
5. Give an example of a RISC I instructions that will perform the following
operations.
a. Decrement a register

b.
c.
d.
e.
f.

Complement a register
Negate a register
Clear a register to 0
Divide a signed number by 4
No operation

GROUP-IX
1. Explain how the mapping from an instruction code to a microinstruction
address can be done by means of a read-only memory. What is the
advantage of this method compared to the one in fig 7.3 ?
2. Show how outputs 5 and 6 of decoder F3 in fig 7.7 are connected to the
program counter PC.
3. Determine the microoperations that will be executed in the processor of
fig 8.2 when the following 14-bit control words are applied.
a. 00101001100101
b. 00000000000000
c. 01001001001100
d. 00000100000010
e. 11110001110000
Let SP=000000 in the stack of fig 8.3. how many items are there in the
stack if:
a. FULL=1 and EMTY=0?
b. FULL=0 and EMTY=1?
4. A relative mode branch type of instruction is stored in memory at an
address equivalent to decimal 750. The branch is made to an address
equivalent to decimal 500.
a. What should be the value of the relative address field of the
instruction(in decimal)?
b. Determine the relative address value in binary using 12 bits.( why
must the number be in 2s complement?)
c. Determine the binary value in PC after the fetch phase and calculate
the binary value of 500. Then show that the binary value in PC plus the
relative address calculated in part (b) is equal to the binary value of
500.
5. Write the RISC I instructions in assembly language that will cause a jump
to address 3200 if the z(zero) status bit is equal to 1.
a. Using immediate mode
b. Using a relative address mode(assume that PC=3400)
GROUP-X
1. Why do we need the two multiplexers in the computer hardware
configuration shown in fig 7.4? is there another way that information
from multiple sources can be transferred to a common destination?
2. Show how a 9-bit microprogram field in a microinstruction can be
divided into subfields to specify 46 microinstructions. How many
microoperations can be specified in one microinstruction?

3. The stack is organized such that SP always points at the next empty
location on the stack. This means that SP can be initialized to 4000 in
fig 8.4 and the first item in the stack is stored in location 4000 . list the
microoperations for the push and pop operations.
4. How many times does the control unit refer to memory when it fetches
and executes an indirect addressing mode instruction if the instruction
is (a) a computational type requiring an operand from memory; (b) a
branch type.
5. Examples of computers with variable instruction formats are IBM
370,VAX 11 , and intel 386. Compare the variable instruction format of
one of these computer with the fixed-length instruction format used in
RISC I.