ELEC3908F16W17Notes PDF

ELEC 3908 - Physical Electronics
Course Pack
Fall/Winter, 2015-2016
Instructor: Steven McGarry

Department: Electronics
ii
ELEC 3908 Course Pack
Table of Contents
I Lecture Notes .............................................................................................................................. 1
Chapter 1 Review of Basic Diode Theory ...................................................................................... 1
1.1 Diodes ................................................................................................................................................................. 1
1.2 Commercial Diodes ....................................................................................................................................... 3
Chapter 2 Semiconductors ................................................................................................................. 5
2.1 Atomic Shells, Subshells and Orbitals ................................................................................................... 5
2.2 Bonding .............................................................................................................................................................. 6
2.3 Types of Semiconductors ........................................................................................................................... 9
2.4 Group IV Semiconductor Bands ........................................................................................................... 12
Chapter 3 Energy Band Diagrams and Doping .......................................................................... 13
3.1 Energy Band Diagrams ............................................................................................................................. 13
3.2 Intrinsic Material ........................................................................................................................................ 15
3.3 Donor Doped Material .............................................................................................................................. 15
3.4 Acceptor Doped Material ........................................................................................................................ 16
3.5 Compensated Doping ................................................................................................................................ 17
Chapter 4 Basic Integrated Circuit Processing .......................................................................... 19
4.1 Wafer Fabrication ....................................................................................................................................... 19
4.2 Photolithography ........................................................................................................................................ 20
4.3 Etching ............................................................................................................................................................ 21
4.4 Thermal Oxidation ..................................................................................................................................... 22
4.5 Diffusion and Ion Implantation ............................................................................................................ 24
4.6 Deposition ...................................................................................................................................................... 25
4.7 Scribing and Cleaving ............................................................................................................................... 25
Chapter 5 Planar Diode Fabrication .............................................................................................. 27
5.1 Substrate Diode ........................................................................................................................................... 27
5.2 Well Diode ..................................................................................................................................................... 28
5.3 Epitaxial Diode ............................................................................................................................................. 29
Chapter 6 Doping Profiles and 1D Approximation .................................................................. 31
6.1 3D, 2D and 1D Doping Profiles ............................................................................................................. 31
6.2 Uniform Doping Approximation .......................................................................................................... 32
6.3 Junction Area Scaling ................................................................................................................................ 33
6.4 Design with Diode Area ........................................................................................................................... 34
Chapter 7 Generation, Recombination and Diffusion ............................................................. 36
7.1 Generation and Recombination ........................................................................................................... 36
7.2 Diffusion ......................................................................................................................................................... 37
7.3 Diffusion Length .......................................................................................................................................... 39
Chapter 8 Diode Operation .............................................................................................................. 41
8.1 Equilibrium ................................................................................................................................................... 41
8.2 Forward Bias ................................................................................................................................................ 42
8.3 Reverse Bias .................................................................................................................................................. 44
Chapter 9 Depletion Region GR and Parasitic Resistance ..................................................... 46
9.1 Depletion Region GR ................................................................................................................................. 46
9.2 Parasitic Resistance ................................................................................................................................... 47
Chapter 10 Diode Model Parameter Extraction ........................................................................ 51
10.1 Model Parameter Extraction ............................................................................................................... 51
10.2 Extraction of Ideal Diode Model Parameters ............................................................................... 51
10.3 Linear Regression .................................................................................................................................... 53
Chapter 11 pn-Junction Electrostatics .......................................................................................... 56
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iv

11.1 Poissons Equation .................................................................................................................................. 56
11.2 The Depletion Approximation ............................................................................................................ 57
11.3 Qualitative Junction Electrostatics ................................................................................................... 57
11.4 Quantitative Junction Electrostatic Results .................................................................................. 58
Chapter 12 Diode Reverse Breakdown ........................................................................................ 61
12.1 Reverse Bias Junction Electrostatics ............................................................................................... 61
12.2 Avalanche Breakdown ........................................................................................................................... 62
Chapter 13 Diode Small Signal Modelling ................................................................................... 65
13.1 Small Signal Conductance .................................................................................................................... 65
13.2 Depletion Capacitance ........................................................................................................................... 65
13.3 Small Signal Equivalent Circuit .......................................................................................................... 68
Chapter 14 Diode Switching ............................................................................................................. 70
14.1 The pn-Junction Charge Control Equation .................................................................................... 70
14.2 Turn Off Transient ................................................................................................................................... 71
14.3 Turn On Transient ................................................................................................................................... 73
Chapter 15 BJT Structure and Fabrication .................................................................................. 75
15.1 BJT Structure ............................................................................................................................................. 75
15.2 Fabrication of the Vertical npn Structure ...................................................................................... 76
15.3 BJT Nomenclature ................................................................................................................................... 76
Chapter 16 Bipolar Transistor Operation ................................................................................... 79
16.1 Regions of Operation .............................................................................................................................. 79
16.2 Forward Active Operation ................................................................................................................... 80
16.3 Reverse Active Operation ..................................................................................................................... 81
16.4 Saturation Operation .............................................................................................................................. 82
16.5 Cutoff Operation ....................................................................................................................................... 82
Chapter 17 Bipolar Transistor Injection Models ...................................................................... 83
17.1 Current Components .............................................................................................................................. 83
17.2 Basic Injection Model ............................................................................................................................. 83
17.3 Simplifications for Operating Regions ............................................................................................ 85
17.4 The Ebers-Moll Model ............................................................................................................................ 88
Chapter 18 The Early Effect, Breakdown and Self-Heating ................................................... 90
18.1 The Early Effect ......................................................................................................................................... 90
18.2 Avalanche Breakdown ........................................................................................................................... 90
18.3 Self-Heating ................................................................................................................................................ 93
Chapter 19 BJT Base Resistance and Small Signal Modelling ............................................... 96
19.1 Base Resistance ........................................................................................................................................ 96
19.2 Low Frequency Small Signal Equivalent Circuit ......................................................................... 98
19.3 High Frequency Small Signal Equivalent Circuit ........................................................................ 99
19.4 Transit Frequency ................................................................................................................................. 101
Chapter 20 MOSFET Structure and Processing ...................................................................... 103
20.1 Structure .................................................................................................................................................... 103
20.2 Fabrication ................................................................................................................................................ 104
20.3 Mask Layout, Geometry and Symbols ........................................................................................... 105
Chapter 21 MOSFET Operation .................................................................................................... 107
21.1 Drift Conduction ..................................................................................................................................... 107
21.2 Threshold Voltage ................................................................................................................................. 108
21.3 Electric Fields in the MOSFET .......................................................................................................... 109
21.4 MOSFET Operation ................................................................................................................................ 109
21.5 Regions of Operation and Current Characteristics ................................................................. 111
Chapter 22 MOSFET Threshold Voltage .................................................................................... 112

22.1 The Fermi Level ...................................................................................................................................... 112
22.2 Work Function Difference .................................................................................................................. 113
22.3 The Flat Band Condition and Band Bending in the MOS Structure .................................. 114
22.4 Substrate Depletion Charge ............................................................................................................... 115
22.5 Threshold Voltage Calculation ......................................................................................................... 116
Chapter 23 The MOSFET Square Law Model ........................................................................... 117
23.1 Co-ordinate System and Model Assumptions ............................................................................ 117
23.2 Triode Region Model ............................................................................................................................ 117
23.3 The Square Law Pinchoff Condition .............................................................................................. 121
23.4 Saturation Region Model .................................................................................................................... 121
Chapter 24 Channel Shortening and dc Parameter Extraction ......................................... 123
24.1 Channel Shortening ............................................................................................................................... 123
24.2 MOSFET Parameter Extraction ........................................................................................................ 124
Chapter 25 Short Channel Threshold Voltage Effects .......................................................... 126
25.1 Charge Sharing in the MOSFET Channel ...................................................................................... 126
25.2 The Trapezoidal Depletion Charge Model .................................................................................. 126
25.3 Length and Bias Dependence ........................................................................................................... 128
25.4 Mitigation of the Short Channel VT Effect .................................................................................... 128
Chapter 26 MOSFET Small Signal Model ................................................................................... 130
26.1 Low Frequency Small Signal Equivalent Circuit ....................................................................... 130
26.2 Source/Drain Depletion Capacitance ............................................................................................ 130
26.3 Extrinsic MOSFET Capacitance ........................................................................................................ 131
26.4 Intrinsic MOSFET Capacitance ......................................................................................................... 132
26.5 High Frequency Small Signal Equivalent Circuit ...................................................................... 133
Chapter 27 Scaling and Velocity Saturation ............................................................................ 134
27.1 Constant Field MOSFET Scaling ....................................................................................................... 134
27.2 MOSFET Velocity Saturation ............................................................................................................. 135
Chapter 28 Process Variation, Testing, Packaging and Reliability .................................. 138
28.1 Process Variation ................................................................................................................................... 138
28.2 Testing and Packaging ......................................................................................................................... 138
28.3 Reliability Modelling ............................................................................................................................ 139
28.4 Electromigration .................................................................................................................................... 140
28.5 Hot Carrier Effects ................................................................................................................................. 140
28.6 Electrostatic discharge (ESD) ........................................................................................................... 142
II Sample Problems ................................................................................................................ 144

Chapter 1 Problems ......................................................................................................................... 144
Chapter 10 Problems ....................................................................................................................... 156
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Chapter 15
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Chapter 23
Chapter 24
Chapter 25
Chapter 26
Chapter 27
Chapter 28
Problems ....................................................................................................................... 163

Problems ....................................................................................................................... 164
Problems ....................................................................................................................... 165
Problems ....................................................................................................................... 167
Problems ....................................................................................................................... 169
Problems ....................................................................................................................... 170
Problems ....................................................................................................................... 172
Problems ....................................................................................................................... 173
Problems ....................................................................................................................... 174
Problems ....................................................................................................................... 175
Problems ....................................................................................................................... 176
Problems ....................................................................................................................... 178
Problems ....................................................................................................................... 179
Problems ....................................................................................................................... 180
III Solutions to Sample Problems ...................................................................................... 181

Chapter 1 Solutions .......................................................................................................................... 181
Chapter 10 Solutions ....................................................................................................................... 196
IV Physical Constants and Material Properties ............................................................ 230
V Laboratory Instructions ................................................................................................... 231
Lecture Notes
Chapter 1 Review of Basic Diode Theory

1.1
Diodes
A diode, or pn-junction, is a device constructed from regions of p and n-type semiconducting

materials that are in electrical contact.
Figure 1.1 shows the schematic symbol, positive current/voltage conventions, and identities of the
p and n-type materials for the pn-junction. A VD that raises the potential of the p-type with respect to
the n-type is termed a forward bias, and the resulting current is considered positive. The converse is a
reverse bias, and the resulting ID is negative.
Figure 1.1: Diode symbol
The simplest useful (non-piecewise) model for the relationship between applied voltage and
current flow in a diode is the simple ideal diode equation, given by
ID = IS (e qVD
kT
1)
(1.1)
where IS is the saturation current (A) and T is absolute temperature (K). If ID vs VD is plotted on
linear axes using IS = 10-12 A and T =300K as an example, Figures 1.2(a) and 1.2(b) are obtained.
Although thesharp increase in ID at higher biases is shown, the linear scale disguises some other
useful information, and two plots are required to identify both the forward and reverse
characteristics. Plotting |ID| on a log scale yields Figure 1.2(c). The effect of the log scale is to
compress the large range of current values. The shape near ID = 0 is due to log(0) .
Review of Basic Diode Theory
(a) Forward and reverse bias.
(b) Reverse bias only.
(c) Log axis
Figure 1.2: Plots of the simple ideal diode characteristic

Using the approximations exp( x ) << 1 for x 3 and exp( x ) >> 1 for x 3 , two simplifications
of equation (1.1) can be identified. For VD 3kT q , the exponential is negligible compared to 1, and
ID IS . For VD 3kT q , the exponential dominates 1, so taking the natural logarithm of both
sides of (1.1) with VD 3kT q yields:
" q%
ln( ID ) = ln( IS ) + $ 'VD
# kT &
VD
3kT
q
(1.2)
Equation (1.2) predicts that a plot of ln( ID ) vs. VD for VD 3kT q will be linear with slope
q kT and intercept
ln(IS ) .
Figure 1.3(a) is an enlargement of the behavior of equation 1.7 around VD = 0. The plot also shows
the position of +/-3kT/q on the voltage axis. Figure 1.3(b) illustrates the point that if the linear
the resulting
characteristic is projected back to the VD origin,

ID intercept is the saturation current IS.
(a) Enlargement of VD0
(b) Projection of linear portion
Figure 1.3: Details of the simple ideal diode forward bias characteristic with |ID| on a log axis
Example 1.1:
A diode has
the error in
ID
IS = 1012 A . What is the error in VD compared to VD 0.7 V for ID = 10 mA ? What is

if
VD = 0.7 V
is assumed?
Solution:
For ID = 10 mA, (1.1) is rewritten to give
VD =
kT " ID % 1.379 1023 300 " 102 %

ln$1+ ' =
ln$1+ 12 ' = 0.60 V
q # IS &
1.6 1019
# 10 &
The error is approximately 18%. If VD = 0.7 V is assumed,
ID = IS (e qVD
kT
1) = 607 mA
Therefore VD = 0.7 V cannot be assumed and substituted into the exponential, or the results can be
unusable.
1.2
Commercial Diodes
Some interesting results are obtained if the current versus voltage characteristics are measured for
different commercial discrete diodes. Table 1.1 lists a few commonly available discrete diodes.
Table 1.1: Three commercial discrete diodes and their suggested applications.
The plotted characteristic of the logarithm of the current against the voltage of each of the diodes
in Table 1.1 will show differences from the expected behavior:
Although all will results show the linear region predicted by equation (1.2), the slope will not
be q/kT as expected, and will be different for different diodes.
The intercept projected onto the ID axis is predicted by (1.2) to be IS. This value is different
for different devices, implying that IS must be different.
Each characteristic will cease to be linear above some value of VD.
Review of Basic Diode Theory
Taken together, these observations suggest that the characteristics of the individual devices should
be investigated. If ID-VD data is measured for each of the devices and the results plotted in the form of
Figure 1.2(c), the result is Figure 1.4.
Figure 1.4: Measured ID (log scale) vs VD for each of the diodes in Table 1.1.
Again, the data in Figure 1.4 suggests some observations
The saturation current IS is clearly not constant from device to device. This implies that IS is a
function of the particular structure of a device, and not a fundamental property of devices in
general.
The slope of ln(ID) vs VD is generally not q/kT as predicted by the simple ideal diode
equation, (1.1). Furthermore, the slope is different for different devices, so a single constant
modification of (1.1) will not solve the problem.
There is some other effect occurring at high values of VD, which is not accounted for in the
simple ideal diode equation, causing the current to rolloff.
In order to formulate a more accurate model of the diodes behavior, and thus obtain a better
prediction of the performance of a circuit containing a diode, it is necessary to look in more detail at
the nature of the saturation current term IS, and other physical effects which can account for the nonkT/q slope and high current rolloff. To understand these we must first step back and consider the
nature of semiconductor materials and how they are used to fabricate devices.
Chapter 2 Semiconductors
2.1
Atomic Shells, Subshells and Orbitals
In individual atoms the electrons occupy shells. The electron shells are labeled K, L, M, N, O,
P, and Q; or 1, 2, 3, 4, 5, 6, and 7; going from innermost shell outwards (Figure 2.1). Electrons in
outer shells have higher average energy and travel farther from the nucleus than those in inner shells.
This makes them more important in determining how the atom reacts because the pull of the atom's
nucleus upon them is weaker and more easily broken. In this way, a given element's reactivity is
highly dependent upon its electronic configuration.
Figure 2.1: Atomic shell diagram

Each of the shells contains one or more subshells labeled s, p, d, f, and g; which contain 1, 3, 5, 7,
and 9 orbitals, respectively (Table 2.1). An orbital can contain one or two electrons; if two are
present they must be of opposite spin.
(a)
(b)
Table 2.1: Atomic shells (a) and subshells (b).
The shapes of the orbitals for the various subshells are illustrated in Figure 2.2.
Semiconductors
Figure 2.2: Atomic orbital geometries

The relative ground state energies of the electrons in an isolated atom have discrete values for
each atomic orbital. The highest energy shell that is occupied by at least one electron is called the
valence shell and the orbitals within it are called valence orbitals. The atomic orbital energies for the
alkali metals lithium (Li) and sodium (Na) are shown in Figure 2.3 (with hydrogen shown for
reference).
Figure 2.3: Valence atomic-orbital energies of Lithium (Li) and Sodium (Na)
2.2
Bonding
The outer, valence electrons are responsible for connecting individual atoms together to form
solids. When atoms are bonded together into a solid, the number of possible energies of the valence
electrons increases due to the influence of the added atoms. For a very large number of atoms, as is
the case for a crystal, the energy levels almost merge forming bands as shown in Figure 2.4.
Figure 2.4: Energy level splitting of valence electrons to form a band.

A simple example illustrating crystal bonding is the formation of solid lithium by adding
individual atoms. Lithium has only three protons and three electrons therefore, in the ground state,
the 1s orbital is filled with two electrons having opposite spins and the third electron half fills the 2s
orbital. As shown in Figure 2.5, adding a second Li atom causes the 2s orbital to split into two orbital
of different energies (the lower called the bonding orbital and the upper called the antibonding
orbital) and both of the electrons normally occupy the bonding orbital. As more atoms are added the
allowed energy levels for the combined system continue to multiply and become closer in energy
until the separation becomes so small (<kT) that they are almost continuous and we call the group of
levels a band. The formation of the energy band corresponds to delocalization of valence electrons
over increasing numbers of Li atoms. A 1-mg sample of Li would contain nearly 1020 atoms.
Figure 2.5: Molecular-orbital energies corresponding to delocalization of valence electrons over

increasing numbers of Li atoms.
Note that the energies of the 2p orbitals also split as we add atoms to the crystal, but in the case of
lithium this has no effect since the 2s valence orbital is only half full. Because the valence orbital of
lithium is not filled, the resulting valence band in the crystal is also not filled and lithium is a true
metal.
Semiconductors
The element beryllium is the next highest atomic number to lithium with one more proton and
electron. In this case the 2s orbital is filled so as we add more atoms to form a beryllium crystal the
resulting valence band is also filled. In the case of beryllium 2s band overlaps the 2p band, as shown
in Figure 2.6, so there are many available energy states for electrons to allow for motion and
therefore conduction. Since the conduction is due to band overlap rather than filling, beryllium is
called a bivalent metal or semi-metal.
Figure 2.6: Molecular-orbital energies corresponding to delocalization of valence electrons over

increasing numbers of Be atoms.
In semiconductors and insulators the energy levels still split and the bands are formed when a
large number of atoms are bonded together, but in these cases the valence band no longer overlaps
the next highest band. This is illustrated for silicon in Figure 2.7.
Figure 2.7: Energy band formation with increasing numbers of Si atoms.
At very low temperatures semiconductors have no mobile electrons since the valence band will be
full so it will behave as an insulator. In general, if the energy difference between the valence band
and the next band is large compared to the thermal energy, kT, then the material will be an insulator.
Figure 2.8 summarizes the relationship of the bands and electrons for metals, semi-metals,
semiconductors and insulators.
Figure 2.8: Band and electron relationship of materials
2.3
Types of Semiconductors
There are many different forms of semiconductor including amorphous, polycrystalline and
crystalline structures composed of organic or inorganic materials. This course will concentrate on
crystalline inorganic materials. The most popular of these materials to date have been:
III-Vs (a combination of Group III and Group V materials - GaAs, InP, etc.)
II-VIs (a combination of Group II and Group VI materials - CdTe, ZnS, etc.)
Group IV (C, Si, Ge)
Figure 2.9 shows a section of the periodic table that includes most of the interesting elements used
to make these semiconductors along with their shell structures. In all of the materials used the net
average valence is four. In other words, for every group III atom there needs to be a corresponding
group V atom and for every group II atom there needs to be a corresponding group VI. In this way
bonding orbital filling is achieved.
10
Semiconductors
Figure 2.9: Main group of elements forming group IV, III-V and II-VI semiconductors
The III-V and II-VI materials have achieved popularity for some specialized applications where
they have had a benefit over Group IV materials particularly in optoelectronics. These materials
normally crystallize into a zincblende structure, as shown in Figure 2.10. This is a tetragonally
bonded structure where all bonds are to the complementary atomic species.
Figure 2.10: Zincblende bonding structure of III-V or II-VI semiconductors

The most popular semiconductor materials are from Group IV of the periodic table. These
materials normally crystallize into a diamond structure, as shown in Figure 2.11. This is also a
tetragonally bonded structure essentially identical to zincblende except that all atoms are the same.
Figure 2.11: Diamond bonding structure of Group IV semiconductors
11
12
Semiconductors
2.4
Group IV Semiconductor Bands
In a similar manner to looking at making a crystal by adding atoms, as we did previously, we can
look at what happens to the energies in the bonding structure for group IV elements as their
separation is reduced. As isolated atoms are brought closer together their orbitals overlap and spread
in energy, as illustrated in Figure 2.12. Once the diamond structure crystal is formed the atoms have
an average separation determined by the energy minimum of the crystal lattice at the ambient
termperature present. This separtion determines the energy difference between the valence electron
band and the next empty band. Generally, the smaller the atom the stonger the bonding and the larger
the energy separation will be. As shown in Figure 2.12 group IV crystals can form a variety of band
structures depending of the element:
Carbon (C) Insulator (Eg 5.5eV)

Silicon (Si) Semiconductor (Eg 1.1eV)
Germanium (Ge) Semiconductor (Eg 0.67eV)
Tin (Sn) Semi-metal (Eg 0.0eV)
Figure 2.12: Bonding and band formation in Group IV semiconductors

The remainer of the course will concentrate on the properties and use of silicon as the main
semiconductor used in the world today.
Chapter 3 Energy Band Diagrams and Doping

3.1
Energy Band Diagrams
As discussed in Chapter 2, when an electron is bound to a nucleus, it may only exist at a finite
number of energy levels, as illustrated in 3.1(a). Each level contains a number of orbitals that can
contain electrons. When atoms are brought together to form a crystal (1022 atoms/cm3 for silicon),
the allowed energy levels of each atom are perturbed by nuclear interaction, resulting in a crystal
characterised by bands of allowed energy levels, as indicated in Figure 3.1(b). The bands are regions
in which energy is essentially continuously variable, and are separated from each other by energy
gaps.
For semiconducting materials, two bands are important: the band containing the electrons participating in covalent bonding, the valence band, and the band at the next higher energy, the conduction
band. For a first analysis, the most important feature of these bands is their energy separation. The
final energy band diagram is therefore a simplification of Figure 3.1(b) showing only the highest
energy in the valence band, labeled Ev, and the lowest energy in the conduction band, labeled Ec, as
shown in Figure 3.1(c). The value for Eg in silicon at 300K is approximately 1.08 eV.
(a) Atomic
(b) Crystal
(c) Energy band diagram
(d) Electron transitions
Figure 3.1: Energy levels and the energy band diagram
Electron movement from the valence to conduction bands may be visualized on the energy band
diagram as shown in Figure 3.1(d). At a temperature T > 0 K, some valence band electrons will
acquire energy Eg, and move to the conduction band. The electron will then occupy an orbital in the
conduction band, leaving behind an empty valence band orbital. At a given temperature, the process
of movement between the bands will be a dynamic equilibrium. The relatively large value of Eg
means that the density of electrons in the valence band is much larger than that in the conduction
band.
An equivalent representation of electron transition is the bonding model view of Figure 3.2.
Separate diagrams are drawn for the valence and conduction orbital sets to show the effect of an
13
14
Energy Band Diagrams and Doping

electron transition out of the valence band. Note that the valence and conduction views coexist
together in space, so that a movement from one to the other does not necessarily imply a spatial
translation.
Figure 3.2: Valence to conduction band transitions on an orbital bonding model.

Electrical conduction in a semiconductor at T > 0 K occurs via electron movement within the
valence and conduction bands. In the conduction band, electron density is usually much lower than
the density of orbitals, so movement is straightforward, as shown in Figure 3.3. In the valence band,
electrons usually outnumber empty orbitals, and electron movement is more efficiently characterised
by the apparent movement of an empty orbital, termed a hole, by successive electron occupations. As
shown in Figure 3.3, the hole propagates in the opposite direction to electron flow. The hole is
considered a positively charged particle, since nuclear protons outnumber electrons by 1 when a
valence band orbital is empty. With this view, the important densities are n, the density of conduction
band, and p, the density of valence band holes.
Figure 3.3: Conduction electrons
3.2
Intrinsic Material
In pure, or intrinsic silicon, conduction band electrons and valence band holes must be created in
pairs, since the only available mechanism is a transition from the valence to conduction bands, and
thus
(3.1)
n = p ni
where n i is termed the intrinsic density, with n i 1.45 1010 /cm3 in silicon at 300K. Although
np = n i
(3.2)
follows for intrinsic material from(3.1), it is also a more general result termed the mass-action
law.
3.3
Donor Doped Material
Atoms from group V of the period table have one more nuclear proton and valence band electron
than silicon. Introduced into a silicon lattice with density ND, creating an extrinsic material, group V
atoms will each have one electron left over after lling the covalent bonds with their neighboring
silicon atoms. These leftover electrons, since they are not participating in crystal bonding, will be
only weakly bound to their parent atom nuclei, and can therefore be promoted to the silicon
conduction band, or ionized, with very little energy increase. A group V atom is therefore called a
donor.
Figure 3.4(a) shows the donor ionization process in a bonding model. Before ionization, the extra
electron associated with the donor atom is still part of the donors orbital structure. After ionization,
the extra electron becomes part of the silicon conduction band orbital structure. The same process
can also be depicted on the energy band diagram, as shown in Figure 3.4(b). The electrons associated
with the donor atoms exist at a donor energy level ED just below Ec.
(a) Orbital model.
(b) Bonding model.
Figure 3.4: Representations of donor doping.

In donor doped material, providing N D >> n i and assuming complete ionization (which is valid at
room temperature), n = ND. The mass action law (3.2) also applies to doped material, so
15
16
p = n i2 n = n i2 N D . Since N D >> n i has been assumed, n >> p , so the material is termed n-type,
(conduction band) electrons are the majority carriers and holes are the minority carriers.
Example 3.1:
A sample of silicon is doped with 1016 cm-3 of Arsenic, a group V atom. What are n and p?
Solution:
A group V atom is a donor, so the resulting material is n-type. The electron density is therefore equal
to the donor doping, and the hole density is given by the mass action law
!"
!!
= 10 cm , =
!.!"!"!"
!"!"
= 2.110! cm!!
Note that n is approximately 12 orders of magnitude larger than p for this n-type material.
3.4
Acceptor Doped Material
Atoms from elements in group III of the period table have one fewer nuclear proton and one fewer
valence band electron than silicon. Introduced into a silicon lattice with density NA, group III atoms
will each have an empty valence band orbital compared to their neighboring silicon atoms. The
ionization process of accepting a silicon valence band electron into an empty orbital can be
accomplished with very little energy increase; hence group III atoms are termed acceptors. Figures
3.5(a) illustrates the process on the energy band diagram, where the acceptor energy level just above
Ev is labeled EA, while Figure 3.5(b) shows the process in the orbital bonding model.
(a) Orbital model.
(b) Bonding model.
Figure 3.5: Representations of acceptor doping.

For acceptor doped material, providing N A >> n i , complete ionization leads to p = N A , and the
2
2
mass-action law to n = n i p = n i N A . Holes are the majority carriers, electrons the minority
carriers, and the material is termed p-type.
Example 3.2:
A sample of silicon is doped with 4x1016 cm-3 of Gallium, a group III atom. What are n and p?
Solution:
A group III atom is an acceptor, so the resulting material is p-type. The hole density is therefore equal
to the acceptor doping, and the electron density is given by the mass action law
= 410!" cm!! , =
!.!"!"!"
!!"!"
= 5.310! cm!!
Note that p is almost 13 orders of magnitude larger than n for this p-type material.
3.5
Compensated Doping
In practice it is quite often the case that a region of semiconductor will be doped with both donors
and acceptors, for reasons that will become clearer when the structure of integrated devices is
considered.
Such a material is referred to as compensated. The energy band diagram can be used to visualize
what happens in compensated material by representing the donors and acceptors at their respective
energy levels ED and EA.
As shown in the Figure 3.6 for the case where ND > NA, donors will lose their electrons to
acceptors until all the acceptors have been ionized, then the remaining ND-NA donors will be
available to create conduction band electrons. To first order, the material therefore appears to have
been doped n-type with an effective doping ND-NA. Thus n=ND-NA and p follows from the massaction law (3.2). If NA>ND, acceptors will acquire electrons from donors until all donors are ionized,
the remaining NA-ND will be available to create valence band holes. The material will therefore
appear to have been doped p-type, with an effective doping NA-ND. Thus, p = NA-ND and n follows
from the mass-action law.
Figure 3.6: Compensation
17
18
Example 3.3:
16
16
A material is doped with 3x10 cm-3 of Phosphorous (group V) and 6x10 cm-3 of Boron (group III). Is the
material n or p-type? What are the concentrations of electrons and holes, and which are the majority and
minority carriers?
Solution:
Phosphorous is a group V atom, so it acts as a donor. Boron is a group III atom, so it acts as an acceptor.
16
16
The dopant densities are therefore ND = 3x10 cm-3 and NA = 6x10 cm-3. Since NA > ND, the material is p-type,
making holes the majority carriers and electrons the minority carriers. The densities are given by
= ! ! = 310!" cm!!
! !
1.4510!" !
=
=
710! cm!!
310!"
Chapter 4 Basic Integrated Circuit Processing

4.1
Wafer Fabrication
The starting material for most integrated circuits is usually a thin round disk of ultra pure,
crystalline semiconductor material called a wafer, or substrate. To obtain these wafers, a long,
cylindrical ingot (or boule) is produced using a process a process shown in simplified form in Figure
4.1.
Figure 4.1: Ingot growth

In ingot growth, ultrapure silicon and a controlled amount of dopant are melted in a quartz
crucible. A small, well-formed seed crystal, created by other means, is suspended just touching the
surface of the melted silicon/dopant mixture. The seed crystal is then rotated and pulled
(approximately revolution/second and 1m/hr, respectively) from the surface of the melt, resulting
in the growth of crystalline material. Initially, the pull speed and rotation rate are adjusted to cause
the ingot diameter to increase, then once the final desired diameter is reached, the pull and rotation
rate are stabilized. Ingots are manufactured in diameters from 75mm (about 3) to 300mm (about
12), with the ingot being approximately 1m long. As the ingot is pulled from the silicon melt, it may
also be reheated, in a process termed float zone refining, to repair crystal defects, known as
dislocations, in the ingot.
Wafers are created by slicing the ingot using a diamond tipped saw, as depicted in Figure 4.2. The
wafers produced are generally between 500 and 1000 m (0.5-1.0 mm) thick. After a wafer is sawed
from the ingot the wafer is polished, using a combined chemical-mechanical polishing (CMP) step,
to give a surface that is extremely flat. Any wafers that are flawed, whether due to a problem in the
crystal structure of the ingot or some damage in the sawing process, are discarded at this stage.
Figure 4.2: Wafer Sawing
19
20
Basic Integrated Circuit Processing

The fabrication of semiconductor wafers, although extremely well developed, is still a very
specialized manufacturing challenge, and only the largest integrated circuit manufacturers create
their wafers in-house. The majority of IC manufacturers buy wafers of a specific size and doping
from a company that specializes in wafer production.
4.2
Photolithography
Photolithography is the photographic transfer of an image to a layer on the surface of the wafer. It
is the mechanism by which geometrical information representing an integrated circuit design is
transferred to a physical realization.
The basic steps in photolithography are outlined in Figure 4.3. A surface is coated with 1-2 m of
photoresist, or PR, a material sensitive to a certain wavelength of illumination, as shown in Figure
4.3(a). Note that the wafer is 0.5-1 mm thick, so these diagrams are not to scale. PR application is
generally accomplished by dropping the PR onto the center of the wafer, which is then spun for a few
seconds to spread the material. The PR is then exposed using a mask containing geometrical
information, analogous to a photographic negative, as shown in Figure 4.3(b). The PR undergoes a
chemical change were it is exposed to the illumination. In the development step, a chemical
developer removes PR, as shown in Figure 4.3(c). A negative PR is hardened against the developer
by the illumination, while a positive PR is weakened. The type of PR determines whether an opaque
region in the mask corresponds to an area that survives development or is removed during
development. Figure 4.3(c) shows a negative PR example. The result, shown in Figure 4.3(d) is an
area of PR on the substrate surface corresponding to a geometric figure in the mask.
(a) PR application
(b) Exposure
(c) Development
(d) Final result
Figure 4.3: Basic steps in the photolithography process using a negative resist.
Masks are often created from a reticle, illustrated in Figure 4.4, containing all geometrical
information for a particular photolithography step. The reticle is usually 10x the size of the eventual
mask, to allow greater precision of features during its creation. The reticle is then used to form the
mask, a full sized photographic plate containing many images of the reticle, one for each eventual
chip. A photoreduction system is used to shrink the size of the reticle image, and the mask is
mounted on a movable platform (or the projected image can be refocussed in different locations) to
allow projection of the reticle image in different locations.
10 cm
Figure 4.4: 10X Reticle

Figure 4.5(a) shows a simplified view of the system used for reticle projection onto the mask. This
step-and-repeat process results in a 1X mask containing an array of reticle images reduced to actual
size, as shown in Figure 4.5(b).
(a) Step and repeat process.
(b) Final mask
Figure 4.5: Creation of the final mask

Modern masks are often written directly using a focused electron beam to write into an
appropriate photoresist on the final mask, eliminating the need for step and repeat of the reticle.
These are called direct-write e-beam masks.
4.3
Etching
The term etching describes the process of selectively removing material from the surface of the
integrated circuit (IC).
Figure 4.6 shows a simplified view of the dry etching process. Ions of an inert gas such as Argon
are accelerated toward the surface. If they strike the surface with sufficient velocity, i.e. if they
possess enough kinetic energy, the impact of the ion on the surface will cause ejection of an atom
from the surface layer. Although a chemical reaction may occur at the surface due to heating, the
primary mechanism of material removal is by a physical process.
21
22
Figure 4.6: Dry etch

Figure 4.7 illustrates the wet etching process. Wet etching uses a chemical reaction to remove
surface material. In wet etching, the chemical used for the etchant is chosen with the surface material
in mind -many different materials need to be etched when making an integrated circuit, and no one
chemical will etch all the materials.
Figure 4.7: Wet etch

Etching is characterised by selectivity, the ability to remove one material while leaving another
material intact, and anisotropy, etching laterally as well as vertically, as illustrated in Figure 4.8. Wet
etching can be more selective, but is generally less anisotropic, with the opposite true of dry etching.
(a)
(b)
(c)
(d)
Figure 4.8: Etching: (a) initial, (b) isotropic, (c) anisotropic, (d) unselective
4.4
Thermal Oxidation
Thermal oxidation refers to the growth of silicon dioxide (SiO2, oxide) on a region of silicon
wafer. Growth is performed in an oxidation furnace, illustrated in Figure 4.9(a). The wafers are
loaded on to a quartz boat, which is rolled into a furnace tube approximately 2m long. The system is
heated to typically 900-1200 C in the presence of pure oxygen (dry oxidation), or steam (wet
oxidation). Oxidation proceeds by consuming part of the silicon wafer, and growth is approximately
symmetrical around the original wafer surface. The key differences between wet and dry oxidation
are the growth rate and the quality of oxide. Compared at the same temperature, wet oxidation grows
an oxide layer approximately 5 to 10 times faster than dry oxidation, as shown in Figure 4.9(b), but
produces a lower quality oxide.
(a) Furnace
(b) Rates
Figure 4.9: Thermal Oxidation

Thermal oxidation occurs wherever the silicon surface is exposed to the oxygen ambient.
However, if the photolithography technique described in Section 4.2 is used prior to oxidation to
form patterned regions of a masking material such as silicon nitride (Si3N4), oxidation will only
occur in the areas not covered by this masking layer. This local oxidation of silicon, or LOCOS,
process, depicted in Figure 4.10, can be used to form oxide through thermal oxidation in selected
areas of the wafer surface. Since the oxide will grow laterally as well as vertically, some oxide will
grow under the edge of the masking layer, as shown in the enlargement in Figure 4.10. This is termed
the birds beak effect, and sets a limit on the minimum width of region that can be formed by this
method.
Figure 4.10: Local Oxidation of Silicon (LOCOS)
23
24
4.5
Diffusion and Ion Implantation
The ingot growth method described in Section 4.1 can be used to obtain semiconductor substrates
doped with either donors or acceptors. However, creation of integrated devices requires selective
formation of regions of p and n-type material.
Diffusion is a general process that causes particle movement to reduce a concentration gradient,
and will be discussed in detail in section 7.2. In semiconductor processing, diffusion refers to the
introduction of dopant into a region of semiconductor material by heating the material to a relatively
high temperature (1000-1200 C) in the presence of gaseous dopant atoms. Since the concentration of
dopant is greater outside the material than inside, and the temperature is sufficient to allow diffusion
to occur, doping atoms diffuse into the material. This process is depicted in Figure 4.11. As Figure
4.11 shows, during the diffusion process dopant tends to move laterally under the window opening as
well as straight into the substrate, since a concentration gradient exists in all directions. This lateral
diffusion is undesirable, since it results in a significantly wider diffused dopant area than the window
opening.
Figure 4.11: Dopant diffusion

This problem can be overcome by using ion implantation to create the dopant region. In ion
implantation, an electric field is used to accelerate dopant atoms directly toward the substrate surface.
The dopant then penetrates into the substrate due to the high kinetic energy of the dopant atoms.
Some lateral doping still occurs, since some dopant atoms will be scattered laterally by collisions
with the atoms in the substrate crystal structure, however the effect is much smaller than lateral
movement in diffusion. This results in a narrower dopant region, as shown in Figure 4.12.
Figure 4.12: Ion implantation
Another benefit of ion implantation is that the dose, the total number of dopant atoms, as well as
the energy of implantation can be varied to produce a much greater range of dopant concentration
profiles. Pre-deposition, or predep, and drive-in refer to a first implantation step, followed by a
dopant redistribution step consisting of a heating of the wafer with no further implantation, as
illustrated in Figure 4.13.
(a) Predep
(b) Short drive in
(c) Medium drive in
(d) Long drive in
Figure 4.13: Dopant redistribution during various lengths of drive in.

In Figure 4.13(a), a predep has been done to introduce a high concentration of dopant just under
the surface of the substrate. The subsequent views show the redistribution at successive times during
drive-in.
4.6
Deposition
Many steps in the fabrication of an integrated circuit require a layer of material to be formed on
the existing surface of the structure. Although the special case of oxide growth on crystalline silicon
material can be accomplished using thermal oxidation, it is usually necessary to deposit more oxide
later in the process, after the silicon surface has been covered. Another example is the deposition of
metal, later patterned using photolithography, for interconnections between devices. A third example
is the requirement in some structures, such as the bipolar transistor, to deposit a layer of silicon on
top of an existing structure. The generic name given to a process that forms a layer of material on the
surface of the chip is deposition. Deposition methods may be broadly divided into two categories:
physical and chemical deposition.
Physical deposition relies on ejection of atoms from a target composed of the material to be deposited. The ejected atoms stick to the surface of the wafer and cause growth of a film of material. In
evaporation, the target material is heated until atoms leave the surface due to thermal emission.
Sputtering uses a stream of neutral atoms directed at the target to cause a physical ejection of atoms,
a process exactly analogous to dry etching. These methods are used to deposit layers of metal for
interconnections.
Chemical deposition methods use a mixture of gases at the wafer surface and high temperatures to
cause a chemical reaction that precipitates the desired material onto the wafer surface. This method is
used for deposited oxides as well as well as for forming an epitaxial layer -a deposited layer of crystalline silicon. Chemical methods have the added advantage of the possibility of varying the
composition of the deposited layer by varying the concentrations of reactants used in the process.
4.7
Scribing and Cleaving
After all the various process steps have been completed, the result is a wafer full of individual
integrated circuits. The last step is scribing and cleaving, used to separate the wafer into the
25
26

individual die. Scribing refers to scratching the wafer surface between the individual chips (along
scribe channels between die) to weaken the physical strength of the wafer along these lines. Cleaving
is the process of breaking the wafer along the scribe lines. Figure 4.14 illustrates the result of this
process.
Figure 4.14: Separation of wafer
Chapter 5 Planar Diode Fabrication

5.1
Substrate Diode
A substrate diode is simply a counter doped region in the wafer. Si3N4 is deposited by CVD, and a
layer of PR is patterned using a mask defining the active area, as shown in Figures 5.1(a)-5.1(d).
(a) Si3N4 deposition
(b) Coating with PR
(c) Exposure
(d) Development
Figure 5.1: Deposition of silicon nitride and coating with PR.

The Si3N4 is etched where not protected by the PR, as shown in Figures 5.2(a)-5.2(c).
(a) Etching
(b) After etch
(c) PR removed
Figure 5.2: Etching of the nitride layer.

A LOCOS oxidation step creates an isolating oxide as shown in Figures Figure 5.3(a)-5.3(d).
(a) Cutaway
(b) Full
(c) Cutaway
(d) Full
Figure 5.3: Thermal oxidation for substrate diode (a-b) during oxidation, (c-d) after nitride
removal.
The counterdoped region, or implant, is now formed, either by diffusion or ion implantation, as
shown in Figures 5.4(a) and 5.4(b). Connections to the two terminals of the diode are made using deposited and patterned metal, as shown in Figures 5.4(c) and 5.4(d). The substrate, or backside
connection is common to all devices.
27
28
Planar Diode Fabrication
(a) Cutaway
(b) Full
(c) Cutaway
(d) Full
Figure 5.4: (a-b) implantation of the counterdoped region and (c-d) metallization
5.2
Well Diode
To form an isolated, two-terminal diode, a counterdoped well is used. As shown in Figures 5.5(a)5.5(c), a LOCOS oxidation step followed by implantation forms a 2-3 m deep counterdoped well in
the substrate. This step requires a mask to dene the well region.
(a) Nitrided well area.
(b) Oxidation.
(c) Well implant.
Figure 5.5: Creation of the well diode isolation oxide and well implant.
An implanted n+ region is formed to allow a low resistance contact to the well, as shown in
Figures
5.6(a)-5.6(b). The active junction is then formed by implantation of a p+ region, as shown in
Figures 5.6(c)-5.6(d). Two masks are required, one each for the n+ and p+ regions.
(a) Protective PR
(b) n+ implant
(c) Protective PR
(d) p+ implant
Figure 5.6: Implantation of well diode counterdoped regions.

Once the n and p regions have been formed and all photoresist stripped, a layer of isolation oxide
is grown on the surface so that metal connections to the implanted regions do not contact the
substrate in the well opening area. The final step is then to deposit metal on the surface of the
structure and use another complete set of photolithography steps (as well as another mask) to form
metal contacts to the two diode connections, the contact implant to the well area and the
counterdoped implant. The final structure is shown in Figure 5.7.
Figure 5.7: Well diode

Note that there are now two junctions in the structure, a second being formed between the well
and substrate. Under normal operation, a p-type substrate is connected to the negative supply to
ensure that the well-substrate junction is reverse biased, and hence the main junction is isolated from
the substrate.
The well diode eliminates the thick substrate from the current path, but has a current density
determined at least in part by the depth of the implant, which is not well enough controlled to create
exactly repeatable characteristics. The structure examined in the next Section overcomes all these
problems.
5.3
Epitaxial Diode
In the epitaxial or epi diode structure, a heavily counterdoped region called the buried layer is
rst formed in a lightly doped wafer, as shown in Figures 5.8(a)-5.8(d). The purpose of this layer will
be to provide a low resistance path for current from the active region to the contact.
(a) Base wafer
(b) Oxidation
(c) Implant
(d) Oxide removed
Figure 5.8: Formation of the n+ buried layer.

CVD is then used to form an epitaxial layer of silicon on the wafer surface, as shown in Figure
5.9(a). p+ implants are then formed as shown in Figures 5.9(b)-5.9(d), with the protective oxide also
deposited by CVD. The p+ regions surround each diode structure and isolation individual diodes.
(a) Epi growth
(b) Masking oxide
(c) Isolation implant
(d) Removal of
oxide
Figure 5.9: Formation of the p+ isolation regions.

n substrate contact and p junction implants are now formed using the same process as for the well
diode, as shown in Figures 5.10(a)-5.10(c).
29
30
Planar Diode Fabrication
(a) n+ implant
(b) p+ implant
(c) Final
Figure 5.10: Formation of the n+ epi connection and p+ regions.

A layer of isolation oxide is now deposited and contact cuts are etched to allow access to the implants, as shown in Figure 5.11(a). After a metal patterning step, the result is the final structure
shown in Figure 5.11(b).
(a) Metallization isolation oxide.
(b) Final Metallization.
Figure 5.11: Isolation oxide and metal connections to the diode terminals.
Current flow in the epi diode is vertical, from the p+ implant through the epi material to the buried
layer, through the buried layer, and back up through the epi layer to the n+ contact, as illustrated in
Figure 5.12. This eliminates the thick substrate from the current path, and forces the current flow to
be vertical, thereby eliminating the dependence on the implant depth. One remaining limitation in the
structure is the connection to the buried layer. A full n+ region down to the buried layer would be
preferable, however this leads to extra processing difficulties, and is normally only used in bipolar
transistor structures.
Figure 5.12: Epi diode current flow
Chapter 6 Doping Profiles and 1D Approximation

6.1
3D, 2D and 1D Doping Profiles
Figure 6.1 illustrates the 3D nature of dopant distribution in an implanted junction. The area
inside the edges of the opening, away from the edges where lateral diffusion takes place, is termed
the internal region. In this region, doping is assumed to be uniform in y and z, and therefore a
function of depth (x) only. The peripheral region is the region at the edges of the window opening,
where lateral diffusion has taken place. Doping in the peripheral region is a function of all three
spatial variables.
Contour plots may be used to provide a more complete view of doping variation. Figures 6.2(a)
and 6.2(b) show contours of constant doping for the junction in 3 and 2 dimensions respectively.
Figure 6.1: Dopant diffusion
(a) 3D
(b) 2D
Figure 6.2: Junction constant doping contours

In the internal region contours are flat, since the doping is uniform in y and z. However, since a
change in x in the internal region involves crossing contours, doping is clearly a function of depth.
The complex, 3D nature of dopant distribution in the peripheral regions is indicated by curving of the
contours. A very long device, for which the effect of periphery on the ends could be ignored, would
be well approximated (per unit length) by the plot of Figure 6.2(b), a slice at some point along its
length. Internal and peripheral regions can still be identified in this 2D structure.
For a two-dimensional slice such as that of Figure 6.2(b), the spatial variation of doping may also
be represented in a surface plot. If the quantity N A N D is represented by the height of a surface in
two dimensions, a clearer picture of the spatial variation is obtained. The large expected variation in
31
32
Doping Profiles and 1D Approximation

doping suggests that a log scale for N A N D is appropriate. Figure 6.3(a) shows such a surface plot.
The large doping of the implant is evident, as is the shape of the internal and peripheral regions. The
uniform substrate doping appears as the flat region surrounding the implant. The boundary of the
implanted (counterdoped) region appears as a dip towards -, since the quantity N A N D is passing
the doping in the internal region, half of the full surface plot can be
through zero. To visualize
constructed, so that the edge of the surface shows the internal doping profile. Figure 6.3(b) shows the
half plot.
will be determined only by
If the effect of the periphery can be ignored, so that device operation
the internal region, the variation of doping with depth in the internal region is sufficient to
characterize the device. This variation is the exposed edge of the surface in Figure 6.3(b), which can
then be represented using a 1D plot, termed a 1D doping profile, as shown in Figure 6.3(c).
(a) 2D surface plot
(b) Half of the 2D plot
(c) 1D plot
Figure 6.3: Doping in 2D surface and 1D plots
6.2
Uniform Doping Approximation
A detailed analysis of the diode structure will at some point require an integration of quantities
over the depth variable x. When the doping is a function of position, as in Figure 6.3(a), this integral
may prove difficult to evaluate. For a profile modeled using the Gaussian function from probability,
no closed form solution is possible. The most common approximation is to assume uniform doping,
i.e. doping which is not a function of position. This is an attempt to simplify the structure to the point
where an analytic result can be obtained, but clearly represents a drastic simplification. There are
several possibilities for the magnitude of the uniform doping which is to approximate a profile such
as that of the implant in Figure 6.3(c). The doping can be anywhere between the background
substrate level and the peak, or at the peak itself. A useful approximation is the value of the implant
peak, leading to the approximation shown in Figure 6.4.
Figure 6.4: Uniform approximation
6.3
Junction Area Scaling
In a structure where carriers are injected into a material with no feature to constrain the area of
current flow, current will spread as it progresses towards the contact, as shown in the current flow
lines of Figure 6.5(b). An accurate analysis of current flow in this situation would require modeling
this spreading. With the loss of some accuracy, the situation can be approximated by ignoring the
current spreading and assuming flow through the original internal diode area, as shown in Figure
6.5(a).
(a) AD
(b) Spreading
Figure 6.5: Current spreading and AD

Under the 1D and AD approximations, current is related to bias through an analysis using the 1D
2
(internal area) approximation, leading to an expression giving current per unit area (A/ cm ) of the
internal region. ID is then found by multiplying the per unit area current by AD. Per unit area diode
current density JD and saturation current density JS are therefore defined as
JD
ID
,
AD
JS
IS
AD
(6.1)
33
34
Doping Profiles and 1D Approximation

which allows (1.7) to be written in the equivalent per unit area form
J D = J S (e qVD
kT
1)
(6.2)
Current density allows structures with different AD to be compared directly. All the situations of
5
Figure 6.6, for example, are equivalent, since they all have a current density of 10 A/cm .
Figure 6.6: Structures with different currents and window areas, but the same current density
Example 6.1:
Which device is carrying more current, one with a current density of 100 A/cm2 and an area 30 m by 10
m, or one with a current density of 75 A/cm2 and a square area 20 m on a side?
Solution:
Using (6.1), the currents are identical in the two devices, as shown below
ID = J D AD = 100( 30 10) 108 = 0.3 mA,
6.4
ID = J D AD = 75(20 20) 108 = 0.3 mA
Design with Diode Area
In integrated applications, the diode (window opening) area AD is normally a quantity that can be
selected by a circuit designer. This leads to two possibilities: If the terminal voltage is specified, the
area can be used to set the current level, or if the current is specified, the area can be used to tune the
diodes voltage drop. Furthermore, safe operating limits are typically in terms of current density so
that the specification can be applied to any situation.
Example 6.2:
What area is required if an integrated diode is to conduct exactly 100 A at a bias of 0.7V? The saturation
current of a 500 m by 500 m device is 3_75 )10
Solution:
_14
A.
The saturation current information is used to determine the saturation current density from (6.2)
JS =
IS
3.75 1014
11
=
A/cm2
2 = 1.5 10
4
AD (500 10 )
At a bias of 0.7V, again using (6.2),
J D = 1.5 1011 (e 0.7 0.02586 1) = 8.55 A/cm2
The required area is therefore
ID 100 106
2
AD =
=
= 1.17 105 cm2 ( 34 m)
JD
8.55
Example 6.3:
Diodes in a power IC technology have JS = 1.5x10-11 A/cm2 and a maximum JD of 106 A/cm2 . Can a diode
from this process conduct 1A of current at 0.9V?
Solution:
The required area from the operating constraint is, using (6.2),
AD =
J S (e
D
qVd kT
1)
1
2
= 5.1105 cm2 ( 71.5m)
0.9 0.02586
1.5 10 (e
1)
11
The corresponding current density is below the limit, so a diode from this process can be used
JD =
ID
1
=
1.5 1011 A/cm2
AD 5.12 105
35
36
Generation, Recombination and Diffusion
Chapter 7 Generation, Recombination and Diffusion

7.1
Generation and Recombination
Two processes characterize electron movement between the conduction and valence bands:
generation is the creation of an electron-hole pair by movement from the valence to the conduction
bands, and recombination is the converse, which removes an electron hole pair. In pure silicon,
generation can only occur with a full band to band transition. The relatively large value of Eg makes
the generation/recombination (GR) rate low at room temperature. Since donor and acceptor energy
levels are very close to a band edge, the presence of ionized donors and/or acceptors does not
meaningfully alter this situation.
However, impurities that introduce energy levels near midgap, called traps, can change the GR
rate dramatically, since two steps of Eg/2 is much more likely than one step of Eg. The process of
trap-aided GR, which dominates full band-to-band GR in silicon at room temperature, is shown in
Figure 7.1(a). All four transition processes are occurring at any one time, and the overall behavior is
determined by the net effect.
(a) Generation.
(b) Recombination.
Figure 7.1: Trap-aided generation and recombination processes.

Quantitatively, the effectiveness of traps in facilitating GR is expressed by a characteristic lifetime
of an electron hole pair o. A small o indicates a very effective trap - both processes are functioning
quickly. Anticipating the application to diode analysis, o is termed the minority lifetime.
With a few approximations, such as trap location at midgap and equal probability of capture and
release, the net recombination rate U (/cm3sec) may be written in the Shockley-Read-Hall model as
U=
n ( x ) p( x ) n i2
0 ( n ( x ) + p( x ) + 2n i )
(7.1)
The physical interpretation of GR as a force acting to restore equilibrium can by understood by

considering the following cases:
np > ni2
U>0
np = ni2
U=0
np < ni2
U<0
With np above the equilibrium value, net recombination

acts to reduce np with time
With np at the equilibrium value, there is no net re
combination
With np below the equilibrium value, net generation acts to
increase np with time
Some simplification of the general expression (7.1) is possible for the situation where a
disturbance increases both n and p by an amount large compared to the equilibrium minority density,
but small compared to the equilibrium majority density, termed low level injection. In this situation,
(7.1) can be expressed in terms of the appropriate net minority carrier density np or pn as
U ptype
(n
np0)
n p
,
0
U ntype
( pn pn 0 ) pn
0
(7.2)
Example 7.1:
A p-type material with NA = 2 x 1016 /cm3 undergoes a disturbance which raises the concentrations of
electrons and holes by 109 /cm3. Compare the prediction of U of the full Shockley-Read-Hall model (7.1) to the
simplified equation. Use a minority lifetime of 1 sec.
Solution:
The equilibrium densities of carriers are po = NA = 2 x 1016 /cm3 and npo = ni2/NA 104 /cm3. The
disturbance raises both values by 109 cm3, so the new values are
p = N A + 10 9 N A = 2 1016 /cm3 ,
n p = n p 0 + 10 9 /cm3
(Note that the effect of the disturbance on the majority carrier is negligible, while the minority value is
totally determined by the disturbance.) Using the full expression (7.1),
U=
10 9 2 1016 (1.45 1010 )
10 (10 + 2 10 + 2 1.45 10
6
16
10
= 1015 /cm3sec
and using the approximate expression for p-type material, (7.2),
n p 10 9
= 6 = 1015 /cm3sec
0 10
7.2 Diffusion
Diffusion is the physical process of particle movement to reduce a concentration derivative (1D)
or gradient (2,3D). As illustrated in the 2D example of Figure 7.2, when a concentration gradient
exists between two regions that can exchange particles, the particles move from the area of greater
density to the area of lower density. In the absence of any other restriction, steady state is
characterized by uniform concentration.
37
38
(a) Initial
(b) t > 0
(c) Steady state
Figure 7.2: Illustration of diffusion in two dimensions.

The fundamental governing equation for diffusion flux in one dimension (/cm2sec) is written in
terms of the diffusion coefficient D (cm2/sec) and the spatial rate of change of concentration as
= D
dc ( x )
dx
(7.3)
The negative sign in (7.3) indicates that the direction of flux is opposite to that of increasing
concentration, as shown in Figure 7.3 for dc/dx > 0. D expresses the ease with which the particles
can move through the medium.
Figure 7.3: Diffusion ux

Electron and hole diffusion flux will require custom versions of (7.3), incorporating individual D
values Dn and Dp, and reconciling the definitions for conventional current flow. As shown in Figure
7.4(b), conventional current flows in the direction of hole flux, so the negative sign in (7.3) applies.
However, conventional current flows in the opposite direction to electron flow, so the sign in (7.3) is
reversed.
(a) Hole diffusion
(b) Electron diffusion
Figure 7.4: Current direction for hole and electron flow.

This leads to the equations shown in (7.4) for Jn,diff and Jp,diff
J n,diff = qDn
dn ( x )
,
dx
J p,diff = qDp
dp( x )
dx
(7.4)
For semiconducting material, D can be expressed in terms of the mobility (cm2/Vsec) as
Dn =
kT
n ,
q
Dp =
kT
p
q
(7.5)
Example 7.2:
What are the diffusion coefficients for silicon at 300K?
Solution:
Inserting the required values into (7.5) and (7.5),
Dn = 0.02586 1350 = 34.9 cm3 /sec,
7.3
Dp = 0.02586 470 = 12.2 cm3 /sec
Diffusion Length
If a spatial gradient of electron or hole density exists in a semiconducting material, while the
carriers are moving to reduce the concentration gradient they are also influenced by the process of
generation and recombination.
39
40
Figure 7.5: Diffusion and GR.

The processes of GR and diffusion may occur simultaneously in a region where the np product is
not ni2 and a concentration gradient is driving diffusion flux. In the example shown in Figure 7.5,
electron flow is to the left, with recombination acting to reduce n where the concentration is above
equilibrium, and vice versa for generation. These two factors can be combined into a single
parameter, the diffusion length L (cm), which expresses the average distance over which a carrier will
propagate before being likely to recombine, or the average distance over which generation is likely to
occur
Ln Dn 0 ,
Example 7.3:
L p Dp 0
(7.6)
What are the minority diffusion lengths for silicon at 300K if the minority lifetime is 0.5 sec?
Solution:
Using the results for Dn and Dp and equations (7.6),
Ln 34.9 0.5 106 = 4.18 103 cm = 41.8 m

L p 12.4 0.5 106 = 2.49 103 cm = 24.9 m
Chapter 8 Diode Operation

8.1
Equilibrium
Figure 8.1(a) depicts unconnected p+ implant and n substrate materials. The materials are brought
into contact and allowed to exchange carriers at t = 0, as shown in Figure 8.1(b).
(a) Before connection
(b) After connection
Figure 8.1: p+n junction materials before and after connection

At t = 0+, large p and n gradients exist at the metallurgical junction. Electrons will therefore
diffuse into the p type material, and holes into the n type, causing majority concentrations around the
metallurgical junction to decrease and minority concentrations to increase. The charge imbalance will
create an opposing electric field, as shown in Figure 8.2(b). Equilibrium will be reached when these
two forces balance, as shown in Figure 8.2(c).
(a) t = 0
(b) t > 0
(c) t .
Figure 8.2: Charge redistribution and spatial concentrations in the pn-junction.

Carrier movement to achieve equilibrium is localized around the metallurgical junction. At
equilibrium, the diode can therefore roughly be divided into three regions: neutral regions in the n
and p type materials, where negligible charge movement has occurred, and a depletion region
characterized by charge imbalance and non-zero electric field, as shown in Figure 8.3. The name
depletion region arises from the assumption that the exchange of carriers necessary to achieve
equilibrium will leave the densities of free carriers in the region over which they are exchanged very
low.
41
42
Diode Operation
Figure 8.3: Diode regions
8.2
Forward Bias
Forward bias diode current can be broken down into two physical components: hole flow from p
to n materials, and electron flow from n to p, as shown in Figure 8.4. Forward bias is therefore
characterised by minority carrier injection.
Figure 8.4: Components

The effect of minority carrier injection on the electron and hole spatial distributions for an
implanted p+-n device is shown in Figure 8.5. Low-level injection is assumed, where the increase in
carrier density due to current injection dominates the minority density, but is negligible compared to
the majority density. The substrate is long compared to the hole minority diffusion length Lp, leading
to an exponential pn(x). The implant neutral region is short compared to the electron minority
diffusion length Ln, leading to a linear np(x). Steady state is achieved when the effect of bias to
increase carrier densities is exactly balanced by the tendency of recombination to reduce the
concentrations.
Figure 8.5: Hole and electron concentration spatial variation for forward bias.
The most important boundary condition required in the derivation of a basic model for current
flow is the value of the minority density at the depletion region edge, given for each carrier as
n p ( x ) p depl edge = n p 0e qVD
kT
pn ( x ) n depl edge = pn 0e qVD
(8.1)
kT
Carrier flow for low level injection is by diffusion, thus the derivative of carrier concentration
yields the current density due to minority carriers. From an equation describing the carrier density
with position, and the simplifying assumption GR in the depletion region is not significant, the total
current can be obtained by adding the minority diffusion current components at the two depletion
region edges. Following this strategy, with the details not supplied here, yields
Jn =
qDn n p 0 qVD
(e
wp
kT
1),
Jp =
qDp pn 0 qVD
(e
Lp
kT
1)
(8.2)
where wp is the width of the neutral p-type region. The sum of these two components is then the
total current density in the device, which is the terminal current density JD. Summing these
components gives
" qD n
qDp pn 0 % qVD
J D = J n + J p = $$ n p 0 +
'(e
L p '&
# wp
kT
1)
(8.3)
Comparing the result to the simple ideal diode equation leads to the identification of the saturation
current density term, as shown in (8.4). For the case of an n+-p junction, the width of the n+ neutral
region replaces Lp, and Ln replaces wp, also as shown in (8.4).
JS
p +n
qDn n p 0 qDp pn 0
+
,
wp
Lp
JS n + p =
qDn n p 0 qDp pn 0
+
Ln
wn
(8.4)
Example 8.1:
What is JS for the junction whose doping profile is shown in Figure 8.6(a)? Assume o = sec, use a
uniform doping approximation, and assume wp is equal to the junction depth.
(a) Doping profile for example
(b) Uniform approximation
43
44
Diode Operation
Solution:
The uniform approximation is shown in Figure 8.6(b). npo and pno are then given by
10 2
np0
(1.45 10 )
=
18
10
10 2
= 2.110 /cm ,
pn 0
(1.45 10 )
=
15
8 10
= 2.6 10 4 /cm3
Using wp 1m and values calculated earlier,
JS =
8.3
1.6 1019 34.9 2.110 2 1.6 1019 12.4 2.6 10 2

+
= 3.27 1011 A/cm2
104
2.49 103
Reverse Bias
Figure 8.6 shows the components of current flow for reverse bias. Electrons are injected into the p
material and holes into the n, so reverse bias is characterized by majority carrier injection.
Figure 8.6: Components
Figure 8.7 shows n(x) and p(x) for reverse bias. Majority injection lowers the concentration of minority carriers, hence generation is occurring, which provides the balancing force in steady state. The
changed sign of the density derivatives supports flow in the reverse direction. The boundary
conditions in (8.1) still apply in reverse bias, and since VD is negative, are consistent with the lowered
values at the depletion region edges. The minority density dependence on x is linear in the short
implant material, and exponential in the long substrate material.
Since equations (8.1) still apply, the same JD expression applies. The typical reverse bias current
limit of -IS may be understood from Figure 8.7. For VD < -3kT/q, the boundary conditions (8.1)
predict that the concentrations will become independent of the value of VD. Their derivatives are
therefore independent of VD, making the current independent of VD.
Figure 8.7: Hole and electron concentration spatial variation for reverse bias. The diode structure is indicated
by the dot-dashed line.
45
46
Depletion Region GR and Parasitic Resistance
Chapter 9 Depletion Region GR and Parasitic Resistance

9.1
Depletion Region GR
GR in the depletion region, although it was ignored in the initial development of the ideal diode
equation, can be an important factor, since carrier densities will not be equal to their equilibrium
values. The situation can be viewed simplistically as shown in Figure 9.1(a). In forward bias,
recombination will require another current component in the same direction as the injection current.
In reverse bias, generation will create another current component, again in the same direction as the
injected current.
(a) Forward bias
(b) Reverse bias
Figure 9.1: Extra current component due to depletion region GR in forward and reverse bias.
A complete analysis of this situation is out of the scope of the course, and a number of different
mechanisms are possible depending on the junctions material parameters, but the most important
result is that the presence of significant depletion region GR can change the exponent in the ideal
diode equation. The modified ideal diode equation incorporates a slope factor n into the exponent, as
shown in (9.1)
ID = IS (e qVD
nkT
1)
(9.1)
The slope factor varies between 1, for junctions relatively unaffected by depletion region GR, to
2, for junctions dominated by the effect.
Example 9.1:
-7
What is ID for n = 1 vs 1.2 at VD = 0.7 if JS = 10 A/cm and AD = (50 m)2 ?

Solution:
The saturation current for this area is
2
IS = 107 (50 104 ) = 2.5 1012 A
The two currents are therefore different by almost 2 orders of magnitude
ID = 2.5 1012 e 0.7 (1 0.02586) 1 = 1.43 A,
ID = 2.5 1012 e 0.7 (1.2 0.02586) 1 = 0.016 A
Figure 9.2 shows the prediction of the ideal diode equation (9.1) for a fixed value of IS = 10-13 A
and varying values of the slope factor n, with ID plotted on a log scale. Note that the VD = 0 intercept
of the linear portion is constant, since the same value of IS is used for all characteristics. Relatively
small differences in n cause order of magnitude differences in ID at higher bias, since n appears in the
exponent. The sensitivity of current to n makes analytic prediction of the value of limited use, its
value is normally chosen for best fit to a measured characteristic.
VD(V)
Figure 9.2: ID(n)
9.2
Parasitic Resistance
For the purposes of identifying parasitic resistance, a practical diode structure can be viewed as a
junction described by the ideal diode equation (9.1) inside implant and substrate neutral regions
between the junction and contacts, characterized by parasitic resistances Rimpl and RS, respectively, as
shown in Figure 9.3. The active diode region can only be accessed through the parasitic resistances,
so the applied potential is VDx in Figure 9.3, while VD is the potential used in the ideal diode equation
(9.1).
47
48
Figure 9.3: Diode parasitic resistance

To calculate the resistances of the neutral regions, R is found from the basic definition
R=
l
A
(9.2)
where is the resistivity (-cm) of the material, l is the length along current flow and A is the
cross sectional area. For semiconducting material, the resistivity is found from
1
(qn 0n + qp0 p )
(qn 0n ) n
n type
(qp0 p ) p
p type
(9.3)
where the approximations follow from the relative magnitudes of n and p for n-type and p-type
material. For both Rimpl and RS, the area in (9.2) is AD. The length in each case is the length of the
neutral region.
Since Rimpl will have a much smaller l and much lower (due to higher doping), the resistance of
the substrate will dominate. However, it should be noted that application of (9.2) to the substrate with
area AD will overestimate the resistance, since current spreading will increase the effective AD.
Example 9.2:
Find Rimpl and RS for the p+-n diode whose doping profile is shown below. The substrate is 0.8mm thick.
Approximate the implant neutral width by the junction depth. AD = 250 m2 .
Solution:
Using the (uniform) dopings from the profile, (9.3) and (9.2),
1
p = (q 5 1018 480) = 0.0026 cm, n = (q 1016 1350) = 0.46 cm

Rimpl =
0.0026 104
0.46 0.8 101
=
0.13
,
R
=
= 14.8 k
S
250 108
250 108
Since
the internal diode nodes are not accessible, the general case of nonzero parasitic resistance
may be represented as shown in 9.4, with the two neutral region resistances combined. Evidently
VDx = VD + ID RS VD = VDx ID RS
(9.4)
and thus the ideal diode equation can be modified to relate ID to VDx as
ID = IS e q (VDx I D R S ) nkT 1
(9.5)
When the potential drop across RS is significant compared to VDx, VD will be less than VDx, and
hence the current will be lower than that which would be expected if RS = 0, leading to current
rolloff. This is illustrated in
Figure 9.5, which compares ID vs VDx for a device with IS = 10-11 A, n =
1.2 and four values of RS.
Figure 9.4: VDx
Figure 9.5: Comparison of IS vs. VDx characteristics with varying RS.
49
50
Example 9.3:
Calculate the series resistance associated with the connection from the n+ diffusion to the n+ buried layer
in the epi diode structure whose cross section is shown in Figure 9.6(a). Figure 9.6(b) is a top view of the
masks used to generate the structure. The epi doping is ND = 5x1016 cm.
(a) Cross section
(b) Layout
Figure 9.6: Cross section and layout of an epi diode structure for R calculation example.
Solution:
Using the epi doping, flow length of 3-1 = 2 m from the cross section and area 1 m x 10 m from the
layout, n and RS can be calculated as
1
n = (q 5 1016 1350) = 0.093 cm, RS = 0.093
2 104
= 186
1104 10 104
Chapter 10 Diode Model Parameter Extraction

10.1 Model Parameter Extraction
Parameter extraction refers to the determination of best-fit coefficients for an analytic model
from measured data. There are a number of reasons why model coefficients may be determined by
extraction from measured data rather than directly from analytic expressions. First, not all
coefficients will have analytic equations allowing calculation from physical parameters (e.g. the
diode n). Second, when analytic equations exist, they will inevitably involve approximations that
may result in predictions with unacceptable accuracy (e.g. JS). Third, analytic expression based on
physical parameters are only as accurate as the physical parameters, which may be difficult to
measure and will inevitably vary slightly between nominally similar devices.
As a general rule, parameters that can be isolated via an appropriate measurement are extracted
first. The remaining parameters are then extracted using the values of the parameters just found.
Figure 10.1 shows a typical automated industrial parameter extraction environment. A host PC or
workstation controls one or more pieces of measurement equipment, which are connected to the
Device Under Test (DUT) through a text fixture, a structure that allows easy connection to
measurement channels. The PC or workstation configures the test equipment for a measurement,
signals the system to perform the measurement, then retrieves the data back over the data/control bus,
which is normally a GPIB, or General Purpose Interface Bus connection. Once the data has been
loaded by the computer, a series of programs is run to extract the necessary model parameters.
Figure 10.1: Schematic view of an automated extraction setup
10.2 Extraction of Ideal Diode Model Parameters

The ideal diode equation model 9.1 has three extractable parameters: IS, n and RS. IS may be
obtained directly from a reverse bias ID -VD measurement with VD < -3kT/q, since neither n nor RS will
be important once the exponential is negligible. In forward bias, ln(ID) vs VD will be linear when VD >
3kT/q but low enough so that the effect of RS is negligible. A straight line fit to this portion of the
characteristic therefore yields a second estimate of IS from the intercept and n from the slope. Once n
and IS are known, an ID -VD point where RS is important can be used with the values of IS and n just
found to give RS by solving the ideal diode equation rewritten for RS .
Example 10.1:
Extract ideal diode model parameters for the measured data shown below.
51
52
Diode Model Parameter Extraction
Solution:
The value of IS is first found from the reverse characteristic for VD < -3kT/q as shown in plot (a) below,
yielding IS = 3x10-11 A. The forward characteristic is then used to extract IS and the slope factor n by choosing
two measured points from the linear portion, in this case with VD = 0.22, 0.44 V corresponding currents ID =
2.22x10-8 A and ID = 1.64x10-8 A, as shown in plot (b) below
(a) Rev extraction of IS
(b) Fwd extraction of IS and n
The line to be fit to the linear forward characteristic is ln(ID) = mVD + b, so the coefficients are determined
as
5
8
ln( ID ) ln(1.64 10 ) ln(2.22 10 )
=
= 30.0
VD
0.4 0.22
b = ln(1.64 105 ) 30.0 0.44 = 24.2
m=
IS and n are then related to the slope and intercept by
IS = exp(b) = 3.03 1011 A,
n=
q
1.602 1019
=
= 1.29
mkT 30.0 1.3811023 300
RS is then determined from a bias point where rolloff has occurred, in this case chosen as ID = 1.62x10-2 A and
VD = 1.0 V
Rs =
$
$ 1.62 10 2 ''
1
1.0
1.29
0.0259
ln
&
) = 20.3
&1+
11 )
1.62 10 2 %
% 3.0310 ((
10.3 Linear Regression

In a practical environment, measured data will usually include noise. A straight line fit based on
two points in this situation will reflect the noise on those two points, which may give inaccurate
results. The solution is to use a least squares fit, or linear regression, in which the estimated
and b , are found by minimizing the sum of the squares of the differences
coefficients of the line, m
between the line and the data points, termed the residuals , and illustrated in Figure 10.2. This
procedure dampens the effect of individual point noise values.
Figure 10.2: Least squares residuals

and b are given in terms of the data points (x1, x2, xn) and (y1, y2, yn) by
The estimates m
where x and
n
$ n '$ n '
n x i y i & x i )& y i )
% i=1 (% i=1 (
= i=1
m
n
$ n '2
2
n x i & x i )
% i=1 (
i=1
(10.2)
b = y m x
(10.3)
are the mean values.
Example 10.2:
Determine the coefficients of a least squares fit to the data in Table 10.1, and plot the original data and the
linear fit on the same axes.
x
0.00
0.09
0.18
0.27
2.77
3.02
3.36
3.37
0.36
0.45
0.55
0.64
3.39
4.10
4.27
4.26
0.73
0.82
0.91
1.00
4.41
4.85
4.54
5.28
Table 10.1: Data for least squares example
53
54
Diode Model Parameter Extraction
Solution:
Applying (10.2) directly
12
12
12
y i = 47.63,
x i2 = 4.18,
x y
i=1
i=1
i=1
i=1
m =
12
x i = 6.00,
12 26.53 (6.00)( 47.63)

12 4.18 (6.00)
= 26.53
47.63
6.00
= 2.30, y =
2.30
= 2.82
12
12
The original data is plotted with the least squares straight-line fit below.
One drawback to the least squares method is that it considers all points to be equally important.
This can be a problem when the data contains an outlier, or spurious data point. An outlier is a value
that is quite different from the values around it in a data set, and is usually the result of an
intermittent problem with measurement equipment or a sudden burst of noise on a measurement. The
least squares algorithm will allow the large difference between the outlier and surrounding points to
influence the line coefficients, since it will take the large difference into account in computation of
the total of all residuals. Figure 10.3 illustrates the effect of an outlier on the extraction performed in
the example. The outlier at x 0.22 changes the extracted slope from 2.35 to 2.14 and the intercept
from 2.79 to 2.97. These differences are an artifact caused by the single outlier point.
Figure 10.3: Least squares fit of the example data, but with outlier at x 0.18
Although it might seem that an outlier is easy to detect by virtue of being a very different value
than its neighbors, in practice a robust method for outlier detection is often difficult to specify, since
the outlier can occur at any particular point, its magnitude is unknown, there may be more than one
outlier, etc.. Some more robust methods exist for extraction of linear regression coefficients, but in
practice results are either quickly checked visually, or the eventual extracted parameter value is
checked against known limits.
A large error in extraction of the saturation current from a reverse bias diode characteristic can
occur due to an outlier point. This current will usually be small in the first place, so it is also the most
likely case for noise to influence a measurement. Figure 10.4(a) shows extraction of IS by fitting a
line to measured reverse bias current data. Although the data is noisy, no one point is largely
different than any others.
(a) Original IS data with extraction
(b) Same data with an outlier point
Figure 10.4: Effect of outlier on extracted parameters
With noise on one particular data point to raise the value to the nA range, still a small current, the
value extracted for the saturation current changes from 3.28x10-11 A to 1.06x10-10 A , as shown in
Figure 10.4(b). The outlier has pulled the linear characteristic towards larger values, in other words
the least squares algorithm has had to increase the intercept to try and balance the large error
associated with the outlier.
55
56
pn-Junction Electrostatics
Chapter 11 pn-Junction Electrostatics

11.1 Poissons Equation
Poissons equation is the fundamental relationship between potential (V), electric field E
(V/cm), excess per unit area charge density and permittivity , given in 1D as
d 2 ( x ) dE ( x ) ( x )
=
=
dx 2
dx
(11.1)
Since (x) is an excess charge density, a non-zero value is created by charge separation, the local
imbalance of electrons and holes. Although electrons and holes may both be present in an area of
if their numbers balance, the overall excess charge density is zero.
semiconductor,
Figure 11.1 shows solutions to Poissons equation useful situations. When (x) = 0, E(x) is
constant and (x) is linear. When (x) is constant, E(x) is linear and (x) is quadratic. The integration
constants involved in solving (11.1) will be determined by the boundary conditions of the particular
problem.
(a) = 0
(b) 0
Figure 11.1: Solutions of Poissons equation
11.2 The Depletion Approximation

(x) in a semiconductor is determined by four charge components: electrons and ionized acceptors
with charge -q, and holes and ionized donor atoms with charge +q, giving
( x ) = q( p( x ) n ( x ) + N D N A )
(11.2)
In a pn-junction, NA and ND have already been approximated as uniform. Solving for the true n(x)
and p(x) in the pn-junction at equilibrium is difficult, even for constant doping, and requires
numerical simulation for any practical structure. Figure 11.2(a) shows the result of such a simulation,
with the dotted lines showing the approximate positions of the depletion region edges.
While the log scale in Figure 11.2(a) allows the complete characteristic to be visualized, it gives a
misleading idea of the relative magnitudes of the quantities. Plotting on a linear scale, as shown in
Figure 11.2(b), illustrates that the values of n(x) and p(x) actually fall to negligible values with a
short distance of each depletion region edge. This is the basis for the depletion approximation, in
which n(x) and p(x) are neglected over the entire depletion region.
11.3 Qualitative Junction Electrostatics

The prediction of the depletion approximation may be compared to the more accurate situation
shown in Figures 11.2(a)-11.2(b) by determining (x) in each case and applying (11.1). In both cases,
NA and ND are constant values in their respective materials. For the accurate data, (x) is found from
(11.2) using the actual values of each variable. For the depletion approximation, n(x) and p(x) are the
doping densities outside the depletion region and zero inside, resulting in the plots of Figure 11.3(a).
Integrating once and setting E(x) to zero outside the depletion region yields 11.3(b). A further
integration, negation and choice of (x) = 0 at the left hand edge gives 11.3(c).
57
58
(a)
(b)
(c)
Figure 11.3: Poissons equation solution for accurate and depletion approximation (x)
11.4 Quantitative Junction Electrostatic Results

Using the depletion approximation (x) shown in Figure 11.3(a), the total width of the depletion
region W may be shown to be
W =
2Si # 1
1 &
+
%
(Vbi ,
q $ NA ND '
Vbi =
kT # N A N D &
ln%
(
q $ n i2 '
(11.3)
where Si is the permittivity of silicon and Vbi is the built-in potential. Figure 11.4 shows a contour
plot of W in the NA ND plane, with dashed lines connecting points where NA > 10ND and vice versa.
Outside these lines, the depletion width is essentially determined by the lighter doping.
Figure 11.4: Contours of constant W
The extent of W into the n-type and p-type material are xn and xp respectively, given by
" NA %
xn = W $
',
# NA + ND &
" ND %
xp = W $
'
# NA + ND &
(11.4)
Note that (11.4) and (11.4) predict that when doping is asymmetrical, W extends farther into the
more lightly doped material.
Once the depletion

width and extents into each material are known, the maximum electric field in
the junction can be calculated. Since E(x) is the integral of (x) and is constrained to be zero at all
points outside the depletion region, the peak electric field is therefore the area of either of the
rectangular (x) regions in Figure 11.3(a) with the permittivity scaling factor, i.e.
E deplmax =
qN A x p
qN x
2q $ N A N D '
= D n =
&
)Vbi
Si
Si
Si % N A + N D (
(11.5)
Note that the sign of E(x) only indicates the direction relative to positive x.
Example 11.1:
Compute the depletion region width and the extents of the depletion region into each type of material for
the device used in Figures 11.2(a), etc., i.e. a pn-junction with NA = 4x1016 /cm3 and ND = 1016 /cm3. The
temperature is 300K.
Solution:
From (11.3), with kT/q = 0.0286 V at T = 300 K,
$
'
4 1016 1016 )
&
Vbi = 0.02586ln
= 0.73 V
& (1.45 1010 ) 2 )
%
(
The total depletion width is then given using (11.3) as
# 1
1 &
W = 1.29 10 7 %
+ 16 (0.73 = 3.43 105 cm
16
$ 4 10
10 '
and the individual extents are, using (11.4) and (11.4),
59
60
% 4 1016 (
x n = 3.43 105 '
= 2.74 105 cm = 0.274 m
16
16 *
& 4 10 10 )
%
(
1016
x p = 3.43 105 '
= 0.69 105 cm = 0.069 m
16
16 *
& 4 10 10 )
The absolute x values of the depletion edges, since the metallurgical junction is at 2.0 m, are 2.0 0.069
1.93 m and 2.0 + 0.274 2.27 m. This is how the depletion region edge locations in Figure 11.2(a), for
were determined.
example,
Chapter 12 Diode Reverse Breakdown

12.1 Reverse Bias Junction Electrostatics
Another behavior exhibited by most diodes and not predicted by the ideal diode equation is an
abrupt increase in reverse bias current, as shown in 12.1, termed reverse breakdown. An
understanding of the physical origin of this behavior requires first considering the effect of reverse
bias on the junction electrostatics.
Figure 12.1: Reverse breakdown

A reverse bias raises the potential of the n-type material with respect to the p-type, thereby
creating an electric field component that adds to the field present due to the initial charge
redistribution at equilibrium. From Poissons equation, this extra electric field must be supported by
an increase in excess charge. Since the magnitude of doping cannot change, the width of the depletion region is the only quantity in (x). Hence, the increased (x) required to support the increased
E(x) is created by a widening of W into both regions, preserving the original proportions of xn and xp,
as shown in Figure 12.2(a). The increase in electric field is shown in Figure 12.2(b), and the increase
in potential from Poissons equation, which corresponds to the applied reverse bias, is shown in
Figure 12.2(c). Note that the results of Poissons equation and the physical arguments about how
quantities must vary are all in complete agreement.
(a) (x)
(b) E(x)
Figure 12.2: Effect of reverse bias on electrostatic quantities
(c) (x)
61
62
Diode Reverse Breakdown

Quantitatively, since the applied potential adds to the existing potential, the previous W and
Edeplmax(x) expressions can be modified for the reverse bias case simply by adding VD to the existing
Vbi term. This works for small forward biases case as well, where the applied potential subtracts from
Vbi. With the forward/reverse bias sign convention for VD, W(VD) and Edeplmax(VD) can be written
W=
2 Si ! 1
1 $
+
#
& (Vbi VD ),
q " NA ND %
E depl max =
2q ! N A N D $
#
& (Vbi VD )
Si " N A + N D %
(12.1)
12.2 Avalanche Breakdown

Another process that can cause the creation of electron-hole pairs is impact ionization, the
promotion of a valence band electron to the conduction band through energy transfer from collision
with another electron. Figures 12.3(a)-12.3(b) illustrate this process on both energy band and
bonding model diagrams. A net electron-hole pair is only created when enough energy is transferred
to cause promotion of the valence band electron to the conduction band, and the original electron
retains enough energy to remain in the conduction band.
Figure 12.3(c) shows how the impact ionization process leads to avalanche multiplication, and
hence to a large current increase. Electrons in the pn-junction depletion region gain kinetic energy
through acceleration by the electric field. As reverse bias increases, the average energy of electrons
increases, and at some bias impact ionization events will begin to occur. Once this process starts,
electron hole pairs that are separated and accelerated by the field may also cause impaction ionization
events, and hence n and p, and therefore current, can rise very rapidly. This process of avalanche
multiplication leads to a very abrupt increase in current, and is the physical mechanism behind the
plot of Figure 12.1.
(a)
(b)
(c)
Figure 12.3: (a) Before and (b) after impact ionization. (c) Avalanche multiplication
Impact ionization is characterised by a set of ionization coefficients that specify the probability of
a carrier created by impact ionization itself then creating a further carrier pair by the same process,
with the first probability applied to the original concentration. The product of a probability and the
population available for impact ionization is therefore the expected value of the concentration for the
next event. The density of electrons niik created by impact ionization after k events is therefore given
in terms of the probabilities p1, p2, ... by
nii1 = p1n,
nii2 = p2 p1n,
nii3 = p3 p2 p1n
(12.2)
and thus the total density of electrons taking impact ionization into account is the sum of the
original density and all carriers generated by impact ionization
n ii = n + n iik = n + p1n + p2 p1n + p3 p2 p1n + = n (1+ p1 + p2 p1 + p3 p2 p1 + )
(12.3)
k=1
Although the values of the probabilities may be estimated from theoretical considerations or extracted from measurements, it is common to assume that they are all equal, with their values denoted
by a single ionization probability pii. With this assumption,
% 1 (
n ii = n + n iik = n (1+ pii + pii2 + pii3 + ) = n'
*
&1 pii )
k=1
(12.4)
A multiplication factor Mii is then defined as the total proportional increase in density due to
impact ionization
!! =
!!!
!
= !!!
!!
(12.5)
Figure 12.4(a) shows a plot of the relationship in (12.5). With pii = 0, Mii = 1, and no increase in n
occurs. As pii becomes close to 1, Mii >> 1, leading to large nii.
The values of the impact ionization coefficients are very difficult to predict theoretically. pii is
often modelled as the ratio of the maximum depletion region electric field Edeplmax to a critical field
Edeplmax, raised to a power between 3 and 6
# E deplmax & 36
pii %
(
$ E crit '
(12.6)
The avalanche breakdown mechanism is therefore modelled through the dependence of electric
field on terminal potential. If the breakdown voltage VBR due to avalanche multiplication is defined to
to an impact ionization probability of 1, i.e. Mii , then (12.1) can
be the potential corresponding
be used to solve for this potential explicitly by setting Edeplmax = Ecrit and VD = VBR rewriting to give
VBR aval = Vbi
2 "
SiE crit
1
1 %
+
$
'
2q # N A N D &
(12.7)
Figure 12.4(b) is a contour plot of avalanche breakdown voltage evaluated using (12.7) with a
critical eld of 3x105 V/cm. Depending on the doping levels, a very wide range of breakdown
voltages is possible - from a few volts for a junction doped on both sides to hundreds of volts for a
junction lightly doped on both sides. The dashed lines indicate the points where the doping is an
63
64
Diode Reverse Breakdown

order of magnitude larger on one side than the other. Points outside these lines are representative of
an implanted junction where the implant doping is at least order of magnitude larger than the
substrate doping. In this case the breakdown voltage is essentially determined by the more lightly
doped substrate.
(a) Mii
(b) VBR
Figure 12.4: Avalanche breakdown multiplication factor and breakdown voltage
Example 12.1:
A diode has a saturation current of IS = 3x10-10 A, and an ionization probability given by (12.6) with a
power of 3. What proportion of the critical electric field must the peak depletion region electric field be to give
a reverse bias current flow of 10 nA?
Solution:
The first step is to find the multiplication factor corresponding to the current increase
M ii =
10 109
= 33.3
3 1010
From (12.5), this implies
!! = 1 ! = 0.97
!!
and therefore from (12.6)
!"#$%&' = 0.97
! !
!"#$ = 0.99!"#$
Thus the maximum depletion region electric field must be 99% of the critical field to obtain a current flow
of 10 nA.
Chapter 13 Diode Small Signal Modelling

13.1 Small Signal Conductance
The small signal conductance gD of a diode is the rate of change of ID with respect to VD. Normally
gD is of interest when VD > 3kT/q, so with the 1 ignored in the ideal diode equation,
gD
dID
q
=
IS e qVD
dVD nkT
nkT
q
ID
nkT
(13.1)
gD is a function of operating point since it is a linearization of the operating point dependent ID-VD
characteristic.
Example 13.1:
What VD is required for gD = 10 mS if IS = 5x10-11 A and n = 1.3? Ignore parasitic resistance.
Solution:
3
ID = 10 1.3 0.02586 = 3.36 10
& 3.36 104 )

A VD = 1.3 0.02586ln(1+
+ = 0.53 V
5 1011 *
'
13.2 Depletion Capacitance

Capacitance is the rate of change of charge with voltage, as shown in (13.2).
C=
dq
dv
(13.2)
This suggests that capacitance could be measured for a device under test, or DUT, as shown in
Figure 13.1.
Figure 13.1: Capacitance of DUT

In practice, however, it is difficult to measure a q accurately. With current written as dq/dt,
(13.2) can be rewritten as
65
66
Diode Small Signal Modelling
i( t ) = C
dv ( t )
dt
(13.3)
leading to the more common method of determining C from the phase shift between i(t) and v(t).
However, Figure 13.1 is a useful visualization of the insight that capacitance exists between two
terminals of a device when achange in potential across the terminals requires charge to be supplied
(sourced) or removed (sunk).
Considering the diodes depletion region charge, the W corresponding to a VD requires charge to
be supplied or sunk, since will change. This dq associated with a dv defines the depletion
capacitance of the device. Figure 13.2(a) illustrates this argument -an increase in VD lowers W and
requires charge to be supplied to compensate the edges of the depletion region, which can be
considered a small signal differential charge at a separation W. Since W is a function of VD, the
differential charge position is a function of bias, as shown in Figure 13.2(b).
(a) Differential charge
(b) Bias dependence
Figure 13.2: Diode depletion capacitance

2
The per unit area depletion capacitance C dep (F/cm ) is determined from (13.2) by taking the
2
derivative of Q dep (C/cm ), with respect to VD, which can be written using the chain rule as
dQ
dQ dep dW
dep
C dep
=
dVD
dW dVD
(13.4)
C dep in (13.4) is the charge associated with the positive terminal -qNAxp. The derivatives are
# ND &
dQ dep
dx
d
=
qN A x p ) = qN A p = qN A %
(,
(
dW
dW
dW
$ NA + ND '
dW
1 2Si N A + N D
=
dVD
2W q N A N D
(13.5)
Note that d Q dep /dW is negative, meaning Q dep becomes more negative (an increase in negative
charge) as W increases, which is intuitively correct. C is therefore
dep
#
N D & # 1 2Si N A + N D & Si
C dep (VD ) = %qN A
( %
(=
N A + N
q NA ND ' W
$
D ' $ 2W
(13.6)
with the absolute capacitance Cdep = C dep AD (F). The result in (13.6) has the same form as a parallel plate capacitor, with a separation W and dielectric permittivity Si, because the differential charge
regions are separated by silicon dielectric and a distance W.
For modelling purposes it is more convenient to bring the voltage dependence of (13.6) out
explicitly. This accomplished by first manipulating W(VD) by
W (VD ) =
2Si N A + N D
V
2 N + N
(Vbi VD ) bi = Si A D Vbi
q NA ND
Vbi
q NA ND
(Vbi VD ) = W
Vbi
(0)
VD
Vbi
(13.7)
Substituting this form of W(VD) into (13.6) gives
C dep (0)
W (0)
C dep (VD ) = Si
=
,
1 VD Vbi
1 VD Vbi
C dep (0) Si
W (0)
(13.8)
In general, the term in the denominator of (13.8) can take on exponents between 1/2 and 1/3 for
common doping profiles. For this reason, the exponent is considered a fitting factor for the model,
termed the grading coefficient, and given the symbol z. The final, general expression for the
depletion capacitance is therefore
C dep (VD ) =
C dep (0)
(1 VD
Vbi )
(13.9)
Evaluating (13.9) over a range of biases for a diode with NA = 1016 cm-3 and ND = 1017 cm-3 and an
area of 50 m by 50 m gives the depletion capacitance characteristic shown in Figure 13.3(a),
been plotted in pF. As VD increases, W decreases, so the capacitance rises.
where capacitance has
Near the potential Vbi, the depletion width becomes small and the capacitance becomes very large.
Although (13.9) predicts that C dep for VD Vbi, in practice this situation is characterised by
high level injection, and the depletion region no longer exists in the simple form taken so far. The
basic equation for W is therefore no longer valid. Figure 13.3(b) shows the effect of different grading
coefficients on the C dep (VD) characteristic for a device with C dep (0) = 10-8 F/cm2, Vbi = 0.8 V and an
area of 75 m2.
(a) Basic characteristic
(b) Effect of z variation
Figure 13.3: Depletion capacitance characteristic
67
68
Diode Small Signal Modelling
Example 13.2:
A diode has ND = 4x1018 cm-3 in a well of doping NA = 1016 cm-3. The 1D area is a square 100m on a side.
What bias range ensures that the depletion capacitance does not exceed 1.5 pF?
Solution:
For this device,
$
'
4 1018 1016 )
&
Vbi = 0.02586ln
= 0.85 V,
& (1.45 1010 ) 2 )
%
(
AD = (100 104 ) = 104 cm2
The specified maximum capacitance can be used to find the corresponding depletion width from
W =
11.7 8.854 1014

= 6.9 105 cm
12
4
(1.5 10 10 )
The corresponding potential is
VD = Vbi W 2
q NA ND
= 2.8 V
2Si N A + N D
Since depletion capacitance increases as VD increases, a value of no more than 1.5 pF is guaranteed by the
voltage constraint VD 2.8V.
13.3 Small Signal Equivalent Circuit

For small signal circuit analysis, a semiconductor component is replaced by a small signal
equivalent circuit, which allows characterisation of the circuit response to the small signal input. The
small signal equivalent circuit is a linearized representation of the device operation at the bias point
created by the external circuit. A network analysis of a circuit containing small signal models gives
the response to a perturbation that is small compared to nonlinearities in the circuit. This response is
then understood to be itself a perturbation on top of whatever bias condition is present at an output
node.
Figure 13.4 shows the diode small signal equivalent circuit. This equivalent circuit is fairly
simple, since only two effects must be accounted for in the pn-junction structure, the conductance gD
and depletion capacitance Cdep (note that since the equivalent circuit uses the actual depletion
capacitance value Cdep, rather than the per unit area term C dep ). The values of gD and Cdep are
operating point dependent -the small signal equivalent circuit must therefore be constructed with
knowledge of the operating point conditions (ID for gD and VD for Cdep).
Figure 13.4: Diode small-signal equivalent circuit
69
70
Diode Switching
Chapter 14 Diode Switching

14.1 The pn-Junction Charge Control Equation
The transient or switching response of the diode is the temporal evolution of operation in response
to a sudden change of bias. For simplicity, a p+n structure will be assumed, so that the characteristics
are dominated by pn. The n-type material is long compared to Lp, and RS = 0. pn is now written as
pn(x,t). pn(x,t) is influenced by a spatial rate of change of Jp, as shown in Figure 14.1.
When J p ( x + dx ) > J p ( x ) , pn(x,t) must be decreasing in the differential volume - more are
leaving than are being supplied. Thus
pn ( x, t )
t
J
=
p grad .
1 J p ( x, t )
q x
(14.1)
Recombination will act to lower hole density, so for low level injection
pn ( x,t )
p ( x,t )
= U ( x,t ) = n
t U
0
(14.2)
These two independent physical effects may be added, and dpn/dt = dpn/dt recognized to give
pn ( x,t )
1 J p ( x,t ) pn ( x,t )
=
t
q x
0
(14.3)
(14.3) is now multiplied by qAD and integrated over the n-type neutral region
qAD
d
dt
cont.
xn
pn ( x,t ) dx = AD
cont.
xn
J p ( x,t )
dx qAD
x
cont.
xn
pn ( x,t )
dx
0
(C/cm2) in Figure 14.2 may be written

The integrated excess minority charge Q
p
(14.4)

( t ) q cont. p ( x,t )dx
Q
p
n
x

(14.5)
then this term identified in (14.4), to give
dQ p ( t )
Q ( t )
AD
= AD ( J p (cont.,t ) J p ( x n ,t )) AD p
dt
0
(14.6)
Figure 14.2: Stored charge per unit area, Q

p
In (14.6), Jp(cont.,t) is zero, since dpn/dx 0 at that point for a long length of material. The
remaining current density term ADJp(xn,t) is simply the
time dependent terminal current iD(t), since
+
the structure was assumed to be p n. (14.6) therefore becomes the charge control equation, relating
the time rate of change of excess hole density to the factors that can change the quantity with time
dQp ( t)
Q ( t)
= iD ( t) p
dt
0
(14.7)
14.2 Turn Off Transient

from steady state forward operation towards reverse bias, as shown in
When the diode is switched
Figure 14.3, the resulting response is termed the turn off transient.
Figure 14.3: Turn off transient

Before the transient, ID is determined by the forcing voltage, diode forward voltage VDon and R as
71
72
Diode Switching
IF =
VF VDon VF
R
R
(14.8)
where the approximation holds when VF >> VDon. Qp just before switching can be determined by
setting the time derivative in (14.7) to zero and solving
Qp (0 ) = IF 0
(14.9)
Because the diode stores charge, its terminal voltage cannot change instantaneously - at the instant
of switching, the current direction will reverse, but the charge will persist. Thus, Qp(0+) = Qp(0-).
state forward pn(x,t) distribution. When ID changes direction, holes will be
IF supports the steady
removed from n-type region and pn(x,t) will begin to collapse, as shown in Figure14.4(a). VD will
also fall towards zero, consistent with the xn boundary condition pn 0 exp(qVD kT ) . The time taken
for excess minority charge to be removed, when pn(x,t) passes through pn0 on its way to steady state
reverse bias, is termed the storage time ts.
(a) Storage time
(b) Recovery
Figure 14.4: Turn off transient in the diode
After ts, charge removal continues until a reverse bias of VR has built up across the diode, as
shown in Figure 14.4(b). This is termed the recovery phase of the turn off transient.
During the storage time, VD falls from VDon 0, and ID is approximately constant if VR >> VDon.
After ts, VD falls towards VR, and ID decreases accordingly, towards a steady state value of - IS VD and
ID are therefore as shown in Figures 14.5(a) and 14.5(b).
(a) Diode current during turn off.
(b) Diode voltage during turn off.
Figure 14.5: Current and voltage waveforms for the diode during the turn off transient.
The charge control equation can be used to derive a simple approximate expression for the storage
time tS. If VR >> VDon, IR VR/R. Substituting IR for iD(t) in (14.7) and rearranging gives
IR =
dQp ( t ) Qp ( t )
+
dt
0
(14.10)
( )
Solving (14.10) with boundary conditions Qp 0 + from (14.9) and Qp ( t s ) 0 gives

0
"
" I %
" V %
Q (t ) %
t
0 ln $ I R p '
= t 0s ts = 0 ln $1 F ' 0 ln $1 F '
0 & Q t=0+
# IR &
# VR &
#
)
p(
(14.11)
where the last equality holds if VF >> VDon and |VR| >> VDon.
After tS, the behavior is largely determined by the widening of the depletion region. The nonlinear
nature of C dep makes analysis difficult. An exponential charging behavior is often assumed.
Example 14.1:
Calculate ts if 0 = 0.5 sec, R = 10 k, VF = 8 V and VR = -10 V.
Solution:
A simple application of (14.11) gives
$ V '
$
8 '
t s = 0 ln&1 F ) = 0.5 106 ln&1
) = 0.29 sec
% 10 (
% VR (
14.3 Turn On Transient

The turn on transient occurs when the diode is in a steady state reverse bias condition and the
current is abruptly switched to a forward bias direction, as shown in Figure 14.6.
Figure 14.6: Turn-on transient conditions
73
74
Diode Switching
In the first phase of the transient, the forward current supplies minority carriers to raise the diode
voltage to zero, which can happen very quickly. The next phase of the turn-on characteristic is the
establishment of the minority carrier density profiles corresponding to steady state forward bias. The
process and terminal conditions are shown in Figure 14.7.
Figure 14.7: Turn on transient
Chapter 15 BJT Structure and Fabrication

15.1 BJT Structure
A simplified cross section of a planar integrated bipolar junction transistor (BJT) is shown in
Figure 15.1(a). Figure 15.1(b) illustrates forward active current flow, and indicates the active area.
The active area is extracted for 1D analysis as shown in Figure 15.1(c). The term vertical BJT refers
to the vertical orientation of the active area.
(a)
(b)
(c)
Figure 15.1: Vertical npn bipolar transistor (a) cross section, (b) current ow, (c) 1D approximation
This structure is very similar to the epi diode, with an extra counterdoped region for the emitter.
The collector implant is termed the sinker, and is designed to penetrate as far as possible into the epi.
A top view of the regions in the vertical npn structure is shown in Figure 15.2.
Figure 15.2: Top view
The masks required for fabrication can be deduced from this Figure. Multiple contacts are usually
used on the collector and base to improve reliability. The area of the active device is the emitter area
AE , defined by the product of the width bE and the length lE
AE = bE lE
(15.1)
The extraction of the 1D area in Figure 15.1(c) neglects some important effects regarding current
flow in the base region, which will be discussed in a later lecture. Parasitic resistances in the collector
are also ignored, but can be taken into account with external resistances as required.
75
76
BJT Structure and Fabrication
15.2 Fabrication of the Vertical npn Structure

A simplified set of process steps necessary to fabricate a vertical npn BJT is shown in Figure 15.3.
Figure 15.3: Steps in fabrication of the vertical bipolar structure.

Most of the steps have been discussed in the context of the epi diode. Note that Figure 15.3 shows
the n+ sinker and emitter being formed in one step -in practice these would be done separately,
because the requirements of the sinker and emitter are quite different.
15.3 BJT Nomenclature

The nomenclature for the BJT follows from the need to keep track of quantities in three regions
and two junctions. Definitions of widths and variables are shown in Figure 15.4. WC, WB and WE are
the widths of the neutral region in the collector, base and emitter, respectively. WBC and WBE are the
widths of the base collector depletion region and the base emitter depletion region, respectively. Note
that a width variable with a single subscript denotes a neutral region width, while a width variable
with two subscripts denotes a depletion region width between two materials. The width of each
neutral region can be calculated from the total material width and the extents of the depletion region
into each material.
Figure 15.4: BJT definitions

Built-in potentials and depletion widths are calculated by applying the junction equations
VbiBE =
W BE =
kT " N AB N DE %
ln$
',
q # n i2 &
2Si # 1
1 &
+
%
((VbiBE VBE ) ,
q $ N AB N DE '
VbiBC =
W BC =
kT " N AB N DC %
ln$
'
q # n i2 &
(15.2)
2Si # 1
1 &
+
%
((VbiBC VBC )
q $ N AB N DC '
(15.3)
Example 15.1:
Calculate the neutral region widths, minority densities and diffusion coefficients for the transistor structure
shown below at the bias condition indicated. lE = 10 m.
Solution:
Using the diode equations and VBC = VBE VCE = 0.8 1.5 = -0.7 V, the built in potentials and depletion
widths are found from
VbiBE
$
'
1017 1019 )
&
= 0.02586 ln
= 0.93 V,
& (1.45 1010 ) 2 )
%
(
W BE (VBE ) =
VbiBC
$ 17
'
10 5 1015 )
&
= 0.02586 ln
= 0.74 V
& (1.45 1010 ) 2 )
%
(
2 11.7 8.854 1014 %1017 + 1019 (

'
0.93 0.8) = 4.2 106 cm
19
17
19 * (
1.6 10
& 10 10 )
77
78
BJT Structure and Fabrication
W BC (VBC ) =
2 11.7 8.854 1014

1.6 1019
%1017 + 5 1015 (
' 17
0.74 + 0.7) = 6.3 105 cm
15 * (
& 10 5 10 )
WE , WB and WC are found by subtracting depletion region extents from material widths as indicated by
Figure 15.4(a)
$ N AB
'
4
WC = 4 104 W BC &
) = 3.4 10 cm
% N AB + N DC (
$ N AB
'
4
W E = 1104 W BE &
) 110 cm
% N AB + N DE (
$ N DE '
$ N DC '
4
W B = 1.5 104 W BE &
) W BC &
) = 1.4 10 cm
% N AB + N DE (
% N AB + N DC (
From the dopings, the equilibrium minority concentrations are
pE 0 =
n i2
= 21 cm-3 ,
N DE
nB 0 =
n i2
= 2.110 3 cm-3 ,
N AB
pC 0 =
n i2
= 4.2 10 4 cm-3
N DC
The diffusion coefficients are found from
DpE = DpC =
kT
p = 12.2 cm2 /sec,
q
DnB =
kT
n = 34.9 cm2 /sec
q
Chapter 16 Bipolar Transistor Operation

16.1 Regions of Operation
The four basic regions of operation of the bipolar junction transistor are distinguished by the
polarity of bias on each junction, and are summarized for an npn transistor in Figure 16.1.
(a) Forward active.
(b) Reverse Active.
(c) Saturation.
(d) Cutoff.
Figure 16.1: Regions of bipolar transistor operation.
The regions of operation of the bipolar transistor can also be represented on a IC vs. VCE plot such
as that of Figure 16.2, where the IC vs. VCE characteristics are shown for increasing IB values.
Figure 16.2: Regions of operation in IC -VCE
The forward active region corresponds to the upper right quadrant, with forward collector current
and positive VCE . The reverse active region is the complement, negative IC and VCE , so this region is
in the lower left quadrant. IC cannot be positive if VCE is negative, or negative if VCE is positive,
therefore operation in the upper left and lower right quadrants corresponds to cutoff operation. At a
given IC, lowering VCE will eventually cause the collector base junction to become forward biased,
moving the device into the saturation region of operation. Saturation operation is indicated by the
shaded areas of Figure 16.2.
79
80
Bipolar Transistor Operation
16.2 Forward Active Operation

Figure 16.3(a) shows the minority carrier distributions for forward active operation. The
equilibrium values reflect the normal doping values NDC < NAB < NDE. The concentrations are at their
equilibrium values at the contact edges, are set at the depletion edges by the polarity of bias across
the junction, and vary linearly because all materials are thin compared to the minority diffusion
lengths. Diffusion current components can be deduced from the minority carrier density derivatives
in each region, leading to Figure 16.3(b).
(a) Minority carriers
(b) Current components
Figure 16.3: Carriers and injection in forward active operation

In Figure 16.3(b), component 1 is termed the linking current, since it travels from emitter to
collector (note that the slope dnB/dx is the same at either end of the neutral base, thus diffusion
current must be the same). Term 2 is the back injection component. Term 3 is associated with hole
flow in the collector, and will be very small for forward active operation.
Transistor action refers to the relationship between the linking and back injection currents. If the
emitter is much more heavily doped than the base, electron injection will dominate hole injection
across the BE junction, but a proportional change in the back injection component will cause the
same proportional change in the linking current term, since the two both are determined by the BE
junction in forward active operation. If the emitter doping is much higher than that of the base, the
linking current (minority electron injection) term will be many times the back injection (minority
hole injection) term. Thus, the large linking current in the collector and emitter can be controlled by
the small back injection current in the base. This is the familiar gain mechanism of the bipolar
transistor.
Two elements are important to determine transistor action. The emitter doping must be much
higher than that of the base, so the linking current dominates the back injection term. The base region
must also be narrow, so that the BE and BC junctions interact. Two non-interacting junctions would
not form a good bipolar transistor, since nB(x) would not be linear, dnB(x)/dx would not be the same
on either side of the neutral base, and minority electrons injected into the base neutral region could
flow out the base instead of the collector.
Note that the apparent contradiction of having the large linking current flowing through the
reverse biased BC junction is in fact due to the interaction of the two junctions. The presence of the
BE junction close to the BC junction changes nB(x) on the p-side of the BC depletion region from
what it would be if the BC junction were isolated. The BE junction increases dnB(x)/dx to support the
linking current.
Example 16.1:
Calculate base emitter Jn and Jp for the device in Figure 15.5(a) using the Jdiff expressions, the depletion
edge boundary conditions and the neutral region widths already calculated.
Solution:
The values are found by explicitly calculating the slopes of pE(x) and nB(x) hen using the basic Jn and Jp
equations. Note that the electron injection linking current term dominates the hole back injection term.
% 21 21e 0.8 0.02586 (

2
J p = 1.6 1019 12.2 '
* = 11.2 A/cm
4
10
&
)
19
J n = 1.6 10
% 2.110 3 e 0.8 0.02586 2.110 3 (

3
2
34.9 '
* = 2.28 10 A/cm
4
10
&
)
16.3 Reverse Active Operation

The minority carrier distributions for the reverse active region of operation are shown in Figure
16.4(a). Since the roles of the emitter and collector have been reversed, the minority concentrations
are large at the edges of the base-collector depletion region and low at the edges of the base-emitter
depletion region. The current components are shown in Figure 16.4(b). The roles of the emitter and
collector have been reversed, so back injection is term 3 into the collector. With the collector more
lightly doped than the base, transistor action is severely compromised, since the linking current will
not dominate the effective back injection to the same extent as in forward active, where the true
emitter is more heavily doped.
Figure 16.4: Carriers and injection in reverse active operation
81
82
Bipolar Transistor Operation
16.4 Saturation Operation

The minority carrier distributions and currents for the saturation region are shown in Figures
16.5(a) and 16.5(b). Here the BE and BC forward biases raise the minority concentrations on both
sides of each depletion region. Note that the slope of nB(x) can be negative (VBC >VBE ), positive (VBE
>VBC), or zero (VBE = VBC), and hence the linking current can take on either sign and direction.
Figure 16.5: Carriers and injection in saturation operation
16.5 Cutoff Operation

The minority carrier distributions for the cutoff region of operation are shown in Figure 16.6(a).
The reverse bias potentials on both the base-emitter and base-collector junctions cause low values of
minority concentration on either side of each junction. Since the base minority electron concentration
is low on both sides of the neutral base, it is essentially zero over the entire width. The only current
flow is small reverse bias injection components into the emitter and collector.
Figure 16.6: Carriers and injection in cutoff operation
Chapter 17 Bipolar Transistor Injection Models

17.1 Current Components
An analytic bipolar injection model is formed by applying the basic diffusion equation to the
minority carrier distributions in each neutral region to find the individual current components, which
are then added together as appropriate. The only unknown term in the diffusion current equation in
each region is the slope of the linear minority carrier density, which can be found immediately from
the endpoint values and neutral region widths. Referring to Figures 17.1(a), 17.1(b) and 17.1(c),
I pC = qAE DpC
InB = qAE DnB
qA D p
pC 0e qVBC kT pC 0
= E pC C 0 (e qVBC
WC
WC
n B 0e qVBE
I pE = qAE DpE
kT
n B 0e qVBC
WB
pE 0 pE 0e qVBE
WE
kT
kT
kT
qAE DnB n B 0 qVBE

(e
WB
qAE DpE pE 0 qVBE

(e
WE
kT
1)
kT
(17.1)
e qVBC
kT
1)
(17.2)
(17.3)
(a) Collector
(b) Base
(c) Emitter
Figure 17.1: Minority distributions for forward active operation
17.2 Basic Injection Model

The injection model is formed by summing the individual current components. In order to form
quantities whose signs indicate direction relative to a terminal definition instead of a positive x
direction, the convention of Figure 17.2(a) is defined. Individual components are then added and
reconciled with these directions as shown in Figure 17.2(b).
83
84
Bipolar Transistor Injection Models
(a)
(b)
Figure 17.2: (a) positive terminal current definition, (b) correspondence to components
From Figure 17.2(b) and the identities in the previous section, the terminal currents are
I C = I pC + I nB =
qAE DpC pC 0 qVBC

(e
WC
kT
1) +
qAE DnB nB0 qVBE

(e
WB
collector hole injection
IB = I pC + I pE =
qAE DpC pC 0 qVBC

(e
WC
kT
kT
e qVBC
kT
(17.4)
linking (electron) current
1) +
qAE DpE pE 0 qVBE

(e
WE
collector hole injection
kT
(17.5)
1)
back injection
IE = InB + I pE =
qAE DnB n B 0 qVBE

(e
WB
kT
e qVBC
linking (electron) current
kT
)+
qAE DpE pE 0 qVBE

(e
WE
kT
1)
back injection
Example 17.1:
Calculate IC, IB and IC for the device in the example of Lecture 15. The emitter is 1.0 x 10 m.
Solution:
Using equations (17.4), (17.5) and (17.6),
(17.6)
IC = 2.4 1017 + 2.28 104 = 2.28 104 A

IB = 2.4 1017 + 1.12 106 = 1.12 106 A
IE = 2.28 104 + 1.12 106 = 2.29 104 A
Note that IC and IB are identical (to within round-off) to the current densities of the example in the previous
lecture multiplied by the emitter area.
17.3 Simplifications for Operating Regions

Forward Active Region
In the forward active region, VBE > 0 and VBC < 0, so those terms in the injection model multiplied
by exp(qVBE/kT) will dominate. The injection model equations may therefore be simplified to those
shown below, where the term numbers refer to the components from Figure 16.3(b) in the previous
chapter.
IC
qAE DpC pC 0 qAE DnB n B 0 qVBE

+
(e
WC
WB
term 3
kT
qAE DnB n B 0 qVBE

e
WB
(17.7)
kT
term 1
IB
qAE DpC pC 0 qAE DpE pE 0 qVBE

+
(e
WC
WE
term 3
qAE DpE pE 0 qVBE

e
WE
kT
kT
) = qA %$
(17.8)
kT
term 2
IE
qAE DnB n B 0 qVBE

(e
WB
term 1
kT
)+
qAE DpE pE 0 qVBE

(e
WE
# DnB n B 0
WB
DpE pE 0 & qVBE

(e
WE '
kT
(17.9)
term 2
In forward active operation, the collector injection term is negligible. Therefore, the currents are
dominated by the back injection (base and emitter) and linking current (collector and emitter) terms.
Using these equations, the forward active current gain F , defined as the ratio of collector to base
current, will be given by
I
F C
IB
fwd. active
qAE DnB n B 0 W B e qVBE
qAE DpE pE 0 W E e qVBE
kT
kT
DnB N DEW E
DpE N ABW B
(17.10)
85
86

The importance of the emitter to base doping ratio in affecting transistor action, and thus
determining forward active current gain, can be seen in (17.10), where F is directly proportional to
the ratio NDE/NAB.
Example 17.2:
Calculate F for the example bipolar device.
Solution:
F =
34.9 1019 104

= 204
12.2 1017 1.4 104
Reverse Active
Region
In the reverse region of operation, terms multiplied by exp(VBC) will dominate, so the model equations will simplify to (term numbers refer to the components from Figure 16.4(b))
IC
qAE DpC pC 0 qVBC

(e
WC
kT
qAE DnB n B 0 qVBC

(e
WB
term 3
kT
$ DpC pC 0
) = qA &%
E
WC
DnB n B 0 ' qVBC

)e
WB (
kT
(17.11)
term 1
IB
qAE DpC pC 0 qVBC

(e
WC
kT
qAE DpE pE 0 qAE DpC pC 0 qVBC
e
WE
WC
term 3
(17.12)
kT
term 2
IE
qAE DnB n B 0 qVBC

(e
WB
term 1
kT
qAE DpE pE 0
qA D n
E nB B 0 e qVBC
WE
WB
kT
(17.13)
term 2
Using these equations, the reverse active current gain R, defined as the ratio of emitter (since the
emitter is functioning as a collector) to base current, will be given by
I
R E
IB
rev. active
qAE DnB n B 0 W B e qVBC
qAE DpC pC 0 WC e qVBC
kT
kT
DnB N DCWC
DpC N ABW B
(17.14)
Comparing equations (17.10) and (17.14), the forward current gain is proportional to the ratio
NDE/NAB, while the reverse current gain is proportional to NDC/NAB. Since an integrated device
typically has NDE >> NAB >> NDC, the forward current gain is usually much higher than the reverse
current gain.
Example 17.3:
Calculate R for the example bipolar device.
Solution:
R =
34.9 5 1015 3.4 104

= 0.35
12.2 1017 1.4 104
Region
Saturation
In the saturation region, both VBE and VBC are positive, so less simplification is possible, however
a 1 can normally still be ignored compared to exp(VBE) or exp(VBC ), giving (terms from Fig.
16.5(b))
IC
qAE DpC pC 0 qVBC

(e
WC
kT
)+
qAE DnB n B 0 qVBC

(e
WB
term 3
kT
e qVBC
kT
(17.15)
term 1
IB
qAE DpC pC 0 qVBC

(e
WC
kT
)+
qAE DpE pE 0 qVBE

(e
WE
term 3
kT
(17.16)
term 2
IE
qAE DnB n B 0 qVBE

(e
WB
kT
term 1
e qVBC
kT
)+
qAE DpE pE 0 qVBE

(e
WE
term 2
kT
(17.17)
87
88

Cutoff Region
For the cutoff region, with VBE and VBC negative, all the exponential terms will be negligible compared to the 1 terms, giving (terms from Fig. 16.6(b))
!!! !!" !!!

!!
, !
!!! !!" !!!
term 3
!!
!!! !!" !!!

!!
term 3
, !
term 2
!!! !!" !!!

!!
(17.18)
term 2
Note that the linking current term has disappeared entirely, and the only components present are
the majority injection terms of holes from the emitter and collector into the base.
17.4 The Ebers-Moll Model

A more compact representation of the basic injection model equations (17.4) to (17.6) is possible
with a suitable grouping of terms and definitions of new parameters. A little algebra gives the result
that if the following definitions are made,
IES
qAE DnB n B 0 qAE DpE pE 0

+
,
WB
WE
ICS
qAE DnB n B 0 W B
,
qAE DnB n B 0 W B + qAE DpE pE 0 W E
qAE DnB n B 0 qAE DpC pC 0

+
WB
WC
(17.19)
qAE DnB n B 0 W B
(17.20)
qAE DnB n B 0 W B + qAE DpC pC 0 WC
then the injection equations (17.4) to (17.6) can be written
IC = F IES (e qVBE
kT
1) ICS (e qVBC
kT
1) F IF IR
IB = (1 F ) IES (e qVBE
kT
1) + (1 R ) ICS (e qVBC
IE = IES (e qVBE
kT
1) R ICS (e qVBC
kT
kT
1) (1 F ) IF + (1 R ) IR
1) IF R IR
(17.21)
(17.22)
(17.23)
The form of equations (17.21) to (17.23) suggests that IF and IR can be realized by diodes, and the
remaining terms by current controlled current sources. A circuit topology to realize this functionality
is shown in Figure 17.3.
Figure 17.3: Ebers-Moll representation
Example 17.4:
Calculate the Ebers-Moll coefficients for the example bipolar device, and use these coefficients and the
Ebers-Moll equations to verify the results for IE, IB and IC from the earlier example.
Solution:
IES = 8.38 1018 + 4.10 1020 = 8.42 1018 A,

F =
8.38 1018
= 0.995,
8.38 1018 + 4.11020
IF = 8.42 1018 (e 0.8 0.02586 1) = 2.25 104 A,
ICS = 8.38 1018 + 2.411017 = 3.25 1017 A

R =
8.38 1018
= 0.258
8.38 1018 + 2.411017
IR = 3.25 1018 (e0.7 0.02586 1) = 3.25 1017 A
Thus
IE IF = 2.25 104 A,
IC F IF = 0.995 2.25 104 = 2.24 104 A
IB (1 F ) IF = 0.005 2.25 104 = 1.13 106 A
89
90
The Early Effect, Breakdown and Self-Heating
Chapter 18 The Early Effect, Breakdown and Self-Heating

18.1 The Early Effect
When IC is plotted vs. VCE at constant IB, most devices exhibit an positive slope on the current
characteristic, known as the Early effect. Figure 18.1(a) illustrates the physical origin of this effect.
When the reverse bias across the base-collector junction increases, WBC increases, lowering WB. The
decreased WB increases the slope of nB(x), and hence the linking current. The slope is usually
characterised by the (approximate) IC = 0 intercept of the forward active characteristics, as shown in
Figure 18.1(b), which is termed the Early voltage VA.
(a) Origin
(b) The early voltage

Figure 18.1: The Early effect
18.2 Avalanche Breakdown

Avalanche breakdown is usually associated with the base-collector junction of a BJT, since the
device is usually operated in the forward active region. Figure 18.2 illustrates the avalanche
breakdown mechanism in the bipolar structure. A large reverse bias across the base-collector junction
increases the electric field, and if the field increases past a critical point, carriers can be accelerated to
the point where impact ionization will occur. The newly created electron-hole pairs are in turn
accelerated, and may cause secondary ionization, and so on, leading to a large increase in carrier
numbers, and hence current.
Two figures of merit used to characterise the breakdown voltage of a transistor, depending the
configuration of measurement sources. The notation used is to list the terminals being stimulated in a
subscript, with the condition of the third terminal usually O for open.
Figure 18.2: Avalanche breakdown.
BVCBO refers to the collector-base voltage at which breakdown occurs with the emitter opencircuited, as shown in Figure 18.3. This measurement treats the base-collector junction as an isolated
diode, measuring the same breakdown mechanism as was the case for the two terminal structure. The
source current is monitored, and breakdown is defined to occur when a predetermined excess current
is measured. Although this measurement is straightforward and gives an unambiguous definition, its
applicability to circuit operation is limited, since the open emitter condition rarely occurs in practice.
Figure 18.3: BVCBO
BVCEO is a measurement with the base terminal open and a source connected between the collector
and emitter, as shown in Figure 18.4. This is more representative of a circuit configuration in which
the base is connected to a high impedance. The breakdown mechanism for BVCEO continues to be impact ionization in the base-collector junction, but the overall operation is more complicated.
91
92
Figure 18.4: BVCEO
Carriers generated in the BC depletion region will be swept out by the electric field. Those
carriers injected into the base cannot flow out the base terminal, and therefore must be injected into
the emitter, and form an effective back injection component. Since the base-emitter junction has been
designed to provide maximum gain, this back injection component creates a corresponding large
base injection, which then flows to the collector. Thus, the BVCEO measurement effectively provides
gain of the impact ionization current through injection across the base-emitter junction. For this
reason, a threshold collector current defining breakdown will be reached at a lower VCE for the BVCEO
measurement than VBC for the BVCBO measurement. This mechanism is shown in Figure 18.5.
Prediction of the value of BVCEO is not as straightforward as for BVCBO (which simply uses the same
expression as for the diode), but BVCEO will be smaller than BVCBO, for the reasons described above.
Figure 18.5: The effect of transistor action during BVCEO measurement.
Example 18.1:
Calculate BVCBO for the transistor in example 1, using Ecrit = 2x105 V/cm. Will BVCEO be larger or smaller
than this value?
Solution:
Using the equation for VBR from the diode,
BVCB0 = VbiCB
2 "
SiE crit
1
1 %
+
$
' = 26.5V
2q # N AB N DC &
BVCEO is always smaller than BVCBO, because transistor action amplifies the effect of the impact ionization
current and produces higher collector current at a lower value of VCE , and hence VCB.
18.3 Self-Heating
Self-heating refers to the rise in temperature of a device due to its power dissipation. Although
self-heating is being presented here in the context of bipolar transistors, any device can potentially be
affected by self-heating. The resulting increased operating temperature is a long-term reliability
issue, and has important consequences for modelling.
Heat transfer between two bodies in one dimension is governed by the heat equation relating the
thermal flux (W/cm2) to the thermal conductivity (W/cm-K) and temperature gradient
dT
=
dx
(18.1)
This equation can be viewed physically as saying that the heat flux between two bodies is proportional to the difference in temperature
of the two bodies, with the constant of proportionality being
the thermal conductivity, . A higher at the same dT/dx results in larger , as shown in Figure 18.6.
(a) Large .
(b) Small .
Figure 18.6: Heat transfer
Any device that is absorbing (dissipating) electrical power is doing so by converting the energy to
some other form. When the energy is converted to heat, it is carried away from the device by heat
flux , as shown in Figure 18.7.
Figure 18.7: Resistor energy conversion
93
94
Although (18.1) could be applied directly, it is more convenient to define the temperature rise
above ambient Trise in terms of the power dissipation and a thermal resistance RTh (K/W), inversely
related to
Trise = PD RTh
(18.2)
The linearity of (18.2) allows the net effect of a complete thermal environment to be expressed as
the sum of a number of individual thermal resistances corresponding to stages in heat dissipation. For
example, Figure 18.8 showsa cross sectional view of a discrete bipolar transistor inside a package
which is sitting in still air. If the overall thermal resistance can be approximated by two values,
characterising the device to package and package to ambient, the overall thermal resistance of the
system is simply the sum of the individual thermal resistances.
Figure 18.8: Example thermal environment
Example 18.2:
The device in Figure 18.8 is operated with VBE = 1.0 V, IB = 2 mA, VCE = 5 V and IC = 100 mA. The device
to package RTh is 100 K/W and package to ambient is 200 K/W. If the ambient temperature is 25 C, what is
the operating temperature of the device?
Solution:
PD is found by summing IV at the base and collector with the emitter as reference
PD = 1.02x10-3 + 5.0100x10-3 = 0.5 W
The total RTh is the sum of the individual thermal resistances, so the temperature rise is
RTh = 100 + 200 = 300 K/W,
Trise = 0.5300 = 150 K
Since the ambient temperature is 25 C, the device is operating at a temperature of 175 C.
If the operating temperature of the device is too high, component lifetime can suffers due to accelerated failure. To reduce the operating temperature, a heat sink is often used to lower the package to
ambient RTh.
Example 18.3:
The operating temperature of the device in the previous example is to be limited to 125 C. If a heat sink is
added that reduces the package to ambient RTh from 200 to 25 K/W, will the device meet the specification?
Solution:
With the heat sink, the new thermal resistance and temperature rise are
RTh = 100 + 25 = 125 K/W,
Trise = 0.5125 = 62.5 K
Assuming the ambient temperature is 25 C, the device is now operating at a temperature of 87.5 C, which
is within the specification.
From a modelling point of view, the operating temperature of a bipolar transistor, whether influenced by self-heating or by the environment in which the device is operating, is an important
parameter to take into account in predicting terminal currents because some of the physical
parameters which determine the terminal currents are themselves temperature dependent. By far the
strongest temperature dependence is in the intrinsic density ni, which is more than exponentially
dependent on temperature, doubling approximately every 6-7 C. This means that the equilibrium
minority densities pE0, nB0 and pC0 which appear in the injection equations (17.4), (17.5) and (17.6)
are strong functions of temperature, and therefore strongly influence the terminal current. For a
device operated with a fixed VBE, the current will be extremely sensitive to temperature, since it will
be proportional to the minority density.
In considering self-heating in a device, the technique used in the previous examples can only give
a first order approximation of the temperature rise, since the terminal currents are functions of the
temperature. A more accurate result therefore requires an iterative solution, where the power
dissipation is calculated from the terminal conditions, a new operating temperature is calculated, the
terminal conditions are updated, then a new power dissipation is calculated, and so on. State of the
art circuit simulators, which take thermal resistance into account, will perform this iteration
automatically.
95
96
BJT Base Resistance and Small Signal Modelling
Chapter 19 BJT Base Resistance and Small Signal Modelling

19.1 Base Resistance
In a vertical integrated bipolar device, as shown in the simplified view of Figure 19.1, base
current must flow through the extrinsic base material to the edge of the active transistor region, then
through the intrinsic base region of the active device.
Figure 19.1: BJT base material region
Figure 19.2(a) shows a simplified view of the extrinsic base region, ignoring the portion under the
base contact. Since the region of current direction change has been neglected, resistance is
determined by the dimensions in Figure 19.2(b). If the resistivity of the extrinsic material is Bx, the
extrinsic base resistance rBx is then
rBx =
Bx sB
W B lE
(19.1)
The intrinsic region of the base is illustrated in Figure 19.2(c) and 19.2(d).
(a) Region
(b) Dimensions
(c) Region
(d) Dimensions
Figure 19.2: Base regions: (a-b) intrinsic, (c-d) extrinsic
Analysis of the intrinsic region is complicated by the fact that current flow does not occur through
parallel surfaces of the material. Current flows from the base through the side of the region, and is
injected into the emitter through the top. The simple R formula can therefore not be used directly.
To analyse the situation, the assumption is made that flow into the emitter is constant along the
top of the internal base region, as shown in Figure 19.3(a). As carriers are injected into the emitter,
fewer flow through the internal base, so the x-direction current is reduced. If the flow into the emitter
is uniform, the resulting x-direction current is linear, as shown in Figure 19.3(b). i(bE) = 0
corresponds physically to the fact that all the base current is injected into the emitter.
(a) 1D base current flow.
(b) Linear i distribution.
Figure 19.3: Intrinsic base current flow and linear distribution.
The equivalent base resistance is then found by determining the potential at x = 0 corresponding to
the current distribution in Figure 19.3(b), then dividing that potential by the current at x = 0. The
current at any point x and the resistance associated with flow to that point are given by x
#
x&
i( x ) = iB %1 (,
$ bE '
R( x ) =
Bi x
W B lE
(19.2)
Each point x contributes i(x)R(x) to the potential, so the potential at x = 0 is
V (0) =
1
bE
bE
0
R( x )i( x ) dx =
1
bE
bE
0
$ Bi x '$ $
x ''
BiiB bE
i
1
&
&
) B&
)) dx =
W B lE 6
% W B lE (% % bE ((
(19.3)
The internal base resistance rbb is then (note: 1/6 the resistance associated with flow straight
through)
rbb' =
V (0) 1 BibE
=
iB
6 W B lE
(19.4)
Example 19.1:
Calculate rBx and rbb for the example bipolar structure. Assume the base contact separation is 15 m, and
that the base doping is uniform.
Solution:
Since the base is uniform, Bi = Bx is given by
97
98

1
Bx = Bi = (1.6 1019 1017 480) = 0.13 - cm

Substituting values,
rBx =
0.131.5 104
= 139 ,
1.4 104 10 104
rbb' =
1
0.131104
= 15.5
6 1.4 104 10 104
19.2 Low Frequency Small Signal Equivalent Circuit

The low frequency hybrid-pi equivalent circuit of the bipolar transistor is shown in Figure 19.4.
Figure 19.4: Low-frequency BJT equivalent circuit
The base resistances are in series with a component r = 1/g modeling the emitter back injection
base current component, dIB/dVBE. The transconductance gm models dIC/dVBE . These values are
found for forward active operation as
gm
dIC
d #qAE DnB n B 0 qVBE
=
e
%
dVBE dVBE $ W B
dIB
q
q
I
1 gm
=
IB =
IC B = gm
=
dVBE kT m
kT IC
F F
kT
& q
IC
(=
' kT
(19.5)
(19.6)
Note that dWB/dVBE in g was ignored, which means the Early effect has been neglected for that
component. The Early effect is included explicitly through ro.
Example 19.2:
Calculate r and gm for the example bipolar structure.
Solution:
Using the equations above and the value of F calculated earlier
gm =
1.6 1019
2.28 104 = 8.8 103 S,
23
1.38110 300
g =
8.8 103
= 4.3 105 S
204
19.3 High Frequency Small Signal Equivalent Circuit

There are two important physical origins of capacitance in the bipolar structure. The first,
depletion capacitance, is identical to that considered for the case of a pn-junction, in this case applied
to each of the two junctions, as shown in Figure 19.5(a).
(b) C dep
(a) Origin
Figure 19.5: BJT C dep
The pn-junction C dep model is applied to this situation, defining base-emitter and base-collector
depletion capacitances
(0) =
C depBE
C depBC (0) =
Si
W BE (0)
Si
W BC (0)
C depBE (VBE ) =
C depBC (VBC ) =
C depBE (0)
(1 VBE
VbiBE )
z BE
C depBC (0)
(1 VBC
VbiBC )
CdepBE = C depBE AE
z BC
CdepBC = C depBC AE
(19.7)
(19.8)
The second type of capacitance found in the bipolar structure is diffusion capacitance. The origin
of diffusion capacitance is the relationship between stored base charge and base-emitter voltage. As
depicted in Figures 19.6(a) and 19.6(b), excess minority charge Q is stored in the base region.
B
99
100
(VBE)
(a) Q
B
(VBE + VBE)
(b) Q
B
Figure 19.6: Physical origin of diffusion capacitance.
This charge is a function

of VBE through theBE depletion region boundary condition. Q
B
/dVBE can
increases with increasing VBE , and vice versa. Since dq/dv is non-zero, a capacitance d Q
B
gives the base diffusion capacitance C (F) as
be associated with this behavior. An analysis of Q
B
C = B gm
where the base transit time B is
(19.9)
W B2
B =
2DnB
(19.10)
If the diffusion and depletion capacitances are added to the low frequency equivalent circuit of
Figure 19.4, the result is the high frequency hybrid- equivalent circuit shown in Figure 19.7.
Figure 19.7: High frequency hybrid- small signal equivalent circuit.
Example 19.3:
Find the depletion and diffusion capacitances for the example bipolar structure.
Solution:
Using the equations already given,
W BE (0) = 1.1105 cm
C depBE (0) = 9.4 108 F/cm2
C depBE = 2.5 107 F/cm2
W BC (0) = 4.5 105 cm
C depBC (0) = 2.3 108 F/cm2
C depBC = 1.7 108 F/cm2
B = 2.8 1010 sec C = 2.5 1012 F
19.4 Transit Frequency

One of the most widely used figures of merit for a bipolar transistor is the transit frequency fT , the
frequency at which the magnitude of the short circuit collector to base current gain becomes unity.
Figure 19.8(a) shows the condition used to measure the short circuit current gain.
(a) Circuit
(b) Small-signal representation
Figure 19.8: Circuit and small-signal equivalent for fT
From a phasor analysis of the circuit in Figure 19.8(b)
IC = Vb' e ( gm jCdepBC ),
IB = Vb' e ( jCdepBE + jC + g + jCdepBC )
gm jCdepBC
IC
1
=
IB g + j (CdepBE + C + CdepBC ) j (CdepBE + CdepBC ) gm + B
(19.11)
(19.12)
The frequency at which the magnitude of this is unity is then given by
2fT (CdepBE + CdepBC ) gm + B
fT =
2 (CdepBE + CdepBC ) gm + B
(19.13)
101
102
Example 19.4:
Calculate fT for the example bipolar structure.
Solution:
All the necessary values have been calculated in previous examples.
fT = 5.6x108 Hz = 560 MHz
Chapter 20 MOSFET Structure and Processing

20.1 Structure
Figure 20.1 shows a simplified cross section of a Metal-Oxide-Semiconductor Field-Effect
Transistor, or MOSFET. The MOSFET in constructed on a semiconducting substrate, either p-type,
for an n-channel device, or n-type, for a p-channel device. Substrate contact may be at the backside
or through diffusions at the surface. The gate of the device is a layer of conductive material separated
from the substrate by a thin layer of insulating silicon dioxide called the gate oxide.
Figure 20.1: MOSFET
The oxide capacitance C ox is given in terms of the oxide thickness tox as
C ox = ox
t ox
(20.1)
The gate is heavily doped polycrystalline silicon, also called polysilicon or poly. Polysilicon has a
structure between crystalline and amorphous, with grains of local crystallinity separated by grain
boundaries, as shown in Figure 20.2.
Figure 20.2: Poly
103
104
MOSFET Structure and Processing

Poly is not suitable for carrying current, due to the noise generated by carrier flow across the grain
boundaries. A thick field oxide surrounds the device on all sides to isolate the gate poly from the
substrate outside the device. A second level dielectric isolates the gate poly from other conductive
layers. The source and drain are formed by heavily doped regions, n+ for an n-channel device, and p+
for a p-channel device.
Example 20.1:
Calculate C ox for a MOSFET whose gate is 20 nm thick (ox given in the Appendix).
Solution:
3.9 8.854 1014

C ox =
= 1.73 107 F/cm2
20 107
20.2 Fabrication
The first step in fabrication of an n-channel MOSFET structure is the definition of the active
region of the device, which will contain the gate polysilicon, the source and the drain. A layer of
silicon nitride (Si3N4) is deposited over a protective pad oxide and patterned, as shown in Figure
20.3(a). Thermal oxidation is used to form the field oxide, as shown in Figure 20.3(b), usually by a
wet process, since the oxide does not have to be the highest quality. The intrusion of the field oxide
under the nitride in MOSFET fabrication is termed the birds beak effect, and limits the minimum
dimension of the active area. Once the nitride and pad oxide are removed, the active area is defined
by the opening in the field oxide, much like the substrate diode.
The gate oxide and poly are then deposited and patterned, as shown in Figure 20.3(c). The gate
oxide is formed by dry oxidation, since it is thin but must be of extremely high quality, since any
imperfection could result in a short between the gate and substrate.
The source and drain are then implanted as shown in Figure 20.3(d). In this step a mask is not required - the process is self-aligning, since the gate protects part of the active area from implantation.
Any active region not covered by poly will receive the implant. Lateral diffusion of dopant occurs
under the gate, making the distance between the source and drain edges lower than the gate poly
dimension.
The second level dielectric insulation oxide is then deposited and contact cuts to the source, drain
and possibly gate poly are etched. Metal is then deposited and patterned, as shown in Figures 20.3(e)
and 20.3(f).
Figure 20.3: MOSFET fabrication
20.3 Mask Layout, Geometry and Symbols

A simplified mask set for constructing a basic MOSFET structure is shown in Figure 20.4(a). The
active region mask defines the region containing the source, drain and gate. The gate is defined using
a polysilicon mask. Wherever the polysilicon and active regions coincide, the gate will be separated
from the substrate by only the thin gate oxide. A contact cut mask defines areas where holes are
etched through the second level dielectric to contact the source and drain (or a polysilicon line
running underneath), and the metal mask defines areas of metallization.
As shown in Figure 20.4(b), the drawn gate length differs from the effective gate length L by the
amount of lateral diffusion. The channel width W is the distance along which the gate overlaps the
source and drain diffusions. The width and length of the important area of the MOSFET for current
conduction are shown in the top view of Figure 20.4(c). Note that the active area of the channel is
WL, i.e. the product of the width and the effective channel length (the drawn length minus twice the
lateral diffusion).
105
106
MOSFET Structure and Processing
Figure 20.4: MOSFET layout and geometry
The schematic symbols and positive voltage definitions for n and p-channel devices are shown in
Figures 20.5(a) and 20.5(b), respectively. The substrate is connected to whatever potential guarantees
reverse bias of the source-substrate and drain-substrate junctions, the most negative circuit potential
for a p-substrate n-channel device, or the most positive for n-substrate p-channel.
Figure 20.5: Schematic symbols
Chapter 21 MOSFET Operation

21.1 Drift Conduction
Drift is the movement of a charged particle due to the influence of an electric field. For a
semiconductor, 1D drift current density may be expressed in terms of electron and hole velocity vn
and vp (cm/sec) as
(21.1)
J = qnv n + qpv p
In silicon, carrier velocity is related to electric field by the characteristic shown in Figure 21.1. At
low fields, v is linearly proportional to E, with mobility as the proportionality constant. Mobility
therefore represents velocityper unit electric field. At higher fields, scattering limits the maximum
obtainable velocity, and the carriers experience velocity saturation.
Figure 21.1: Velocity versus electric field for silicon
Mobility is affected by a number of factors. n for (conduction band) electrons is higher than p
for (valence band) holes because the conduction band is less densely populated, allowing easier
movement. Higher levels of doping increase scattering and lower mobility. Mobility increases with T
and low temperatures, when carriers gain more energy than the crystal, and decreases with T at
higher temperatures when the crystals vibration increases scattering. Surface is lower than in bulk
material due to the extra scattering at a surface.
For low values of E, v is proportional to E, allowing (21.1) to be written
J = qnn E + qp p E = (qnn + qp p )E = E,
1
qnn + qp p
Example 21.1:
What maximum V can be applied across a region of silicon 2 m wide before vn saturates?
(21.2)
107
108
MOSFET Operation
Solution:
Using Figure 21.1, v saturates at E 2 x 104 V/cm, corresponding to 2 x 104 2 x 10-4 = 4 V.
21.2 Threshold Voltage

Figures 21.2(a) and 21.2(b) depict a basic MOS structure with a grounded, p-type substrate and a
gate potential VGB creating an electric field from the gate into the substrate. The field will repel
majority holes from the surface, creating a depletion region of negative fixed (uncompensated
acceptor) charge, and attract mobile minority electrons to the surface.
(a) Depletion
(b) Inversion
Figure 21.2: MOS structure
At low fields the density of electrons attracted to the surface is negligible, and substrate depletion
charge balances that on the gate. Increasing the field requires increased gate charge (higher
potential), which is balanced by a widening of the depletion region.
At higher fields the density of minority electrons attracted to the surface becomes dominant. Further
increases in gate potential, and hence gate charge, are then compensated by increased minority
electron density, with the depletion region width, and hence charge, no longer increased. The
minority electron layer at the surface shields the depletion region from further increases in electric
field. In this region of operation, the electron layer density, and hence conductivity, can therefore be
modulated by the gate-induced electric field. This modulation of conductivity is the field-effect
referred to in the name of a JFET or MOSFET.
The gate potential at which the mobile minority electron density dominates the characteristic is
the threshold voltage VT. The mobile minority electron charge is called the inversion layer, and forms
the channel.
21.3 Electric Fields in the MOSFET

As depicted in Figure 21.3, the MOSFET is characterised by a transverse field from gate to
substrate and a lateral field between source and drain. Although explicit separation of the two effects
may not be valid in a modern small geometry MOSFET, superposition can be used in the discussion
of long-channel devices, so the two effects will be discussed separately here for a basic insight.
Figure 21.3: MOSFET electric fields
The transverse field is that considered in Section 21.2, which is formed by the balance of charge
on the gate and in the substrate, and is responsible for inducing the inversion layer. An increase in
transverse field increases inversion layer density. The lateral field is created when a potential
difference exists between the source and drain. The lateral field causes drift conduction of the mobile
electron inversion layer charge. An increase in lateral field causes greater current density through the
channel.
21.4 MOSFET Operation

If a MOSFET is operated with a gate-source bias below the threshold voltage, no inversion layer
is formed. The depletion regions around the source and drain and that under the gate are continuous,
since the source and drain are immediately adjacent to the gate edge. For zero VDS, the sourcesubstrate and drain-substrate depletion regions are symmetrical, so the cross section of Figure 21.4(a)
is obtained. Increased VDS widens the depletion region around the drain-substrate junction, since this
represents an increase of drain-substrate reverse bias. This in turn affects the depletion region under
the gate at the drain end, as shown in Figure 21.5(b). No drain to source current flows, because there
is no mobile electron flow (channel) under the gate.
(a) VDS = 0
(b) VDS > 0
Figure 21.4: VGS < VT
109
110
MOSFET Operation
If VGS > VT, an inversion layer is formed at the substrate surface under the gate, contacting the
source and drain diffusions since they are adjacent to the gate edge, as shown in Figure 21.5(a). With
zero VDS the depletion regions are again symmetrical, and although the channel is present, no
current flows since there is no lateral electric field. As shown in Figure 21.5(b), a positive value of
VDS creates a lateral electric field, and causes conduction through the inversion layer (channel) by
drift. This increased reverse bias on the drain widens the depletion region and lowers the mobile
electron concentration at the drain end, again by virtue of VDS representing a reverse bias. Increasing
VDS therefore increases current flow, but at a decreasing rate with respect to VDS.
(a) VDS = 0
(b) VDS > 0
Figure 21.5: VGS > VT
As the drain potential increases further, the drain-substrate reverse bias continues to increase; the
electron inversion layer density at the drain end continues to decrease. The point at which the
electron inversion layer density becomes very small is termed the pinchoff condition, and is depicted
in Figure 21.6(a). The value of VDS at which pinchoff occurs is the saturation voltage VDS,sat. Further
increases in drain potential, and hence lateral field, are then absorbed by the formation of a high field
region at the drain end, as shown in Figure 21.6(b). Drift current is supported past pinchoff by the
high field maintaining the nE product when n becomes small. Current in this region continues to increase with increasing VDS as the mobile channel recedes, but the rate of change with VDS is much
smaller.
(a) At pinchoff
(b) Past pinchoff

Figure 21.6: Pinchoff
21.5 Regions of Operation and Current Characteristics

Cutoff in the MOSFET is defined by VGS < VT, with ideally no current flow for any VDS (although
a small current may be possible for VGS very near VT ). Triode operation is the region defined by VGS
> VT and VDS < VDS,sat, the pre-pinchoff mode. Saturation is the region VGS > VT, VDS > VDS,sat, after
pinchoff has occurred.
Figure 21.7(a) shows the commonly used MOSFET ID vs. VDS at constant VGS characteristic, with
curves for different VGS values plotted on the same axis. For cutoff ID = 0 for any VDS. In the triode
region, ID increases for increasing VDS, but at a decreasing rate, since the drain end channel density is
decreasing. The pinchoff point depends on VGS since it is defined by the VDS sufficient to cause the
drain end mobile charge to become small. A larger value of VGS causes a larger initial mobile charge
density, and hence a larger value of VDS required to reduce the value. In saturation, ID is a weaker
function of VDS, but still a strong function of VGS through the transverse fields effect on the mobile
charge density.
Another widely used MOSFET characteristic is ID vs. VGS at constant VDS, shown in Figure
21.7(b). For VGS < VT, ID = 0 regardless of the value of VDS, so all the curves coincide with the VGS
axis below VT. As VGS is increased at a given VDS, conduction begins with the device starting out in
saturation operation. Physically, this is due to the fact that if VGS is close to VT, the inversion layer
density will be small, and the drain end of the channel will start out pinched off due to the non-zero
VDS. As VGS increases, the inversion layer density builds up, and eventually a point is reached where
the drain end is no longer pinched off and the device moves into triode operation. The larger the
(fixed) value of VDS, the greater the transverse field required to overcome the reverse bias on the
drain, so the transition between saturation and triode occurs at a higher value of VGS.
The ID - VGS characteristic can also be visualized on the ID VDS plot of Figure 21.7(a). The
condition of constant VDS corresponds to a vertical line on Figure 21.7(a), so the ID - VGS characteristic
is the behavior of the device as the operating point moves up the vertical line, i.e. as VGS increases.
(a) ID vs VDS
(b) ID vs VGS
Figure 21.7: MOSFET characteristics
111
112
MOSFET Threshold Voltage
Chapter 22 MOSFET Threshold Voltage

22.1 The Fermi Level
Equilibrium between materials can be understood using the energy band diagram by introducing
the concept of the Fermi Level EF , which has several physical interpretations, the most common as a
chemical potential driving reactions. For our purposes, it is simply an energy level within the band
structure whose properties can be used in various derivations.
The position of EF can be calculated for a given semiconducting material in terms of n and p from
n = N c e( E c E F ) kT ,
p = N v e( E F E v ) kT
(22.1)
where Nc and Nv are the effective densities of conduction and valence band states respectively, and
are tabulated value for a given material.
In intrinsic material n = p, so equations (22.1) can be equated and the result rearranged to give the
result below, showing that EF is approximately at midgap, the level Ei, for intrinsic material
! !
!"#$!"%!&
!!
!
!"
!
ln
!!
!!
!!
(22.2)
For doped material, the Fermi level position will no longer be at midgap. In n-type material, as
shown in Figure 22.1(a), EF will be above Ei, since n = ND >> ni and hence Ec - EF must be smaller
than its value for intrinsic material (Eg/2). EF moves closer to Ec as donor doping increases. The
position may be found explicitly as
# N p&
#N &
E c E F = kT ln% c ( = kT ln% c2 (
$ n'
$ ni '
(22.3)
Similarly, for p-type material EF is below midgap, since p = NA >> ni and hence EF Ev must be
smaller than its value for intrinsic material, given explicitly by
#N n&
#N &
E F E v = kT ln% v ( = kT ln% v2 (
$ p'
$ ni '
(22.4)
A polysilicon MOSFET gate is heavily doped p+ or n+ to achieve low resistance. Therefore the
position of EF will be assumed as Ec for an n+ gate, and as Ev for a p+ gate.
(a) n-type
(b) p-type
Figure 22.1: Position of EF in a doped semiconductor
Example 22.1:
Calculate the position of EF relative to Ev for silicon at 300K with 2x1016 cm3 of Boron. Is EF above or
below Ei?
Solution:
The position of the Fermi level relative to Ev is found with p NA as
% 1.04 1019 (
E F E v = 8.62 105 300 ln'
= 0.16 eV
16 *
& 2 10 )
Since Eg = 1.08 eV, EF is therefore below Ei, as expected.
22.2 Work Function Difference

When the MOS system is formed, charge redistribution will take place so that the substrate and
gate Fermi levels align, creating a potential difference between the gate and the substrate. Since no
current flows, this potential can be considered an electrostatic offset, which can then be compensated
by an appropriate potential on the gate.
The determination of the original gate and substrate Fermi level separation uses the concept of the
work function, , the energy difference between EF and a reference vacuum potential. The work
function of the gate is dened as M and that of the substrate as S, as shown in Figure 22.2.
Figure 22.2: MS
The work function difference, which represents the energy difference between the gate and
substrate, is then
MS M S
(22.5)
For polysilicon gate silicon substrate devices, MS can be expressed in terms of the silicon band
gap, since the gate and substrate band diagrams will have the same position relative to the reference
level. In general, MS will be
positive for a p+ gate and negative for an n+ gate, with the value relative
to Eg/2 determined by the substrate type. Figure 22.3 shows two examples.
113
114
Figure 22.3: Work function differences for two combinations of gate and substrate types
Example 22.2:
Calculate the work function difference for an n+ poly gate and a substrate with NA = 2x1016 cm3 .
Solution:
For this situation,
MS = ( E c E F ) substrate = E g ( E F E v ) substrate = (1.08 0.16) = 0.92 eV
22.3 The Flat Band Condition and Band Bending in the MOS Structure
Since energy = -/q, non-zero implies spatial variation of energies in the band diagram. The flat
band condition in the substrate is defined as zero and E, as shown in Figure 22.4(a). The gate
potential required for this condition is the flat band voltage VFB, the negative of the potential
corresponding to the work function difference energy (note that VFB = MS, although the units are
different)
&1.602 1019 [ J/eV] )

VFB = MS [eV] (
+
q[ J/V]
'
*
(22.6)
With VGB > VFB, < 0, E > 0 and > 0 in the substrate. Since energy = -/q, the substrate bands
bend downwards nearing the surface, as shown in Figure 22.4(b). At inversion, Ei is below EF at the
surface by the amount it is above Ei in the substrate, with the bulk potential B (V) defined by
kT $ N A '
ln& )
q % ni (
The potential at the substrate surface at inversion is therefore 2B.
(22.7)
(a) Flat band
(b) Depletion
(c) Inversion
Figure 22.4: MOS band bending
Example 22.3:
Calculate the bulk potential for a MOSFET substrate which is doped with NA = 2x1016 cm-3 .
Solution:
$ 2 1016 '
B = 0.02586&
= 0.37 V
10 )
% 1.45 10 (
22.4 Substrate Depletion Charge

For VGB VFB, the per unit gate area depletion charge in the substrate is given by
Q dep = 2qSi N A (2 B )
(22.8)
This charge appears on one side of the oxide capacitance C ox , implying that the negative of this
charge must appear
on the gate, as shown in Figure 22.5. The gate potential corresponding to the
depletion charge is therefore Q dep C ox .
Figure 22.5: MOS substrate gate depletion charge per unit area
115
116
22.5 Threshold Voltage Calculation

The threshold voltage is then the (electrostatic) sum of all potentials required for inversion
VT =
VFB
2 B
2qSi N A (2 B )
C
(22.9)
ox
flat band band bending
depletion charge
Example 22.4:
Calculate VT for a MOSFET with an n+ poly gate, a 20nm thick oxide and substrate with NA = 2 x1016 cm-3 .
Solution:
% 1.602 1019 (
VFB = MS '
* = 0.92 V
q
&
)
Q dep = 7.0 108 C cm2
VT = 0.92 + 2 0.37
7 108
= 0.22 V
1.73 107
Chapter 23 The MOSFET Square Law Model

23.1 Co-ordinate System and Model Assumptions
A 1D analysis is not possible for the MOSFET, since quantities vary with substrate depth and
position in the channel, thus more than one dimension is required in the co-ordinate system, as shown
in Figure 23.1. Also illustrated in Figure 23.1 is one of the key assumptions in the derivation:
uniformity in the z direction.
Several other important assumptions are made in deriving the square law model of MOSFET
operation. The device is assumed to be n-channel with a uniformly doped substrate. Steady state
operation is assumed, and current flow is taken to be zero for VGS VT. Only drift conduction is
considered, and in the initial derivation velocity saturation is ignored.
Figure 23.1: MOSFET co-ordinates substrate
23.2 Triode Region Model

In the triode region (VGS >VT and VDS < VDS,sat), the drift electron current density is given by
J n ( x, y ) = qn ( x, y )n ( x, y )E ( x, y )
(23.1)
This expression may be integrated over x and z, i.e. a slice of the channel at a point y as shown in
Figure 23.2, to give
xc
J n ( x, y ) dxdy =
xc
qn ( x, y )n ( x, y )E ( x, y ) dxdy
(23.2)
where xc is a point sufficiently far from the surface so that all the necessary mobile (inversion)
charge is captured. The exact value of xc will not be necessary.
117
118
The MOSFET Square Law Model
Figure 23.2: z, x integration
At steady state, the lhs of (23.2) is simply ID. On the rhs, integration with respect to z is a multiplication by W, since the structure is assumed uniform in z, giving
xc
(23.3)
ID = Wq 0 n ( x, y )n ( x, y )E ( x, y ) dx
In general, (x) models the decreasing surface scattering moving into the substrate, and (y)
allows for the changing E, and hence tendency to be pulled to the surface, along the channel. These
effects may be coarsely combined into a constant effective surface mobility n and moved outside
the integral.
In (23.3), E is the lateral electric field, so E(x) denotes the change in lateral field with depth into
the substrate. In general, E decreases with x, as shown in Figure 23.3.
Figure 23.3: Electric field assumption
However, over the thin inversion layer 0 x xc, the change can be neglected for a simple model,
and E taken as a constant, now depending only on y, and hence may be moved outside the integral
xc
(23.4)
ID = nWE ( y )q 0 n ( x, y )dx
(C/cm2) may be identified in (23.4), allowing the modification shown

A total mobile charge Q
m
xc
Q m ( y ) q 0 n ( x, y ) dx
ID ( y ) = nWE ( y )Q m ( y )
(23.5)
A final integral with respect to y gives
L
0
ID ( y ) dy = nW
E ( y )Q ( y )dy
0
I D = n
W
L
E ( y )Q ( y )dy
0
(23.6)
From Poissons equation, the lateral electric field may be written in terms of the surface potential
S. ((x=0)) as E(y) = -dS /dy This also suggests that a change of integration variable from y to S
will simplify the problem. The variation of y from 0 (source end) to L (drain end) is expressed in S
as SS (source end) to SD (drain end)
ID ( y ) = n
W
L
L
0
d
Q m ( y ) S dy
dy
I D = n
W
L
SD
SS
E ( y )Q m ( S )d S
(23.7)
The MOS structure itself requires 2B surface potential for inversion. At the source, the surface
potential SS is the substrate value 2B plus the reverse bias VSB. Similarly SD = 2B + VDB, and thus
ID = n
W
L
2 B +VDB
2 B +VSB
Q m ( S )d S
(23.8)
is determined indirectly through a charge balance, involving an important

The mobile charge Q
m
assumption known asthe gradual channel approximation. Charge is assumed to balance between the
gate and substrate at all points along the channel, in other words the contribution of the source and
drain to controlling channel charge is ignored. This assumption is reasonable for long channel
devices, but
is less accurate for short channel devices, and will be reconsidered in a later lecture.
(C/cm2) must be balanced by
Under this approximation, the total per unit gate area gate charge Q
G
(C/cm2), which in turn is determined by the mobile
the total per unit gate area substrate charge Q
S
charge and the depletion charge
Q G = Q S = Q m + Q dep
Qm= QG Qdep ID = n
L
2 B +VDB
2 B +VSB
(Q
+ Q dep d S
(23.9)
Q
G is found from C ox and the gate (VGB - VFB) and surface (S) potentials
Q G = [(VGB VFB ) S ]C ox
(23.10)
( ) = qN x ( ) , leading to Q ( ) = 2q N ( ) . However,
The depletion charge Q
dep
S
Si A
S
dep
S
A p
S
is
possible useful ID equation, the square law derivation assumes that Q
to achieve the simplest
G
constant along the channel at the source end value, as shown in Figure 23.4, resulting in
( )
Q
dep
S
sq. law
( ) = 2q N (2 + V )
=Q
dep
SS
Si A
B
SB
(23.11)
119
120
Figure 23.4: Square law Q

dep
Substituting these charges into the integral and simplifying gives
W
ID = n C ox
L
2 B +VSB
&
2qSi N A (2 B + VSB ) )
((VGB VFB S ) +
+d S
C ox
('
+*
(23.12)
After performing the integration, substituting limits and simplifying, ID is given by
ID = n C ox
2 B +VDB
W
L
2.
+%
2qSi N A (2 B + VSB ) (
V VSB ) 0
-'VGB VSB VFB 2 B
*(VDB VSB ) ( DB
(23.13)
*
2
-,'&
0
C ox
)
/
A more general form of the threshold voltage may be identified from (23.13)
VT = VFB + 2 B +
2qSi N A (2 B + VSB )
C
ox
= VFB
2qSi N A
+ 2 B +
+
C ox
C ox
(23.14)
2 B + VSB 2 B
The original MOS VT may now be regarded as that for VSB = 0, and is defined as the zero bias
threshold voltage V , and the dependence of V on V is termed threshold modulation The multiplier
To
T
SB
in the VSB dependent term is defined to be the threshold modulation parameter V ,
( )
VTo = VFB + 2 B +
2qSi N A (2 B )
,
C
2 B + VSB 2 B
ox
VT = VTo +
2qSi N A
C ox
(23.15)
Example 23.1:
Find if NA = 2x1016 cm-3 and tox = 20 nm.
Solution:
2 1.6 1019 11.7 8.854 1014 2 1016

= 0.47 V
1.73 107
With
the definition of VT for the square law model and the simplifications VGS = VGB - VSB and VDS
= VDB - VSB, (23.13) can be simplified to the familiar square law triode region current expression
ID VGS >VT
VDS VDS,sat
= n C ox
2 '
W$
VDS
V
V
V
&( GS
)
T ) DS
L%
2 (
(23.16)
23.3 The Square Law Pinchoff Condition
0 at the drain end

(23.16) is valid until the pinchoff point VDS , defined by Q
m
0 = (VGB VGB 2 B VDS,sat VSB )C ox + 2qSi N A (2 B + VSB )
(23.17)
This equation can be rearranged to give
VDS,sat square law = VGB VSB VFB 2 B
= VGS VT
C
(23.18)
ox
VGS
VT from (23.14)
It is important to note that (23.18) applies only to the square law model, and results from the
constant Q dep assumption made in derivation of the square law model.
23.4 Saturation Region Model

For VDS > VDS,sat, the channel is pinched off and the extra electric field is absorbed by a high field
region near the drain. The simplest model for the drain current in this operating region is to assume
that the width of this high field region is small compared to the channel length, which implies that the
drain current does not change past pinchoff
ID VGS >VT
VDS VDS,sat
W #V 2 &
W
= n C ox % DS,sat ( = n C ox
L$ 2 '
L
# (V V ) 2 &
T
%% GS
((
2
$
'
(23.19)
121
122
Example 23.2:
Calculate the drain current flowing in the transistor whose layout is shown in Figure 23.5(a) for the
potentials shown in Figure 23.5(b). Assume 0.1 m of lateral diffusion in the source and drain. The gate type,
oxide thickness and substrate doping are identical to the previous examples.
(a) Layout (1 square = 1m).
(b) Potentials.
Figure 23.5: Layout and potentials for MOSFET example.
Solution:
From the layout of Figure 23.5(a), the channel width is 8 m, and the drawn channel length is 2 m.
Subtracting the lateral diffusion of the source and drain, the channel length L is 1.8 m. The bulk node is
grounded while the source is at a potential of 1 V, so the potentials required for the square law model are
VSB = 1 0 = 1 V,
VGS = 3 1 = 2 V,
VDS = 4 1 = 3 V
The threshold voltage including the effect of threshold modulation will be
VT = 0.22 + 0.47
2 0.37 + 1 2 0.37 = 0.43 V
The applied VGS value of 2 V is larger than the threshold voltage, so the device is conducting. To determine
the region of operation, the value of the saturation drain source voltage VDS is rst found from (23.18)
VDS,sat = 2 0.43 = 1.57 V
Since the applied VDS of 3 V is larger than VDS,sat, the device is in the saturation region of operation. The
drain current is therefore given by equation (23.19). Substituting values gives
2
8 104 % (1.57) (
'
* = 5.0 104 A
ID = 530 1.73 10
1.8 104 '& 2 *)
7
Chapter 24 Channel Shortening and dc Parameter Extraction

24.1 Channel Shortening
Past pinch-off, the high field region at the drain end of the channel results in a reduction of the
effective (electrical) channel length by an amount L, as shown in Figure 24.1(a), a process termed
channel shortening. As L increases and L decreases, current increases.
0 at the drain end, the square law charge balance equation is no longer valid. An
Once Q
m
empirical modification to account for channel shortening multiplies the ID equations by a term with a
linear dependence on VDS, characterised by the channel shortening parameter . Note that both
expressions are multipled by (1 + VDS) to ensure continuity of ID.
= n C ox
ID VGS >VT
2
W $ (VGS VT ) '
))(1+ VDS )
= n Cox &&
L%
2
(
VDS VDS,sat
2 '
W$
VDS
V
V
V
(
)
& GS
)(1+ VDS )
T
DS
L%
2 (
ID VGS >VT
VDS VDS,sat
(24.1)
(24.2)
The effect of on ID characteristics is shown in Figure 24.1(b).
(a) Mechanism
(b) Modelling
Figure 24.1: Channel shortening
Example 24.1:
Find Iout in the current mirror circuit of Figure 24.2, assuming VDD = 5 V, VSS = 5 V, Iin is 200 A, both the
transistors have the structure and dimensions of the previous examples and = 0.025 for the output transistor.
Ignore channel shortening on the input transistor.
123
124
Channel Shortening and dc Parameter Extraction
Figure 24.2: Current mirror for example problem.
Solution:
Note that both devices are operating in the saturation region. Since channel shortening is ignored on the
input transistor, the value of VGS reects exactly 200 A of current, and so the term multiplying (1+VDS) on
the second transistor will be 200 A. Thus
Iout = 200x10-6(1+0.02510) = 250x10-6 A
In reality the input transistor should have channel shortening taken into account, however this would
require the solution of a cubic equation to find VGS.
24.2 MOSFET Parameter Extraction

For triode operation (VDS < VGS VT, VGS > VDS + VT ) at small VDS, the square law model
simplifies to
ID n C ox
W
L
((VGS VT )VDS )
(24.3)
This suggests that a measurement of ID vs VGS at small VDS will yield a straight line characteristic
whose intercept on the VGS axis is VT , and whose slope is proportional to n . A measurement of ID vs
VGS with 0 can therefore be used to extract VTo and n by fitting a line to the linear part of the
characteristic and extracting VTo from the intercept, and n from
n =
dID dVGS
Cox (W L)VDS
This process is illustrated in Figures 24.3(a) and 24.3(b).
(24.4)
(a) VTo
(b)
Figure 24.3: VTo and
n extraction
From another measurement at VSB > 0, a straight line fit will yield
VT , thus can be found from
(Figure 24.4(a))
VT VTo
=
2 B + VSB 2 B
Once VT and
(24.5)
n are found, is found from the slope of the ID vs VDS in saturation (Figure 24.4(b))
dID
dVDS
2
W # (VGS VT ) &
((
= n Cox %%
L$
2
'
VGS const.
(24.6)
(a)
(b)
Figure 24.4: and extraction
125
126
Short Channel Threshold Voltage Effects
Chapter 25 Short Channel Threshold Voltage Effects

25.1 Charge Sharing in the MOSFET Channel
In order to achieve inversion, the substrate charge Q dep must be compensated by charge on the
gate. The inclusion of all Q dep in the VT expression is an assumption that all the depletion charge is
compensated by the gate, as shown in Figure 25.1(a). However, in practice some of the depletion
charge is compensated by charge in the source
and drain, as shown in Figure 25.1(b). Thus, Q dep is
an overestimate
of the amount of gate charge required for inversion With Q dep in the expression for
VT , the threshold voltage is therefore overestimated. This problem will be more severe as L is
reduced, since the amount of charge controlled by the source and drain will become
a greater
proportion of Qdep .
(a) Gate control
(b) Shared control
Figure 25.1: Control of Q

dep
25.2 The Trapezoidal Depletion Charge Model
A relatively simple model for charge sharing may be obtained on a geometric basis, as shown in
Figure 25.2. The channel regions at the source and drain ends are partitioned into areas controlled
only by the source or drain, and areas controlled only by the gate.
The source is assumed to have a cylindrical cross-section. The point of intersection between the
depletion region that would be obtained with only the source, and the depletion region that would be
obtained with only the gate is identified. A line is constructed from the substrate surface at the source
to this point. The gate is assumed to control all charge on the channel side of this line. The drain is
also assumed to have a cylindrical cross-section, and the same method is followed. This trapezoidal
model is named for the resulting shape of gate-controlled charge. The charge controlled by the gate is
2
then Q dep
" (C/cm ), to distinguish it from the total depletion charge Q dep . Clearly Q dep
" < Q dep .
Figure 25.2: Trapezoidal model
Since only Q dep

" is controlled by the gate, Q dep is replaced by Q dep
" in the VTo expression
" may be found in terms of Q dep by finding the area of the trapezoid as a function of the overall
Q dep
area. The result of this analysis involves the radius of the cylindrical junction profile xJ (cm) and the
widths of the source and drain depletion regions WS (cm) and WD (cm), respectively
For any practical structure, the correction term is less than 1, leading to Q dep
" < Q dep as expected.
The depletion widths may be approximated using the pn-junction expression for a one-sided junction
(1/ND of the source/drain ignored) and the built-in potential approximated as the inversion condition
S = 2 B.
Example 25.1:
Recalculate VT for the example MOSFET using the trapezoidal model. Assume a source/drain junction
depth of 0.3 m
Solution:
Using the equations above, WS = 3.36x10-5 cm and WD = 5.5x10-5 cm, giving
" = Q dep (1 0.16) = Q dep (0.84 )

Q dep
VTo 0.92 + 2 0.37
7.0 108 0.84

= 0.16 V
1.73 107
127
128
Short Channel Threshold Voltage Effects
Previously VTo = 0.22 V; this result is lower because less charge is controlled by the gate.
25.3 Length and Bias Dependence

The effect of channel length and VDB variation on VT can be understood by examining the effect of
these changes on the trapezoidal area ( Q dep
" ) as a proportion of the rectangular area Q dep . Figures 25.3
(a) and (b) show cross-sections before and after a reduction in L. Since the trapezoidal area is a lower
proportion of the rectangular area as L decreases, VT is reduced as L decreases. Figures 25.3 (c) and
(d) show cross-sections before and after an increase in VDB. As VDB increases, the drain depletion
region widens and the proportion of the rectangular area in the trapezoid is reduced. Hence, VT is
lowered if VDB increases. Figure 25.4 shows a plot of VT evaluated using the expressions given for
variation in L and VDB.
(a) L
(b) L
(c) VDB
(d) VDB
" resulting from an increase in VDB

Figure 25.3: Decrease of Q
dep
Figure 25.4: Plot of trapezoidal model VTo for varying channel length at two drain biases.
25.4 Mitigation of the Short Channel VT Effect

Two strategies are pursued to mitigate (reduce) the effect of short channel VT effects, both of
which can be understood as methods designed to increase the proportion of the rectangular area
occupied by the trapezoid. Increasing the substrate doping, as shown in Figures 25.5 (a) and (b),
decreases the depletion widths. Decreasing xJ, as shown in Figures 25.5 (c) and (d), reduces the area
of that part of the rectangle assigned to the source and drain.
(a) NA
(b) NA
(c) xJ
Figure 25.5: Mitigation of short channel VT
(d) xJ
129
130
MOSFET Small Signal Model
Chapter 26 MOSFET Small Signal Model

26.1 Low Frequency Small Signal Equivalent Circuit
The low frequency hybrid- MOSFET small signal equivalent circuit shown in Figure 26.1
contains a transconductance gm, the rate of change of ID with respect to VGS at constant VDS
gm =
dID
dVGS
= n C ox
VDS const.
W
(VGS VT )(1+ VDS )
L
(26.1)
and an output conductance go, the rate of change of ID with respect to VDS at constant VGS
go =
dID
dVDS
= n C ox
VGS const.
W
L
# (V V ) 2 &
T
%% GS
((
2
$
'
(26.2)
Note that the gate oxide is assumed to be a perfect insulator.
Figure 26.1: MOSFET low frequency hybrid-
26.2 Source/Drain Depletion Capacitance

The source and drain regions form pn-junctions with the oppositely doped substrate, and hence
depletion capacitances will be present. For generality, the capacitances are modeled as shown in
Figures 26.2(a) and 26.2(b): sidewall capacitance, associated with the depletion regions around the
sides, and bottom capacitance, associated with the depletion regions on the bottom faces.
(a) Sidewall
(b) Bottom
Figure 26.2: MOSFET Cdep
To separate capacitance into process and geometrical quantities, CdepSw (F/cm) models the zero bias
sidewall depletion capacitance per unit length of s/d periphery (not including the channel side) PS
(cm) and PD (cm) respectively, and C depBot (F/cm2) models the zero bias bottom depletion capacitance
per unit area of the s/d, AS (cm2) and AD (cm2), respectively. The complete source-bulk and drain bulk
depletion capacitances, CSB (F) and CDB (F), respectively, are then the sums of these two components.
Using the standard depletion
capacitance model and parameters for each junction
Example 26.1:
Find CSB and CDB for the MOSFET example structure assuming CdepSw =3x10-11 F/cm, C depBot =
4x10-8 F/cm2, and the s/d dopings are 1019 cm-3 and z for each junction is 0.4. NA = 2x1016 cm-3
Solution:
The periphery and area of the source and drain are PS = PD = 4 + 8 + 4 = 16 m and AS = AD = 48 = 32
m2, and the built in potential is 0.89 V. Noting that the potentials VSB and VDB are reverse biases, the junction
capacitances are then
CSB =
CDB =
3 1011 16 104
(1 (1)
0.89)
0.4
4 108 32 108
(1 (1)
0.89)
0.4
= 4.5 1014 F
3 1011 16 104 4 108 32 108

+
= 3.11014 F
0.4
0.4
(1+ 4 0.89)
(1+ 4 0.89)
26.3 Extrinsic MOSFET Capacitance

Extrinsic capacitance is that arising from overlaps within the physical structure of the device. As
illustrated in Figures 26.3(a) and 26.3(b), overlap due to lateral diffusion causes extrinsic gate
source/drain capacitances CGS,ovl (F) and CGD,ovl (F). Figures 26.3(c) and 26.3(d) illustrate the origin
of the extrinsic gate substrate overlap capacitance CGB (F).
(a) Top view
(b) Drain end
(c) Top view
(d) Cross section
Figure 26.3: Extrinsic MOSFET capacitances (a-b) gate s/d, (c-d) gate bulk
131
132
MOSFET Small Signal Model
Layout dependent terms in the overlap capacitances are isolated by grouping into per unit width
quantities CGS,ovl (F/cm) and CGD,ovl (F/cm).
"
"
CGS,ovl
= CGD,ovl
ox
x ovl ,
t ox
"
CGS,ovl = CGD,ovl = CGS,ovl
W
(26.4)
For the gate-substrate overlap, a per unit channel length term CGB,ovl (F/cm) is extracted from
measurements, and the gate source extrinsic capacitance is written as
"
CGB = CGB,ovl
L
Example 26.2:
(26.5)
Calculate CGS,ovl, and hence CGS,ovl and CGD,ovl, as well as CGB for the example MOSFET structure (LD =
0.1 m, CGB,ovl = 1.1x10-12 F/cm).

Solution:
"
"
CGS,ovl
= CGD,ovl
=
3.9 8.854 1014

0.1104 = 1.73 1012 F/cm
20 107
CGS,ovl = CGD,ovl == 1.73 1012 8 104 = 1.38 1015 F
26.4 Intrinsic
MOSFET Capacitance
Intrinsic capacitances are those arising from the voltage dependence of internal charge. The most
important for loading are CGS(F) and CGD(F), as illustrated in Figure 26.4(a). By strict definition,
these capacitances are CGS = dQG/dVGS and CGD = dQG/dVGD, and hence depend on the gate charge,
which is balanced by both depletion and inversion charge in the substrate. However, a reasonably
useful model can be obtained by assuming that inversion charge dominates in the substrate, so that
the derivatives are of Qm with respect to the voltages.
With this assumption, both capacitances are zero for VGS < VT , since the inversion layer is not
present. In triode, the capacitances can be shown to be given in terms of the total oxide capacitance
Cox = WLC ox by
CGS
) #
&2,
V
V
2
(
)
GS
T
DS
= Cox +1 %
( .,
3 +* $ 2(VGS VT ) VDS ' .-
CGD
) #
&2,
V
V
2
(
)
GS
T
= Cox +1 %
(.
3 +* $ 2(VGS VT ) VDS ' .-
(26.6)
The values therefore vary from CGS = CGD = Cox/2 in heavy triode, where the inversion layer is
symmetrical, to CGS = 2Cox/3 and CGD = 0 at pinchoff, where the mobile charge has gone to zero at
the drain end. Note that it is not required to have CGS + CGD = Cox, since surface potential varies along
the channel (i.e. the charge-voltage relationship between Qm and VGS is different than that of QG to the
total channel).
Much like the initial triode region current expression, in the saturation region CGS and CGD are
maintained at their pinchoff values. Figure 26.4(b) shows CGS and CGD normalized to Cox for VDS
normalized to VDS,sat = VGS - VT . Heavy triode operation is VDS 0, for which Cox splits equally
between CGS and CGD, since the two ends of the channel are symmetrical. Figure 26.4(c) shows CGS
and CGD normalized to Cox for VGS - VT normalized to VDS. Heavy triode operation VDS << VGS - VT
now corresponds to the asymptotic x . The capacitances are zero below threshold, where the
inversion layer is not present.
(a) Gate loading
(b) CGS, CGD
(c) CGS, CGD
Figure 26.4: MOSFET intrinsic capacitances
26.5 High Frequency Small Signal Equivalent Circuit

If the appropriate capacitive components are included in the structure of Figure 26.1, the high
frequency hybrid-pi equivalent circuit of Figure 26.5 is obtained. Note that the bulk terminal is now
shown, since the source bulk and drain bulk sidewall and bottom capacitances as well as the gate
substrate overlap capacitance are connected to this node. If the source and substrate are connected
together, CGB appears in parallel with CGS and CGS,ovl.
Figure 26.5: MOSFET high-frequency hybrid-
133
134
Scaling and Velocity Saturation
Chapter 27 Scaling and Velocity Saturation

27.1 Constant Field MOSFET Scaling
In MOSFET fabrication and modelling, scaling refers to the reduction in physical size of
MOSFET devices. The scaling of channel and contact dimensions, as illustrated in Figure 27.1, is
straightforward: all dimensions are reduced by a scaling factor > 1, for example optically using the
same mask set and increasing the factor by which the reticle image is reduced.
Figure 27.1: MOSFET geometry scaling
Simple geometrical scaling causes imbalances in the structure that must be addressed with other
changes. Beginning from the structure of Figure 27.2(a), scaling to L results in the structure of
Figure 27.2(b).
(a) Before
(b) L scaling by
(c) Final scalings
Figure 27.2: Constant eld MOSFET scaling
With no other changes, the reduction in L will increase the lateral field, leaving the transverse
field unchanged. This imbalance can be addressed by lowering VDS to VDS. However, from a
practical point of view it is not possible to lower only VDS, all potentials must be lowered, implying
that VGS is lowered to VGS as well. Since this restores the imbalance that was the problem in the first
place, the oxide thickness is reduced to tox (note that there are other reasons to lower potentials, so
only tox is not sufficient). After these scalings, the substrate doping is scaled to NA and the
source/drain junction depths to xJ to mitigate the short channel effects discussed in a previous
lecture. The result is the structure of Figure 27.2(c). Because this approach attempts to preserve the
original field magnitudes, it is termed constant field scaling.
There are several consequences on device performance as a result of constant field scaling,
summarized in Table 27.3. C ox = ox t ox , so it scales by . Scalings cancel in W/L. Voltages are
scaled by 1/ , so the overall scaling of current is 1/ . Power scales as 1/ 2, since both V and I are
reduced. Absolute capacitance scales as 1/ , since per unit area capacitances are increased by but
area is decreased by 1/ 2. Delay, which is proportional to (V/I)C (an RC like quantity), will then
scale as 1/ . The power

delay product, a useful overall metric for digital performance, will scale as
3
1/ . In practice, these scalings cannot all be realized by exactly the factor, but the trends are all
valid, and are the reason that MOSFET scaling is so actively pursued in technology development.
Figure 27.3: Constant field scalings
27.2 MOSFET Velocity Saturation

Full scaling of potentials is not possible in practice, which means that fields tend to be larger in
smaller geometry devices. An increase in lateral field makes the square law model assumption of
v = E less applicable, and requires a more accurate treatment of velocity saturation.
A useful model for velocity saturation can be written in terms of a low field mobility o (cm2/Vsec) and a critical field Ecrit (V/cm) (not the same Ecrit as for impact ionization)
v=
oE
1+ E E crit
(27.1)
with o = 710 cm2/V-sec and Ecrit = 1.7x104 V/cm for silicon. Incorporating this model into an
intermediate point in the square law derivation, the result is
ID = nW
xc
oE
q 0 qn ( x, y )dx
1+ E E crit
ID = nW
oE
Q m ( y )
1+ E E crit
(27.2)
135
136
Scaling and Velocity Saturation
If the denominator on the right hand side is taken to the left hand side and both sides are then
integrated with respect to y over the channel length, the result is
L
0
ID dy +
L
0
ID
E ( y)
dy = nW
E crit
E ( y )Q ( y )dy
(27.3)
On the left hand side, the first term is simply IDL, while the second term will reduce to the integral
of E(y) over the channel length, which is the drain source voltage VDS, thus
!
V $
I D # L + DS & = nW
" crit %
( y)Q ( y) dy I
0
= n
W
L (1+VDS
( y)Q ( y) dy
( L ))
crit
(27.4)
The denominator term outside the integral is the only difference with the original square law
model at the same point in the derivation, thus the integral will proceed in exactly the same manner,
and the square law model can simply be modified to include the denominator term
I D VGS >VT
= nC ox
I D VGS >VT
= nC ox
VDS VDS,sat
VDS VDS,sat
W
L (1+VDS
2
#
V &
% (VGS VT ) VDS DS ( (1+ VDS )
2 '
( Lcrit )) $
W
L (1+VDS,sat
2&
#
V
%% (VGS VT ) VDS,sat DS,sat (( (1+ VDS )
2 '
( Lcrit )) $
(27.5)
(27.6)
One way to view the effect of velocity saturation, therefore, is to consider the channel length to be
increased by a factor (1 + VDS,sat/EcritL) For long channel lengths this term approaches 1, meaning
velocity saturation has little effect. This makes sense physically, since a long channel length has
lower lateral field and less velocity saturation effect. Furthermore, the correction term suggests that a
larger VDS or lower Ecrit increases the effect of velocity saturation. This again corresponds to physical
intuition, since a larger VDS means a larger lateral field and hence increased effect of saturation, and a
lower Ecrit means the onset of velocity saturation effects occurs at lower values of lateral electric
field.
Example 27.1:
Assuming Ecrit = 104 V/cm, calculate the L increase term for the example device.
Solution:
The length correction term is that multiplying the length in the more general expressions (27.5)
and (27.6), (1+VDS,sat/EcritL). Substituting values gives
1+
VDS
3
= 1+
= 1.98
4
LE crit
1.8 10 1.7 10 4
The magnitude of the correction term indicates that velocity saturation will be important in this device at a
channel length of 1.8 m.
Assuming the channel length is small enough so that velocity saturation is significant, the VDS
term in the denominator correction factor also changes the nature of the voltage dependence on
current. The point where dID/dVDS is equal to zero will be lower due to the extra term in the
denominator, and in saturation the drain current will be proportional to VGS - VT not (VGS - VT)2. Since
the drain current in saturation depends on VDS,sat (c.f. equation (23.19)), the presence of VDS in the
denominator correction term means ID will be proportional to VDS,sat, not VDS,sat2 as before. This lowers
the effective transconductance of the device.
Figure 27.4 shows a comparison of the ID - VDS characteristics for the square law model with and
without velocity saturation The importance of velocity saturation is clear from the large difference in
saturation region current.
Figure 27.4: ID -VDS characteristic with and without velocity saturation.
This difference would be mitigated to some extent by incorporating the velocity saturation term in
to the parameter extraction process. The value of the low field mobility would then reflect the
presence of the velocity saturation term.
A surprising result is the loss of dependence of the drain current on the channel length L. If the
VDS/(LEcrit) term dominates 1 in the denominator correction factor, the L factors cancel and the
dependence on L is removed (alternatively, the term L(1+VDS,sat/EcritL). can be written L+VDS/Ecrit
and VDS/Ecrit can be assumed to be dominant). This effect, observed for many years in small
geometry devices, can be explained physically by noting that when velocity saturation occurs, the
drain current is limited by the velocity of carriers along the channel, not by the lateral electric field.
Thus, if velocity saturation is the limiting factor, ID loses its dependence on L because carrier
movement along the channel is no longer a function of the lateral electric field.
137
138
Process Variation, Testing, Packaging and Reliability
Chapter 28 Process Variation, Testing, Packaging and Reliability

28.1 Process Variation
Process variation refers to small perturbations in processing conditions during fabrication of
devices with similar structures.
For example, growth of a layer of silicon dioxide by thermal oxidation requires control of both
time and temperature, and variation of either of these (e.g. a gradual change in the calibration of the
temperature sensor) will lead to variation in oxide thickness. In photolithography, variations in the
finite accuracy of reticle and mask generation as well as mask alignment cause geometrical variations
in devices. The doping profile of a junction is affected by both the dopant concentration and wafer
temperature, which can change as a result of dopant flow control or temperature sensing. Wet etching
uses a chemical reaction to remove material, so a change in the concentration of etchant solution will
affect the rate of etching.
Each process technology step requires control of one or more conditions, and the finite precision
and accuracy of this control leads to variations in processing, and hence device performance. This
process variation leads to small changes in the structure and doping profiles of fabricated devices,
and hence to variation of electrical behavior and model parameters.
Normally large numbers of devices are measured and the relevant parameters extracted and the
results are analysed statistically to allow process variations to be included in circuit modeling. The
statistics are also used to feedback and adjust the processing parameters to ensure the process is
producing devices having the parameters desired. This is called statistical process control (SPC).
28.2 Testing and Packaging

Before scribing and cleaving, wafer level testing is performed to check chip functionality. Signals
are routed to and from the chip through probes contacting the chips metal connection pads.
Although frequency limitations of the probes prevents testing at full speed, identification of faulty
parts at this stage is crucial to avoid the waste involved in packaging of non-functional parts.
The wafer is then scribed and cleaved and the operational die are packaged. In a wire-bond
package, such as the 8-pin dual inline package shown in Figure 28.1, wires connect metal contact
points on the wafer to the package pins. Once the die is inside the package, it is subjected to full
speed testing (to specification). This level of testing is usually more expensive and time consuming.
Yield, the fraction of parts that meet some criteria, is critical in semiconductor manufacturing.
Two important distinctions are made: functional yield refers to the fraction of manufactured circuits
that work at all, and parametric yield refers to the fraction of operational circuits that achieve rated
performance. Both numbers are important, since a process with high functional yield but low
parametric yield produces many working parts, but few of which work well enough, while a process
with low functional yield but high parametric yield produces working parts that mostly achieve
specified performance, just very few that work at all.
Figure 28.1: 8-pin DIP package.
28.3 Reliability Modelling

Entirely separate from testing is the issue of reliability, a major concern to the manufacturers of
integrated circuits and systems since the cost of servicing components in the field can be larger than
the original cost of the component. Much effort is therefore put into reliability studies and methods
for minimizing failure mechanisms. The key parameter used in reliability modelling is the failure
rate, the average number of failures that occur in a large population per unit time.
Many different physical systems, despite the differences in failure mechanisms and lifetime scale,
exhibit the basic failure rate vs operating time behavior shown in Figure 28.2, which is referred to as
the bathtub curve. This is not a mathematical prediction, simply a characteristic that has been
observed in reliability modelling over many different components and systems.
The failure rate characteristic in Figure 28.2 is broadly divided into three regions. Early failures
are those that occur very soon after manufacture, usually due to a manufacturing problem or
weakness in the basic structure (e.g. a weak chip-package connection that holds during testing but
opens when the chip is mounted, or a processing problem resulting in gate oxide contamination and a
shortened MOSFET lifetime). Failure rate decreases with time in the early failure region, as the
weakest parts fail and are removed from the population. In normal operation, the failure rate is
(relatively) constant, as variations in both longer term failure mechanisms and environment tend to
cancel. In the wearout phase, failure rate increases again as the majority of parts near the end of their
expected lifetime.
Characterising reliability on a real time scale is not practical, since components are normally
expected to last for years. Accelerated life testing, in which the effect of failure mechanisms is
enhanced, usually by operation at an elevated temperature, can be used to compress the time scale.
Figure 28.2: The bathtub curve
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140
28.4 Electromigration
One cause of failure in modern integrated circuits is electromigration, the movement of physical
material under pressure caused by electrical current. The effect of electromigration is most serious at
a via, the connection between two layers of metal, where a void may be formed, as shown in Figure
28.3. Aluminum is not suitable for the connection, so the dissimilarity between the two types of
metal leads to separation of the metal at the top of the connection under the pressure of
electromigration. This raises the resistance of the connection, causing more power dissipation and
heating, which enhances the electromigration effect.
Figure 28.3: Void formation.
Ultimately, as shown in Figure 28.4, all connection may be lost between the metal layers, which
will result in an open connection, and hence almost certainly an nonfunctioning circuit. Since
electromigration is enhanced by temperature elevation, accelerated life testing is very useful in
investigation and characterisation. The effect of electromigration is reduced by the use of other
metals in the via, as well as layout techniques to add multiple current paths for lines carrying high
currents.
Figure 28.4: Open via
28.5 Hot Carrier Effects

As discussed earlier, true constant field scaling of the MOSFET cannot be achieved in practice
due to the difficulties presented in scaling all circuit potentials. Modern short channel devices
therefore exhibit higher channel electric fields, and a larger degree of carrier velocity saturation for
larger VDS values.
The term hot carriers describes high velocity, and therefore high energy, electrons or holes, which
typically occur at the drain end. As Figure 28.5 illustrates, there are two principal results of the high
carrier channel velocity, referred to as hot carrier effects.
Carrier injection into the gate oxide occurs when channel carriers entering the high-field region at
the drain retain enough energy after being scattered by the silicon lattice atoms to force their way into
the structure of the silicon dioxide gate insulator. This results in a component of uncompensated
charge, which modifies the threshold voltage by altering the flat band condition. Even more
seriously, charge injection into the gate oxide damages the structure of the oxide and will lead
eventually to failure of the insulator and conduction between the gate and substrate.
Avalanche multiplication at the drain end of the channel creates extra electron-hole pairs in this
region. The existing lateral and transverse electric fields separate these charges, resulting in an
increased drain current as well as a component of substrate current. This extra component of drain
current is undesirable, since it is difficult to control and can cause local heating at the drain end of the
channel.
Figure 28.5: Hot electron effects
The most common technique for mitigating hot carrier effects is the lightly-doped drain or LDD
structure shown in Figure 28.6. Extra processing steps are used to form a more lightly doped region
between the heavily doped drain and the channel. The lighter doping increases the effective
resistance of these regions, essentially introduces a series resistance in the source and drain leads.
Similarly to the case of the parasitic diode series resistance, this results in a potential drop across the
internal MOSFET device (i.e. across the channel itself) relative to the applied drain source potentials,
so that the potential across the channel region is lowered compared to the terminal potential drop.
This reduces the lateral electric field, and therefore the carrier velocity, and hence reduces the
susceptibility to hot carrier effects.
Figure 28.6: LDD structure
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142
28.6 Electrostatic discharge (ESD)

Electrostatic discharge refers to the exchange of carriers between two bodies through ionization
of a connecting medium. This process is driven by the nature of conductive bodies to equalize their
potentials. Charge transfer directly onto the gate of a MOSFET can be catastrophic, since the gate
oxide is very thin. Due to a number of possible mechanisms such as voids, local crystal (as opposed
to the normal amorphous) structure formation, contaminants or precipitates, the silicon dioxide
commonly used for MOSFET gate insulation will only function up to a certain maximum level of
electric field. Past this maximum level the oxide structure will change and allow conduction, which is
referred to as dielectric breakdown. The corresponding electric field is referred to as the breakdown
field, Ebreak.
Example 28.1:
A MOSFET has W = 10.0 m, L = 1.0 m and tox= 20 nm. If the maximum gate oxide field is 500 V/cm,
what is the maximum charge (F) allowed on the gate?
Solution:
The potential corresponding to the maximum field is found using tox to be V = 50020x10-3 = 10 V. C ox has
already been calculated previously, so applying Q = CV with gate area scaling
QG = 101.73x10-710x10-41x10-4 = 172.6x10-15 C = 172.6 fC
Since very little charge is normally required on the gate to cause gate oxide damage, many
precautions are taken in the manufacturing environment to reduce the possibility of static buildup by
grounding as many surfaces as possible. On-chip techniques are also used to reduce the chance of
static damage. Input protection circuits such as the simple example shown in Figure 28.7(a) are used
to protect sensitive inputs that may be connected to MOSFET gates. The circuit works by introducing
current limiting resistors and diodes into the input path. If a static discharge event raises the potential
of the input pad higher than VDD or lower than VSS, one of the diodes will conduct and shunt the
charge away to a supply. The resistors limit the current through the diodes or to the sensitive circuit
node.
(a) Input protection
(b) Chip protection circuitry
Figure 28.7: Protection from static discharge
In most commercial designs, the protection circuitry is built into a standard pad configuration that
also includes VDD and VSS supply lines. As shown in Figure 28.7(b), these pad layouts are simply
butted together in the required numbers, and the power connections are made automatically. The
protection and possibly driver circuitry in the interior part is connected directly to the supply lines.
143

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ELEC 3908 - Physical Electronics

Instructor: Steven McGarry

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II Sample Problems ................................................................................................................ 144

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Problems ....................................................................................................................... 163

III Solutions to Sample Problems ...................................................................................... 181

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Chapter 1 Review of Basic Diode Theory

A diode, or pn-junction, is a device constructed from regions of p and n-type semiconducting

Figure 1.1: Diode symbol

Review of Basic Diode Theory

(a) Forward and reverse bias.

(b) Reverse bias only.

(c) Log axis

Figure 1.2: Plots of the simple ideal diode characteristic

sides of (1.1) with VD 3kT q yields:

characteristic is projected back to the VD origin,

(a) Enlargement of VD0

(b) Projection of linear portion

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IS = 1012 A . What is the error in VD compared to VD 0.7 V for ID = 10 mA ? What is

For ID = 10 mA, (1.1) is rewritten to give

kT " ID % 1.379 1023 300 " 102 %

The error is approximately 18%. If VD = 0.7 V is assumed,

Each characteristic will cease to be linear above some value of VD.

Review of Basic Diode Theory

Again, the data in Figure 1.4 suggests some observations

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Atomic Shells, Subshells and Orbitals

Figure 2.1: Atomic shell diagram

Figure 2.2: Atomic orbital geometries

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Figure 2.4: Energy level splitting of valence electrons to form a band.

Figure 2.5: Molecular-orbital energies corresponding to delocalization of valence electrons over

Figure 2.6: Molecular-orbital energies corresponding to delocalization of valence electrons over

Figure 2.7: Energy band formation with increasing numbers of Si atoms.

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Figure 2.8: Band and electron relationship of materials

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Figure 2.10: Zincblende bonding structure of III-V or II-VI semiconductors

Figure 2.11: Diamond bonding structure of Group IV semiconductors

Group IV Semiconductor Bands

Carbon (C) Insulator (Eg 5.5eV)

Figure 2.12: Bonding and band formation in Group IV semiconductors

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Chapter 3 Energy Band Diagrams and Doping

Energy Band Diagrams

(c) Energy band diagram

(d) Electron transitions

Figure 3.1: Energy levels and the energy band diagram

Energy Band Diagrams and Doping

Figure 3.2: Valence to conduction band transitions on an orbital bonding model.

Figure 3.3: Conduction electrons

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Donor Doped Material

(a) Orbital model.

(b) Bonding model.

Figure 3.4: Representations of donor doping.