A

Summer TrainingReport
ON

VLSI Design & Embedded System

(VDES-2016)
Submitted by

Rahul Srivastava

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MOTILAL NEHRU NATIONAL INSTITUTE OF TECHNOLOGY Allahabad
ALLAHABAD, 211004, INDIA

Motilal Nehru National Institute of Technology

Allahabad
Department of Electronics and Communication Engineering

CERTIFICATE

This is to certify that Mr. Rahul Srivastava of Motilal Nehru National Institute of
Technology, Allahabad has participated in summer training programme on VLSI Design
& Embedded System (VDES-2016)at Motilal Nehru National Institute of Technology
Allahabad, organized by Department of Electronics and Communication Engineering from
15th June to 13th July 2016. The conduct of participant during the course was good.

Date:13-07-16

Course Coordinator

Place: Allahabad

(VDES 2016)

MNNIT, Allahabad

II

Acknowledgement
Engineering is not only a theoretical study but it is a implementation of all we study for creating something
new and making things more easy and useful through practical study. It is an art which can be gained with
systematic study , observation and practice. In the college curriculum we usually we get the theoretical
knowledge.
Along with a B.Tech degree , it is necessary to construct a bridge between the educational life and the
industry . I consider myself extremely fortunate to obtain the opportunity to be assigned the Project. I would
like to this opportunity to convey my sincere gratitude to Prof. V.K. Srivastava (HOD ECE department), Er.
Vadithya Narendar and Dr. Santosh Kumar Gupta , MNNIT Allahabad those who helped me to materialize
this project.
I sincerely thank VDES lab trainers , MNNIT Allahabad specially Mr. Aman Jain , Ms. Shreyashi Jaiswal ,
and Mr. Rupesh Shukla for assigning me the project and encouragement in carrying out the project
throughout.

I also thank my colleagues who helped me throughout the project. I enjoyed my time with

them and look forward to working with them again . Thanks all who have been associated with me some
way or the other.

Date : 13-07- 2016

Rahul Srivastava

Place: Allahabad

III

ABSTRACT
The first project that I have implemented is on Light intensity measurement on Microelectronica Kit
through an IC (TSL230 BR) which generates square wave frequency proportional to intensity. Accurate and
quantifiable measurement of light is essential in creating desired outcomes in practical day to day
applications as well as unique applications. From measuring the amount of light in a work space surface to
ensuring emergency exits have proper illumination, light measurement and analysis is an important step in
ensuring efficiency and safety.

In the second section of this report, FPGA based design of UART is implemented using FPGA kit.
The UART consists of two independent HDL modules. One module implements the transmitter, while the
other module implements the receiver. The transmitter and receiver modules can be combined at the top
level of the design, for any combination of transmitter and receiver channels required.
Data can be written to the transmitter and read out from the receiver, all through a single 8 bit bi-directional
CPU interface.

IV

TABLE OF CONTENTS

NO.

TOPICS

PAGE
NO.

1.

PROJECT 1 : Light Intensity measurement

1.1

Introduction

1.2

About the Project

1.3

Result and the Output

11

1.4

Conclusion

12

2.

PROJECT 2 : FPGA based UART design and

implementation

13

2.1

Introduction

13

2.2

About the Project

15

2.3

Result and the Output

20

2.4

Conclusion

23

3.

APPENDIX

24

LIST OF FIGURES
NO.

FIGURE

PAGE NO.

1.1

Microcontroller Architecture

1.2

Functional block diagram

1.3

Light to frequency additional board

1.4

Back of the light to frequency additional board

1.5

Light to frequency additional board schematic

diagram

10

1.6

Snapshot of the project implemented

11

2.1

Basic layout of UART

13

2.2

UART module

14

2.3

UART block diagram

15

2.4

Digital data UART format

16

2.5

Sequence of transmitter

16

2.6

Reciever module

17

2.7

Basic operation of receiver

18

2.8

Synchronizing of rxclk to centre point of start bit

18

2.9

RS-232 connector

19

2.10

Overview of UART and RS-232

19

2.11

Block diagram of transmitter module

20

2.12

Implementation of transmitter

20

2.13

Output

21

2.14

Block diagram of reciever module

21

2.15

Implementation of receiver

22

2.16

Output

22

PROJECT 1 LIGHT INTENSITY MEASUREMENT

1.1 Introduction
Waves carry energy, and the amplitude of a wave is generally a measure of how much energy the wave
carries. In the same way, the displacement of a bow string, determines the amount of energy that propels the
arrow. Energy is a positive quantity, so the amplitude is a positive number.

However, scientists don't usually talk about the amplitude of a light wave, since light isn't traveling in some
substance like water or air. Instead they talk about the intensity of the light. Intensity is like brightness, and
is measured as the rate at which light energy is delivered to a unit of surface, or energy per unit time per unit
area. For instance, the intensity of the sunlight on your solar panel, multiplied by the panel's area, would tell
you how much power (energy per unit time) you have available to run your solar water heater.

In doing lighting efficiency work, you need to measure light intensity. You also need to know how to
express light intensity for selecting lamps and for laying out the overall lighting configuration.
Unfortunately, lighting terminology tends to be confusing and somewhat inconsistent. This brief Note
introduces you to the terms that the lighting trade uses to communicate about light intensity, and it points out
which of these terms are important to know.

Lumens
Lumen is the unit of total light output from a light source. If a lamp or fixture were surrounded by a
transparent bubble, the total rate of light flow through the bubble is measured in lumens. Lumens indicate a
rate of energy flow. Thus, it is a power unit, like the watt or horsepower. Typical indoor lamps have light
outputs ranging from 50 to 10,000 lumens. You use lumens to order most types of lamps, to compare lamp
outputs, and to calculate lamp energy efficiencies (which are expressed as lumens per watt).Note that lumen
output is not related to the light distribution pattern of the lamp. A large fraction of a lamps lumen output
may be useless if it goes in the wrong directions.
3

Footcandles and Lux

Footcandles and lux are units that indicate the density of light that falls on a surface. This is what
lightmeters measure. For example, average indoor lighting ranges from 100 to 1,000 lux, and average out
door sunlight is about 50,000 lux.
The footcandle is an older unit based on English measurements. It is equal to one lumen per square foot. It is
being replaced by lux, a metric unit equal to one lumen per square meter. One footcandle is 10.76 lux.
Although footcandles are now officially obsolete, they probably will continue to be used because many
existing light meters are calibrated in footcandles. The general term for lux or footcandles is illuminance.
The general term is sometimes used by lighting engineers, but the units of lux or foot candles are more
commonly used.

You use footcandles or lux to measure the adequacy of lighting on the task. Foot candles and lux relate only
to the task area, not to the lighting equipment or to the geometry of the space. For example, you could create
an illumination level of 100 lux on a surface by using a single spotlight located far away, or by using many
covelights nearby. For energy conservation work in existing facilities, you need a light meter that measures
illuminance in footcandles or lux. You will use it continually as you lay out lighting, select fixtures to be
delamped, etc. Lightmeters have become inexpensive, so you can afford to spend the money to get a rugged
electronic unit of good quality, rather than the older type that uses a fragile meter movement. Figure 1 shows
a foot candle meter.

Candlepower
Candlepower is a measure of lighting concentration in a light beam. It is used primarily with lamps that
focus, such as spotlights and PAR lamps. In lamps where candlepower is specified, the candlepower rating
usually applies only to a small spot in the center of the beam.
4

The official unit of candlepower is the candela, which is equal to one lumen per steradian . (A steradian is
a fraction of the surface area of a sphere that is equal to the square of the radius divided by the total surface
area. This is approximately 8% of the total surface area.)This term is rarely used in practical work. Lamp
catalogs usually list candlepower rather than candelas. This is like using horsepower as both a general
term and a specific unit. To confuse matters further, candelas were earlier called candles.

Brightness
In general, brightness is an expression of the amount of light emitted from a surface per unit of
area.Brightness is not an official term of the lighting trade, and lighting designers may become huffy when
you use it. However, the concept is essential for understanding visual quality, especially in relation to
contrast and glare. Brightness does not inherently relate to lamps, or even to light sources. The light could be
reflected or transmitted. For example, the bright surface could be the surface of a fluorescent tube, a page of
a book, a window with a view of the sky, or a store window with reflections.
The closest official term is luminance, which is expressed as candelas per square meter of light emitting
surface. (Luminance used to be measured in foot lamberts, which is now an obsolete term.) For example,
the luminance of a heavily overcast sky is about1,000 candelas per square meter, and the luminance of a
typical frosted light bulb is about 100,000 candelas per square meter. Luminance is defined in terms of the
direction of light emission. The details get technical, and you probably will not need to deal with them. In
brief, the brightness of an object usually depends on the direction from which you look at it.
Note that luminance has nothing to do with size of the light emitting surface. The light source could be as
small as a lamp filament, or it could be as large as the whole sky, or it could be a task area, such as a desk
top. Measuring brightness (luminance) is tricky and requires specialized equipment. For practical work,
learn how to avoid excessive brightness, so you wont need to measure it. If you do a good job of laying
outlighting, people within the space will not be subjected to brightness that is severe enough to cause glare
.Luminance is the converse of illuminance. The former describes the intensity of light that is leaving a
surface, whereas the latter describes the intensity of light that is falling on a surface. For light reflected from
5

a surface, luminance equals illuminance multiplied by the percentage of reflectance.Brightness also is

used to describe the subjective sensation of light intensity. This sensation largely depends on the overall
layout of the scene surrounding the viewer. An uncomfortable level of brightness is described as glare.

1.2 About the Project

8051 Microcontroller
The 8051 microcontroller is an 8-bit microcontroller introduced by Intel Corporation. this microcontroller
has 128 bytes of Random Access Memory(RAM), 4K bytes of on-chip Read Only Memory(ROM), two
timers, one serial port and four port(each 8-bits wide) all on a single chip. The Central Processing Unit
(CPU) can work only on 8-bit of data at a time. The 8051 has four I/O ports, each 8- bits wide.

Fig.1.1 : Microcontroller Architecture

The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex instruction set
computing (CISC) instruction set, single chip microcontroller (C) series developed by Intel in 1980 for use
in embedded systems.[1] Intel's original versions were popular in the 1980s and early 1990s and
enhanced binary compatible derivatives remain popular today.
Intel's original MCS-51 family was developed using N-type metal-oxide-semiconductor (NMOS)
technology like its predecessor Intel MCS-48, but later versions, identified by a letter C in their name (e.g.,

80C51) used complementary metaloxidesemiconductor (CMOS) technology and consume less power than
their NMOS predecessors. This made them more suitable for battery-powered devices.
The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/16/32-bit MCS-251 family of
binary compatible microcontrollers.[2] While Intel no longer manufactures the MCS-51, MCS-151 and MCS251 family, enhanced binary compatiblederivatives made by numerous vendors remain popular today. Some
derivatives integrate a digital signal processor (DSP). Beyond these physical devices, several companies also
offer MCS-51 derivatives as IP cores for use in field-programmable gate array (FPGA) orapplicationspecific integrated circuit (ASIC) designs. ROM of 4KB and RAM of 128 bytes

TSL 230 BR
The TSL230 light-to-frequency converter combines a silicon photodiode and a current-to-frequency
converter on a single monolithic CMOS integrated circuit. The output is a square wave (50% duty cycle)
with frequency directly proportional to light intensity. Because it is TTL compatible, the output allows direct
interface to a microcontroller or other logic circuitry. The device has been temperature compensated for the
ultravioletto-visible light range of 300 nm to 700 nm and responds over the light range of 300 nm to 1100
nm. The TSL230 is characterized for operation over the temperature range of 25C to 70C.

Fig.1.2 : Functional Block Diagram

Light to Frequency Additional Board

The Light to Frequency additional board is used to convert light into pulse train (frequency) which is
directly proportional to light intensity reaching the TSL230BR light sensor. The additional board is
connected to a development system via a 2 x 5 connector supplied on the board and one of 2 x 5 connectors
8

supplied on the development system`s I/O ports. Which of the ports is to be used for connection solely
depends on the user`s program loaded into the microcontroller. Jumpers S1 and S0 are used to select the
sensor`s light sensitivity, whereas jumpers S3 and S2 are used to scale frequency on the light`s sensor`s
output pin.

Fig.1.3 : Light to Frequency Additional Board

Fig. 1.4 : Back of the Light to Frequency Additional Board

Fig. 1.5 : Light to Frequency Additional Board Connection Schematic

Measuring the frequency

The choice of interface and measurement technique depends on the desired resolution and data-acquisition
rate. For maximum data-acquisition rate, period-measurement techniques are used. Period measurement
requires the use of a fast reference clock with available resolution directly related to reference-clock rate.
The technique is employed to measure rapidly varying light levels or to make a fast measurement of a
constant light source. Maximum resolution and accuracy may be obtained using frequency-measurement,
pulse-accumulation, or integration techniques. Frequency measurements provide the added benefit of
averaging out random- or high-frequency variations (jitter) resulting from noise in the light signal.
Resolution is limited mainly by available counter registers and allowable measurement time. Frequency
measurement is well suited for slowly varying or constant light levels and for reading average light levels
over short periods of time. Integration, the accumulation of pulses over a very long period of time, can be
used to measure exposure the amount of light present in an area over a given time period.

10

1.3 Result and the output

Fig. 1.6 : Snapshot of the Project implemented

Sensitivity bits (s1, s0) = (L, H)

Intensity of room with light = 165.31
Intensity of room without lights = 1.675
Sensitivity bits (s1, s0) = (H, L)
Intensity of room with lights = 16774.87
Intensity of room without lights = 102.675
Sensitivity bits (s1, s0) = (H, H)
Intensity of room with light = 1729.43
Intensity of room without lights = 11.675
Scaling bit (s3, s2) = (L, L)
Intensity of room with light = 165.31
Sensitivity bits (s1, s0) = (L, H)
Intensity of room with light = 19.64
11

1.4 Conclusion

With the help of relation, measured intensity of light is proportional to current flowing through photodiode
which is in turn proportional to frequency of square wave generated by light to frequency converter IC, we
have obtained the desired result.
Frequency of desired square wave corresponding to same light intensity can be observed to be changing in
accordance with sensitivity and scaling.

12

PROJECT 2 FPGA based UART design and Implementation

2.1 Introduction
Address mapping for the transmitter and receiver channels can easily be built into the interface at the top
level of the design. Both modules share a common master clock called mclkx16. Within each module,
mclkx16 is divided down to independent baud rate clocks.

Fig. 2.1 : Basic UART Layout

BAUD RATE GENERATOR of UART:

From one UART device to the other. The Baud count includes the overhead bits Start, Stop and Parity that
are generated by the sending UART and removed by the receiving UART. This means that seven-bit words
of data actually take 10 bits to be completely transmitted.
Baud Rate =Clock Frequency/ (Sampling Rate) * (Divisor)

13

Fig. 2.2 : UART Module

Baud Rate Generator specifies the rate at which transmission or reception should happen. During
transmission the data is shifted out to Tx line at Baud Rate and in reception data on Rx line is sampled at
baud rate. It is configurable with 8 bit latch registers (DLL and DLH) to different baud rates.
Divisor (decimal) = (clock frequency) / (baud rate x clock sampling rate)

14

2.2 About the Project

A basic overview of the UART is shown below. At the left hand side is shown the transmit hold register,
transmit shift register and the transmitter control logic blocks, all contained within the transmitter
module called txmit. At the right hand side is shown the receive shift
register, receive hold register and the receiver control logic blocks, all contained within the receiver
module called rxcver. The two modules have separate inputs and outputs for most of their control lines,
only the bi-directional data bus, master clock and reset lines are shared by
both modules. Smaller functions, such as combinatorial logic synthesized from HDLs, are mapped in
parallel into independent fragments, providing high gate utilization without sacrificing performance. Related
and unrelated functions can be packed into the same logic cell, increasing effective density and gate
utilization.

Fig. 2.3 : RECEIVER MODULE

15

The two subsystems involved in communication are interfaced to UART module. They operate at
different clock frequencies other than UART. Serial data are contained within frames of 8 data bits, as well
as coded information bits. Between successive transmissions, the transmission line is held high. A
transmission is initialized by a leading low start bit. Next to the leading low start bit comes 8 bits of data
information, beginning with the LSB and ending with the MSB. After the 8 data bits comes the parity bit,
representing the parity result of the 8 data bits. The parity bit can be set true based on even parity or odd
parity mode. Next to the parity bit comes a trailing high stop bit indicating the end of a data frame.

Fig. 2.4 : Digital UART Data Format

The transmitter waits for new data to be written to the module. When new data is written a transmit
sequence is initialized. Data that was written in parallel to the module gets transmitted as serial data frames
at the tx output. When no transmit sequences are in place, the tx output is held high.

Fig. 2.5 : Sequence of Transmitter

16

We have now covered all necessary declarations, and are ready to look at the actual implementation. Using a
hardware description language allows us to describe the function of the transmitter in a more behavioral
manner, rather than focus on its actual implementation at the gate level.
In software programming languages, functions and procedures break larger programs into more readable,
manageable and maintainable pieces. The Verilog language provides functions and tasks as constructs,
analogous to software functions and procedures.

A Verilog function and task are used as the equivalent

to multiple lines of Verilog code, where certain inputs or signals affect certain outputs or variables. The use
of functions and tasks usually takes place where multiple lines of code are repeatedly used in a design, and
hence makes the design easier to read and maintain. A Verilog function can have multiple inputs, but always
only one output, while the Verilog task can have both multiple inputs and multiple outputs and even in some
cases, neither.
The master clock mclkx16 is divided down to the proper baud rate clock called rxclk, and equals to
mclkx16/16. Serial data to be received at the rx input of the module. Data received in serial format can be
read out in parallel format, through the 8 bit data bus.

Fig. 2.6 : RECEIVER MODULE

Between successive transmissions, the transmission line is held high, according to standard UART behavior.
The receiver waits in idle mode for the rx input to go low. At the falling edge of rx the receiver enters
hunt mode, searching for a valid start bit of a new data frame to be received. If a valid start bit is detected,
the receiver enter shift data mode. If an invalid start bit is detected, the receiver returns to idle mode.
17

During reception of a data frame, various parity and error checks are performed. When a complete data
frame has been received the receiver returns to idle mode.

Fig. 2.7 : THE BASIC OPERATION OF RECEIVER

The frequency of rxclk is equal to mclkx16/16, and the first rising edge of the rxclk will always occur at the
center point of the start bit. Figure 14 below shows how generation of the baud rate clock rxclk is
synchronized to the center points of the start bit and the following data bits.

Fig. 2.8 : SYNCHRONIZING RXCLK TO CENTRE POINT OF START BIT

RS-232 connector:
The J3 connector provides a standard RS-232 connection.
The pins of J3 are directly connected to the FPGA, allowing an internal implementation of the serial
controller.
It's possible to implement two UART without hardware handshaking.

18

Fig. 2.9 : RS-232 Connector

Fig. 2.10 : Overview of UART and RS-232 Connector

19

2.3 Result and the output

(A) TRANSMITTER

Fig. 2.11 : Block Diagram of Transmitter Module

Fig. 2.12 : Implementation of Transmitter

20

This figure is observed by connecting the kit with Hyper Terminal.

Fig. 2.13 : OUTPUT

(B) RECEIVER

Fig. 2.14 : Block Diagram of RECEIVER MODULE

21

Fig. 2.15 : Implementation of RECIEVER

Data is transmitted through Hyper Terminal and it is displayed on LEDs of FPGA kit.

Fig. 2.16 : OUTPUT

22

2.4 Conclusion

We designed the UART consisting of baud rate generator, transmitter and receiver modules on XILINX
ISE using code in Verilog language.
We successfully implemented this design on Spartan 3E kit.

23

APPENDIX A
PROGRAM CODE for Embedded Project on Light to Frequency Converter
sbit LCD_RS at P2_0_bit;

// register select line

sbit LCD_EN at P2_1_bit;

//setting P2.1 as

sbit LCD_D4 at P2_2_bit;

//setting P2.2 as data 4 line

sbit LCD_D5 at P2_3_bit;

// ,,

P2.3 ,,

,,

5 ,,

sbit LCD_D6 at P2_4_bit;

sbit LCD_D7 at P2_5_bit;

int count_pulse = 0,count_time = 0,count_t0 = 0;

// declaration and initialization of variables

float freq = 0;
char txt[10];
void main() {
LCD_Init();

// initializing the needed components of lcd Display

LCD_Cmd(_LCD_CLEAR);

// clearing any previous text from lcd

screen
LCD_Cmd(_LCD_CURSOR_OFF);

// for getting the blinking cursor disappear from the lcd

screen
TCON.TR0 = 1;

// setting timer 0 run control bit =1

24

TCON.TR1 = 1;

//setting timer1 run control bit =1

TMOD = 0x15;
IE.B7 = 1;

// setting TMOD register

// setting 7th bit of Interrupt Enable register

IE.B1 = 1;
IE.B3 = 1;
TCON.IT0 = 1;
TCON.IT1 = 1;
P3_0_bit=0;
while(1)
{

count_pulse = (count_t0)*(65536) + TH0*256 + TL0 ;

if(count_pulse > 8 & count_time > 0)
{
LCD_Cmd(_LCD_CLEAR);

// clearing any previous text from lcd screen

freq = (count_pulse/(0.786432*count_time));
count_t0 = 0;
count_time = 0;
TCON.TF0 = 0; TH0 = 0x00; TL0 = 0x00;

//setting timer overflow flag of timer 0

TCON.TF1 = 0; TH1 = 0x00; TL1 = 0x00;

FloatToStr(freq,txt);

// conversion of a quantity in float type to string type

LCD_Out(1,1,"INTENSITY = ");

// getting INTENSITY printed in 2 x 16 LCD at position (1,1)

25

LCD_Out (2,1,txt);

/* getting

the value of INTENSITY stored in the variable txt

printed at position (2,1) on LCD */

}
}
}
void timer0() org 0x000B

// the interrupt TIMER0

{count_t0 = count_t0 + 1;}

void timer1() org 0x001B

// the interrupt TIMER1

{count_time = count_time + 1;}

26

APPENDIX B
PROGRAM CODE for Verilog Project on UART implementation
Transmitter Module
`timescale 1ns / 1ps

// specifying delay unit

module transmitter(input in, reset, clk, en, output reg [7:0] data,
output reg txparity
);

// creating module transmitter

// declaration of various variables

reg [7:0]data;
reg [7:0]thr;
reg [3:0]cnt;
reg txfull,parity;
wire oclk;
clkgen txclk(clk,oclk);

initial

// calling the module clkgen for frequency division

//beginning of initial block

begin
data <= 65;
data <= 1;
txfull <= 0;
cnt <= 0 ;
txparity <= 0;
parity <= 0;

27

end

// end of initial block

always@(posedge oclk or posedge reset)

//event list of always block

begin
if(reset)
begin
data <= 1;
txfull <= 0;
cnt <= 0;
txparity <= 0;
parity <= 0;
end
else
begin
if(in)
begin
if(txfull!=1)
begin
thr<=data;
txfull<=1;
end
end
if(en & txfull)
begin
cnt<=cnt+1;
if(cnt==0)
begin
data<=0;
end
28

if(cnt>0 & cnt<9)

begin
data<=thr[cnt-1];
parity<=parity^data;
end
if(cnt == 9)
begin
data <= 1;
txfull <= 0;
cnt <= 0;
txparity<=parity;
end

end
end
end
endmodule

module clkgen(clk,oclk
);

// clkgen module begins

reg [16:0]div2;output oclk;input clk;

initial begin div2=0;end

always@(posedge clk)

div2<=div2[15:0]+151;
wire oclk=div2[16];

endmodule

// end of clkgen module

29

Reciever Module

`timescale 1ns / 1ps

// specifying delay unit

module
jaimatadi(clk,rxclk,rxcnt,rxsamplecnt,rst,in,readdata,rxdata,rxen,rxparity,rx_completed,framingerr,d2
);
// declaration of various variables begins
input clk,readdata,rxen,rst,in;
output reg [7:0]rxdata;
output reg rxparity=0,rx_completed,framingerr;
output d2;
reg d2,rxbusy;
output reg [3:0]rxcnt;
output reg [5:0]rxsamplecnt;
output rxclk;
reg [7:0]rxhdr;//rx hold reg
divclk1 oversamplingclk(clk,rxclk);
//rxen allows the input from transmitter to be stored in rxhdr

initial
begin
rxparity<=0;
rx_completed=0;
framingerr<=0;
rxcnt=0;
rxsamplecnt<=0;
30

rxbusy=0;
rxhdr<=0;
rxdata<=0;
d2=1;
end

always@(posedge rxclk or posedge rst)

begin
if(rst)
begin
rxparity<=0;
rx_completed=0;
framingerr<=0;
rxcnt=0;
rxsamplecnt=0;
rxbusy=0;
rxhdr<=0;
rxdata<=0;
d2=1;
end

else
begin

d2=in;
if(rxen)
begin
if( d2 ==0 && rxbusy ==0)
begin
31

rxbusy=1;
rxcnt=0;
rxsamplecnt=16;
rx_completed=0;
end
if(rxbusy)
begin
//if((rxcnt==0)
rxsamplecnt=rxsamplecnt+1;
if(rxsamplecnt%16==7)
begin
rxsamplecnt = rxsamplecnt - 16;
if((d2==1)&&(rxcnt==0))
rxbusy=0;
else
begin
if(rxcnt > 0 && rxcnt < 9)
begin
rxhdr[rxcnt-1]<=d2;
rxparity<=rxparity^d2;
end
if(rxcnt==9)
begin
if(d2==0)
framingerr<=1;

else
begin
framingerr<=0;
32

rxbusy=0;
rx_completed=1;
end
end
rxcnt=rxcnt+1;
end
end
end
end
if(readdata & rx_completed)
begin
rxdata<=rxhdr;
end

end
end

endmodule

module divclk1(clk,oclk
);
reg [12:0]div;
output reg oclk;
input clk;

initial
begin
div=0;
33

oclk=0;
end

always@(posedge clk)
begin
div <= div[11:0]+151;
oclk = div[12];
end
endmodule

34

35