3670

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 10, OCTOBER 2008

Optimal Predictive Control of Three-Phase NPC

Multilevel Converter for Power
Quality Applications
J. Dionsio Barros, Student Member, IEEE, and J. Fernando Silva, Senior Member, IEEE

AbstractThis paper presents the optimal control of the ac

currents, the dc voltage regulation, and the dc capacitor voltage
balancing in a three-level three-phase neutral point clamped multilevel converter for use in power quality applications as an active
power filter. The ac output currents and the dc capacitor voltages
are sampled and predicted for the next sampling time using linearized models and considering all the 27 output voltage vectors.
A suitable quadratic weighed cost function is used to choose the
voltage vector that minimizes the ac current tracking errors, the
dc voltage steady-state error, and the input dc capacitor voltage
unbalancing. The obtained experimental results show that the output ac currents track their references showing small ripple, a total
harmonic distortion (THD) of less than 1%, harmonic contents
that are 46 dB below the fundamental, and almost no steady-state
error (0.3%). The capacitor voltages are balanced within 0.05%,
and the balancing is assured even when redundant vectors are not
chosen. Near-perfect capacitor dc voltage balancing is obtained
while reducing current harmonic distortion. Some experimental
evidence of robustness concerning a parameter variation was
also found, with the optimum controller withstanding parameter
deviations from +100% to 50%. Compared to a robust sliding
mode controller, the optimal controller can reduce the THD of the
ac currents or reduce the switching frequency at the same THD,
being a suitable controller for power quality in medium-voltage
applications.
Index TermsActive power filters (APFs), multilevel converter,
neutral point clamped (NPC), power quality, predictive control.

I. I NTRODUCTION

ULTILEVEL converters are designed to evenly inherently share the total dc voltage between cascaded power
semiconductors [1][3]. Therefore, compared to a two-level
converter topology, they are the most suitable power converters
for high-voltage high-power applications [1][14] despite dc
voltage balancing problems and complex modulation [7], [10],
[11], [15][18].

Manuscript received July 25, 2007; revised June 10, 2008. First published
July 9, 2008; current version published October 1, 2008. This work was
supported in part by the Centro de Cincia e Tecnologia da Madeira, in part
by the Fundo Social Europeu, in part by the Programa Operacional Plurifundos
da Regio Autnoma da Madeira, and in part by the Fundao para a Cincia
e a Tecnologia-Fundo Europeu de Desenvolvimento Regional (FCT-FEDER)
Project POSC/EEA-ESE/60861/2004.
J. D. Barros is with the Department of Mathematics and Engineering,
University of Madeira, 9000-390 Funchal, Portugal (e-mail: dbarros@uma.pt).
J. F. Silva is with the Department of Electrical and Computer Engineering,
Instituto Superior Tcnico, Technical University of Lisbon, 1049-001 Lisbon,
Portugal (e-mail: fernandos@alfa.ist.utl.pt).
Digital Object Identifier 10.1109/TIE.2008.928156

There are several multilevel converter topologies available,

with the neutral point clamped (NPC) [1], the flying capacitor
[2], and the cascaded H-bridge [3] the most studied and used
[10], [14]. Among these, the three-phase three-level NPC converter is the most widely used despite some difficulty of neutralpoint voltage balancing [7], [10], [13], [16].
Pulsewidth modulation (PWM) and space vector modulation
(SVM) are the most common control techniques used in multilevel power converters [19], [20]; however, controlled outputs can be affected by power semiconductor switching times.
Control methods for multilevel converters based on hysteresis
comparators, or sliding mode approaches, are robust to model
components and semiconductor switching times, and present a
zero steady-state error; however, they need a variable switching
frequency that is higher than those of the SVM and the PWM
to obtain similar performance [11], [19], [20].
Optimal predictive controllers are based on the linear optimal
control system theory that aims to solve the minimization problem of a cost function [5], [15], [21][27]. Therefore, predictive
controllers can be tailored to minimize system output errors, at
a given sampling frequency, being suitable in the simultaneous
control of currents and voltages with coupled dynamics. Predictive control is a very wide concept, and different approaches
are being applied to power converters with improved results
compared to standard modulation techniques [5], [21], [22],
[27][31].
Predictive controllers can be real-time-implemented in
software-based platforms using a fixed sampling frequency and
microprocessors [20]. Powerful and fast microprocessors are
readily available, allowing the design of high-performance realtime controllers for power electronic converters to optimize
the onoff duty ratios of the power switches and achieve the
desired high-quality performance and a very low total harmonic
distortion (THD) [24], [32].
The current control of the multilevel three-phase converters
is one of the most important and classical subjects in power
electronics and has been studied in the last decades [4], [5],
[11], [13][15], [17], [18], [21], [22], [27][31], [33]. Nowadays, it is still a very important topic of research, particularly
for applications to improve power quality, which demands the
use of converters that are able to strongly reduce the ac current
or voltage distortion and/or increase the power factor [33][37].
Multilevel-converter-based active power filters (APFs) have
potential applications in medium-voltage networks to mitigate
harmonics and/or to increase the power factor since the power
factor can be continuously adjustable, not dependent on the

0278-0046/$25.00 2008 IEEE

BARROS AND SILVA: PREDICTIVE CONTROL OF NPC MULTILEVEL CONVERTER

Fig. 1.

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NPC multilevel converter circuit, working as an active power filter.

square of the medium-voltage value, and parallel resonance

free, which are properties that are well beyond traditional
capacitive power factor compensation [36], [37].
Therefore, Section II presents the multilevel-converter-based
APF modeling. Section III deals with the optimal control of ac
currents, dc capacitor voltage regulation, and their balancing
in a three-level three-phase NPC multilevel converter APF to
choose the optimal vector to enforce the reference output ac
currents and the constant dc reference voltage, and to simultaneously balance the dc capacitor voltages. The performance
shown in Section IV of the proposed real-time optimal predictive controller for the multilevel APF is compared to that of
the robust sliding mode vector control, which uses the multilevel NPC converter redundant vectors to balance dc capacitor
voltages [11].
II. M ODELING M ULTILEVEL APF
The NPC multilevel APF (Fig. 1) can be controlled to compensate the power factor and the ac line iLk current harmonics
introduced by nonlinear loads (the three-phase bridge rectifier
in Fig. 1). The NPC multilevel ac side is shunt-connected to
the electrical network voltages UL1 , UL2 , and UL3 using three
inductors L with loss resistor R to inject currents to cancel
the harmonic component currents of the nonlinear load. The dc
voltage Udc must be regulated, and the capacitor voltages UC1
and UC2 must be balanced.
The switching variables k represent the state of the multilevel converter active switches Skj , with k {1, 2, 3} and
j {1, 2, 3, 4}. Assuming ideal semiconductors, the three valid
combinations of the binary states of the switches Skj of each leg
k can be defined as follows:

(Sk1 = 1 Sk2 = 1) (Sk3 = 0 Sk4 = 0)

1
k =
0
(Sk1 = 0 Sk2 = 1) (Sk3 = 1 Sk4 = 0)

1 (Sk1 = 0 Sk2 = 0) (Sk3 = 1 Sk4 = 1).

(1)

Assuming that a suitable control system balances the capacitor voltages UC1 and UC2 , with UC1 UC2 Udc /2, the
voltage umk between each leg and the neutral point of the
multilevel converter is given by
umk = k

Udc
.
2

(2)

A. Switched State-Space Multilevel APF Model

Applying the Kirchhoff laws to the multilevel converter APF
(Fig. 1), the dynamic equations (3) of the ac line currents iL1 ,
iL2 , and iL3 and the capacitor voltages UC1 and UC2 can be
written as functions of the circuit parameters and k , i.e.,
diL1 R
L
dt
didtL2 0
di
L3 = 0
dt
dUC1 11
C1
dt
dUC2
21

dt
C2

L1
0

+
0
0
0

R
L
0

+
0
11
C1
C212

0
R
L
0
C121
C222
0
L1
0
0
0

11
L
21
L
31
L

0
0
R
L
C131
C232
0
0
L1
0
0

0
R
L
0
C121
C222

0
0
0
0
0

1
C1
1
C2

0
0
R
L
C131
C232

iL1
iL2

iL3

0 UC1
UC2
0

12
L
22
L
32
L

UL1
UL2

UL3

idc
1 0
0 1
0
0
0
0
0
0

iR1
0
i
0 R2
iR3

1
didtR1

0
diR2
dt
0
diR3

dt

(3)

3672

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 10, OCTOBER 2008

where
k (k + 1)
2
k (1 k )
=
2

1k =
2k

ki =

1
2ik
3

ij .

(4)

j=1
j=k

For ac networks with isolated neutral, these equations can be

simplified using coordinates.

B. Switched State-Space Multilevel System

Model in Coordinates
Fig. 2.

The relationship between the variables X123 (in system

coordinates) and the coordinates X is given by (C is the
ClarkeConcordia transformation matrix)
X123 = CX

1
X1
X2 = 2
21
3
X3
21

2
2
2
2
2
2

3
2
23

Available voltage vectors at the output of the multilevel converter.

i values can be used to plot the 27 vectors of Fig. 2. (The

values of 1 , 2 , and 3 are inside the parentheses.)
C. Switched State-Space Multilevel System
Model in dq Coordinates

X .
X0

(5)

The relationship between the variables X in coordinates and Xdq in dq coordinates is given by the Park transformation, i.e.,

Applying (5) to model (3), the coordinates multilevel

model (6) is obtained, i.e.,

diL
dt
diL
dt
dUC1
dt
dUC2
dt

R
L

0
=
1
C1

0
R
L

C11

i
L
iL

0 UC1
UC2
0

1
L
1
L

2
L
2
L

C22
0
C2
2

0
0
L
UL
1

0
0

+
1 UL
0
0
C1
idc
1
0
0
C2
R
0
1 0 iR
L
R
0
L
0 1 iR
diR
+
1 1
0
0 dt
C1
C1
C2
2

C22

(6)

diR
dt

where
i
i



i3
2
i2

=
i1
3
2
2

 

2
3
3
i2
i3 .
=
3
2
2

X = DXdq
 
X
cos
=
sin
X




Xd
.
Xq

(8)

The argument = t is the angular phase of the electrical

network ac line voltage. Applying the Park transformation (8)
to the multilevel converter model (6), the multilevel converter
APF model (9) in dq coordinates is obtained, i.e.,
1d
2d
diLd R

L
L
L
iLd
dt
1q
2q
R
diLq

L
L
L iLq
dt =

1q
1d
dUC1

0
0 UC1

C1
C1
dt
dUC2

UC2
0
0
2d 2q
dt

C2

L1

0
+
0
0

C2

0
ULd
0

1 ULq
C1
idc
1

0
L1
0
0

C2

R
L

+ 1d
C1

R
L

C1q1

1
0
0

C2d2

C2q2

(7)

This model is suitable to establish the optimal predictive

current controller, and the 27 possible combinations of i and

sin
cos

where

 
id
cos
=
sin
iq

sin
cos




i
,
i

0 iRd
1 iRq
di
0 dtRd
0

(9)

diRq
dt

with i {1, 2}. (10)

BARROS AND SILVA: PREDICTIVE CONTROL OF NPC MULTILEVEL CONVERTER

The dynamic equation of the dc voltage Udc is directly

obtained from (9) since Udc = UC1 + UC2 , i.e.,
dUdc
=
dt

1d
2d
+
C1
C2


iLd


1d
2d
+
iRd
C1
C2


1
1
+
+
idc .
C1
C2

1q
2q
+
C1
C2
1q
2q
+
C1
C2


iLq

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where UCi (ts ) and ULx (ts ) are the sampled voltages. Assuming ix (x {, } and i {1, 2}) as the control input during
T , the dynamic behavior of the ac currents is approximately
iLx (ts+1 ) iRx (ts+1 ) + e L T [iLx (ts ) + iRx (ts )]


1x
2x
ULx (ts )
UC1 (ts ) +
UC2 (ts )
+
L
L
L
R


iRq
(11)

This quasi-linear model of the dc voltage Udc is suitable to

design a linear predictive controller to regulate the dc voltage
of the APF.


R
L
1 e L T .
R

Assuming (R/L)T  1, the exponential function can be

approximated by the first two terms of its Taylor series, i.e.,
R

e L T 1 +

III. O PTIMAL P REDICTIVE C ONTROLLER D ESIGN

The ac current and the dc voltage optimal controllers are
designed to choose the best output voltage vector that is able to
minimize the ac line current iL and iL errors, the Udc voltage
regulation error, and the unbalancing of dc capacitor voltages
UC1 and UC2 . The obtained converter model (6) will be
solved to predict the state variable values at the next sampling
period for all the 27 available vectors.

A. Predictive Equations for AC Line Currents

and DC Capacitor Voltages
The solution of the ac line current iLx , with x {, }, is
given by [23]

iLx (ts+1 ) = iRx (ts+1 )+e

ts+1


R

+ eL

(12)

where iLx (ts ) and iRx (ts ) are the currents iLx (t) and iRx (t) at
the sampling instant ts = kT , respectively, and iLx (ts+1 ) =
iLx (t = (k + 1)T ) is the current to be predicted for the next
(k + 1) sampling interval T . The nonlinear current for the
next sampling interval iRx (ts+1 ) can be estimated from the
sampled value of the previous period T of ac currents, i.e.,
iRx (ts+1 ) iRx (ts+1 T ), that is updated every period T .
Assuming a sampling time T that is small enough, UC1 (ts ),
UC2 (ts ), and ULx (ts ) can all be considered nearly constant
during T (T must be at least ten times smaller than the
minimum period of voltages UC1 , UC2 , and ULx ), i.e.,
UCi ( ) UCi (ts )
ts < t < ts+1

(13)

(15)

R
R
T iLx (ts ) T iRx (ts )
L
L
2x
1x
T UC1 (ts ) +
T UC2 (ts )
+
L
L
T
ULx (ts ).
(16)

L
To predict the capacitor voltage difference UC1 (t) UC2 (t),
the corresponding dynamic equations (6) must be solved. The
solution for the capacitor voltages is given by [23]

UCi (ts+1 ) = UCi (ts ) +

ts

R
T  1.
L

iLx (ts+1 ) iLx (ts ) + iRx (ts ) iRx (ts+1 )

ts+1

iLx (ts )+iRx (ts )

 
1x
2x
ULx ( )
UC1 ( )+
UC2 ( )
d
L
L
L

ULx ( ) ULx (ts ),

R
T,
L

Using (15) in (14), the ac line currents (14) can be predicted

at the next sampling time using the following:


R
L T

(14)

ts

i
i
iL ( )
iR ( )
Ci
Ci

i
idc ( )
i
iL ( )
iR ( ) +
d
Ci
Ci
Ci

(17)

where UCi (ts ) are the sampled capacitor voltages at t = ts =

kT . Assume T to be small enough to consider the dc
current idc (t) and nearly constant, and assume that the ac line
currents follow their references, i.e.,
idc ( ) idc (ts )
iLx ( ) iLx (ts )
iRx ( ) iRx (ts ),

ts < t < ts+1 .

(18)

Substituting (18) into (17) and assuming ix (x {, } and

i {1, 2}) as the control during T , the capacitor voltages are
UCi (ts+1 ) UCi (ts )

i
T iL (ts )
Ci

i
i
T iR (ts )
T iL (ts )
Ci
Ci

i
T
T iR (ts ) +
idc (ts ).
Ci
Ci

(19)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 10, OCTOBER 2008

Considering that C1 C2 C, the capacitor voltage unbalance is predicted to be

UC1 (ts+1 ) UC2 (ts+1 )
T
C
1 )

UC1 (ts ) UC2 (ts ) + (2 1 )

[iL (ts ) + iR (ts )] + (2
T

[iL (ts ) + iR (ts )] .

C

(20)

B. Quadratic Cost Function Definition

If a three-leg NPC multilevel converter is operated as a current source, three independent variables can be controlledtwo
ac line currents iL (t) and iL (t), and the capacitive unbalance UC1 (t) UC2 (t). The main objective of the optimizing
controller must be the minimization of the ac line current
errors and the capacitor voltage difference using the following
suitable quadratic cost function of the tracking errors given in
(22) and (23):

e2 (ts+1 ) e2 (ts+1 ) e2U C (ts+1 )
+
+
(21)
C(ts+1 ) =

U C
where
e (ts+1 ) = iLRef (ts+1 ) iL (ts+1 )
e (ts+1 ) = iLRef (ts+1 ) iL (ts+1 )
eU C (ts+1 ) = UC1 (ts+1 ) UC2 (ts+1 ).

Fig. 3. Feedback system of the multilevel converter APF with a predictive

optimal controller.

D. APF Current Reference Generation

and Power Flow Control
(22)
(23)

iLRef (ts+1 ) and iLRef (ts+1 ) are the ac line current references one sample time forward, i.e., ts+1 , to compensate
for the processor calculation times. In cost function (21), the
errors are weighted by , , and U C for two purposes:
1) they normalize the distinct errors, which have different units
and ranges, and 2) they define the priority level of each error
variable.
To assure the adjacent level voltage transition in the multilevel output leg voltages, only adjacent vectors (needing just
the switching of two semiconductors per leg) are analyzed.
The adjacent vectors must simultaneously verify |k (ts+1 )
k (ts )| < 2, with k {1, 2, 3}, in all legs of the multilevel
converter.
C. Multilevel Converter Optimal Predictive Controller
The block diagram of the multilevel converter with the optimal controller (Fig. 3) includes as inputs the states of the multilevel converter switches (all the vectors to be tested) 1 (ts ),
2 (ts ), and 3 (ts ), the sampled capacitor voltages UC1 (ts )
and UC2 (ts ), the ac line current references one sampling time
forward iLRef (ts+1 ) and iLRef (ts+1 ), and the ac currents
iL1 (ts ), iL2 (ts ), iL3 (ts ), iR1 (ts ), iR2 (ts ), and iR3 (ts ), which
were read and transformed to coordinates iL (ts ), iL (ts ),
iR (ts ), and iR (ts ) using the ClarkeConcordia transformation. The controller makes use of these inputs to compute the
optimal vector to apply it to the multilevel converter at the next
sampling interval.

The generation of the current references for the APF must

assure that the ac line currents are sinusoidal, the power factor
is near unity, and the dc voltage is regulated.
A linear optimal predictive regulator is designed to generate
the ac line current references iLdRef and iLqRef to cancel
the mean value of the dc voltage error eUdc (t) = UdcRef (t)
Udc (t) during the time interval TUdc , i.e.,

1
eUdc (t) =
eUdc (t)dt
TUdc
TUdc

1
TUdc

UdcRef (t) Udc (t)dt = 0.

(24)

TUdc

To obtain a quasi-unity power factor, the ac line current

must be in phase with the ac line voltage, forcing iLqRef = 0.
Using the dynamic equation of the dc voltage [see (11)] in (24),
assuming that the optimal predictive controller forces iLd =
iLdRef and iLqRef = 0, the optimal predictive control law of
iLdRef is obtained, i.e.,
UdcRef C UdcRef (t) Udc (t)
iLdRef (t) iRd (t)
TUdc
6UL

2
UdcRef
L
UdcRef L
iRq (t) +
idc (t) (25)
2
6UL Rdc
6UL

where TUdc is the time interval used to compute the mean value
of the dc voltages Udc and UdcRef , the dc current idc , and
the nonlinear currents iRd and iRq . UL is the ac line voltage
amplitude, and is its fundamental angular frequency. The
time interval TUdc must be much larger than the period T of

BARROS AND SILVA: PREDICTIVE CONTROL OF NPC MULTILEVEL CONVERTER

3675

RL = 10 , Rdc = 10 k, RR = 0.1 , iac = 7 A, UL obtained from 230/400 V through a 400/230-V transformer, fac =
50 Hz (T = 0.02 s and = 314.2 rad/s), TUdc = 2 s, =
0.09 A2 , = 0.09 A2 , and U C = 0.04 V2 .
A. Evaluation of NPC Multilevel
Converter Current Controllers

Fig. 4.

Active power filter current reference generation.

ac line currents (TUdc  T ) to maintain the ac line currents

sinusoidal (the time constant Rdc C is of no concern since Rdc
represents the safety discharging resistors of the capacitors;
TUdc  Rdc C). In (25), the switching variables 1d + 2d
and 1q + 2q are given by the following and were similarly
obtained as in [38]:

6UL
1d + 2d
UdcRef
2LUdcRef
1q + 2q
.
6UL Rdc

(26)

In the feedback controller system of the APF, the dc voltages

Udc and the currents idc , iR1 , iR2 , and iR3 are sampled to
generate the ac line current references (Fig. 4), which are
applied to the optimal predictive controller of the multilevel
converter (Fig. 3) to force the ac line currents to follow its
references.
IV. S IMULATION AND E XPERIMENTAL R ESULTS
The multilevel converter model and the optimal controller
were implemented in the MATLAB/Simulink, as shown in
Figs. 3 and 4. The dynamic equations of the system model (3),
the ac line currents iL1 (t), iL2 (t), and iL3 (t), and the capacitor voltages UC1 (t) and UC2 (t) were implemented in the
simulation program. Ideal switches were considered. The optimal predictive controller was implemented in a MATLAB
S-Function. To experimentally validate the simulations, a lowpower (3 kW) laboratorial prototype was built, according
to Figs. 1, 3, and 4, with insulated-gate bipolar transistors
(IGBTs; MG50Q2YS40), diodes (STTA5012TV1), capacitors,
inductors, resistors, IGBT drives with optical isolation (IR2110
together with optocouplers HCPL-2200), sensors to read the
currents iL1 (t), iL2 (t), iR1 (t), iR2 (t), and idc (t) (Hall effect
LEM LA25NP), and sensors to read voltages UC1 (t) and
UC2 (t) (isolation amplifier AD210AN). To determine the optimal vector, the algorithm is implemented in a digital signal
processor PowerPC-based board (DS1103), which is programmed in C language (T ranging from 28 s to 1 ms).
The following parameters were used: C1 = 4.4 mF, 200 V,
C2 = 4.4 mF, 200 V (Udc max < 300 V to have a 25% safety
margin), CL = 1 mF, L = 15.1 mH, LR = 1 mH, R = 0.1 ,

To evaluate the performance of the multilevel ac current

control and the capacitor voltage balancing with the optimal
predictive current controller, a dc source Udc (120 V) with
internal resistance of 0.2 is connected in the dc side of the
multilevel converter (Fig. 1), the nonlinear load is disconnected
from Fig. 1 (resulting in iL1 = i1 , iL2 = i2 , and iL3 = i3 ),
and the current references iLRef = iRef and iLRef = iRef
are obtained from DSP-based lookup tables. The results of
the multilevel currents and the capacitor voltages, obtained
with the optimal predictive controller, are compared with a
hysteresis-based sliding mode controller [11] since it also
works at a fixed sampling frequency but at a variable switching
frequency.
Simulation and experimental results of the ac currents i1 ,
i2 , and i3 , with T = 28 s and a steady-state operation
[Fig. 5(c) and (d)], show that they are nearly sinusoidal with a
very small ripple factor (less than 3%) and a THD that is lower
than 1%. In comparison, the sliding mode controller shows a
more than 7% ripple factor [Fig. 5(a) and (b)] and a THD of
around 6%.
The experimental power spectral density of the ac current
i1 using the sliding mode controller [Fig. 6(a)] shows that the
main harmonics are nearly 32 dB below the 50-Hz fundamental.
The power spectral density shows switching frequencies of over
3.5 kHz, with main spectral lines below 2 kHz. Using the optimal predictive controller [Fig. 6(b)], the experimental results
of the power spectral density of the ac current i1 show the main
harmonics to be nearly 46 dB below the 50-Hz fundamental,
an improvement of 14 dB compared to that of the sliding mode
controller. The switching frequency of the optimal predictive
controller is spreading over the frequency spectrum, which is
advantageous in reducing the audible noise, with main spectral
lines, compared to that of the sliding mode, of mainly below
2.5 kHz. It has been found that the mean value of the switching
frequency of the NPC converter can be reduced by a factor
of 2, compared to that of the sliding mode, by increasing the
ripple factor of the optimum predictive controller algorithm to
the levels of the sliding mode controller. This can be done by
decreasing the sampling period of the microprocessor, which
is further advantageous since it can decrease the cost of the
computing and sampling devices.
The improvement of the optimal controller is due to the chosen optimal vector that minimizes the errors of the ac currents
and the capacitor voltage imbalance. The optimal controller just
chooses the vector, leading to a minimum current error at the
end of each sampling time. The sliding mode controller always
chooses a vector to ensure fast reaching of the sliding mode
regime, unnecessarily increasing the ripple factor, the THD, and
the switching frequency.
The sliding mode controller is characterized by having a fast
dynamic response to step ac current reference changes [11].

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 10, OCTOBER 2008

Fig. 5. Sinusoidal ac currents i1 , i2 , and i3 in a steady-state operation. i1 has a displacement of 2 divisions, and i3 has a displacement of 2 divisions (vertical,
12 A/div; horizontal, 10 ms/div). (a) Sliding mode controller simulations. (b) Sliding mode controller experiments. (c) Optimal controller simulations. (d) Optimal
controller experiments.

Fig. 6. Power spectral density of the ac current i1 in a steady-state operation (vertical, 10 dB/div; horizontal, 500 Hz/div). (a) Sliding mode controller experiments.
(b) Optimal controller experiments.

Applying a positive step (3.5 to 7 A) in the ac current references

(Fig. 7, at 35 ms) and a negative step (7 to 3.5 A) at 75 ms
to compare the performance of the dynamic response for these
two controllers, the results show that they have similar dynamic
responses with no overshoot. The zoom of current i2 [Fig. 7(c)
and (d)] at the negative step time (75 ms) shows the detailed

dynamic response and also indicates that after the rise time,
the ac current i2 follows its reference, i.e., i2Ref , without a
stationary error [Fig. 7(d)].
The optimal predictive controller also chooses the optimal vector that minimizes the capacitor voltage errors, and
these voltages are balanced [Fig. 8(b)], with a mean error

BARROS AND SILVA: PREDICTIVE CONTROL OF NPC MULTILEVEL CONVERTER

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Fig. 7. Sinusoidal ac currents i1 , i2 , and i3 with an amplitude step. i1 has a displacement of 2 divisions, and i3 has a displacement of 2 divisions [vertical,
12 (A/div)/6 (A/Div); horizontal, 10 (ms/Div)/2 (ms/Div)]. (a) Sliding mode controller experiments. (b) Optimal controller experiments. (c) Sliding mode controller
experiments (i2 zoom). (d) Optimal controller experiments (i2 zoom).

Fig. 8. Capacitor voltages UC1 and UC2 with the ac current experiment step variations (vertical, 10 V/div; horizontal, 20 ms/div). (a) Sliding mode controller
experiments. (b) Optimal controller experiments.

of lower than 0.05%. The ac measurements of the capacitor

voltages show, based on the zooming results of Fig. 8(b),
with a vertical scale of 0.4 V/div, that the two capacitor voltages are really overlapped. Near-perfect capacitor dc voltage
balancing is obtained while reducing the current harmonic
distortion.
The capacitor voltages of the sliding mode controller are also
balanced, but they present a ripple error of about 6% [Fig. 8(a)].
The step variations of the ac current amplitude do not affect
the balancing of the capacitor voltages (Fig. 8) in these two
controllers.
To investigate the influence of the 6% ripple of the sliding
mode equalized capacitor voltages, in the ac current ripple
and the THD, simulations were done using two dc voltage
sources to enforce UC1 = UC2 = Udc /2 instead of the capacitors. The sliding mode controlled ac currents (Fig. 9) presented
almost the same ripple factor (7\%) and THD (6%) as in the

Fig. 9. Simulation results of ac currents i1 , i2 , and i3 using the sliding

mode controller and two dc voltage sources to enforce UC1 = UC2 = Udc /2
(vertical, 12 A/div; horizontal, 10 ms/div).

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 10, OCTOBER 2008

Fig. 10. Sinusoidal ac currents i1 , i2 , and i3 with nonnominal parameters. i1 has a displacement of 2 divisions, and i3 has a displacement of 2 divisions
(vertical, 12 A/div; horizontal, 10 ms/div). (a) Double inductance 2 L and half resistance R/2 test. (b) Half electrical network voltages UL /2 test.

Fig. 11. Capacitor voltages UC1 and UC2 with nonnominal parameters (vertical, 10 V/div; horizontal, 20 ms/div). (a) Double capacitance 2 C1 and
2 C2 test. (b) Half capacitance C1 /2 and C2 /2 test.

conditions of Fig. 5(a), showing that small levels of the capacitor voltage ripple [Fig. 8(a)] do not significantly affect the ripple
and the THD of ac currents that are controlled by the sliding
mode method.
The sliding mode controller uses a robust control law, implying a parameter-independent dynamic behavior. The optimal
predictive controller, which chooses the optimal vector of the
multilevel converter, is a model-based controller depending on
system parameters [the capacitors C1 and C2 , the inductors L,
with loss resistor R, the electrical network UL , voltages (Fig. 1),
and the sampling time T ]. To investigate the robustness of
the optimal predictive controller, with industrial component
tolerances, the parameters of the predictive laws were increased
100% or decreased 50% in two limit situations: 1) 2 C1 , 2
C2 , 2 L, R/2, and 2 UL ; and 2) C1 /2, C2 /2, L/2, 2 R,
and UL /2 (comparatively to the nominal values of C1 , C2 , L,
R, and UL ). The experimental results (Fig. 10) show that, even
with these predictive parameter strong mismatches, the ac currents follow their references, with mostly the same performance
obtained when using the nominal parameters (Fig. 5), and the
capacitor voltages are also balanced (Figs. 8 and 11). This
indicates that this optimal predictive controller also presents
some robustness to industrial parameter tolerances.

TABLE I
THD OF PREDICTIVE CONTROLLED AC CURRENTS
AS A F UNCTION OF S AMPLING T IME T

The ac line voltage during the experiments presented a THD

of about 5%, and the THD of ac currents with predictive control
is lower than 1%. This illustrates that the optimal predictive
controller tolerates common disturbances of the electrical network voltage.
Table I contains the evolution of the THD of the predictive
controlled ac currents as the sampling time T increases from
28 s to 1 ms. The THD of ac currents increased from 1% to
10%. During these experiments, the capacitor voltages of the
multilevel converter were always balanced.
The sliding mode controller balances the capacitor voltages using only the redundant vectors {(2, 15), (4, 17), (5, 18),
(10, 23), (11, 24), (13, 26)} [11]. Thus, if these vectors are
not selected, during enough time, from the current errors, the
capacitor voltage can become unbalanced. Fig. 12(a) shows a

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Fig. 12. Sinusoidal ac currents i1 and i2 (vertical, 12 A/div) together with capacitor voltages UC1 and UC2 (vertical, 10 V/div) with a dc voltage having 80%
of its rated value. The time division is 10 ms/div. (a) Sliding mode controller experiments. (b) Optimal controller experiments.

Fig. 13. Experimental results of the nonlinear currents iR1 , iR2 , and iR3 , and the ac line currents iL1 , iL2 , and iL3 , of the active power filter. iR1 and iL1 have
a displacement of 2 divisions, and iR3 and iL3 have a displacement of 2 divisions (vertical, 12 A/div; horizontal, 10 ms/div). (a) Nonlinear current experiments.
(b) AC line current experiments.

situation where the sliding mode is not able to balance the

capacitor voltage. In this case, a simple resistive load (4 ) is
connected as the electrical network (Fig. 1), and the dc voltage
is at 80% of its rated value. The application of nonredundant
vectors with large voltage values results in an unbalanced
capacitor voltage [Fig. 12(a)]. This particular situation can lead
to failure of the power semiconductors. The optimal predictive
controller that can use all the vectors to balance the capacitor
voltages completely solves this problem [Fig. 12(b)]. This
shows that it is not enough to use only the redundant vectors
to balance the capacitor voltages to assure the balancing of
capacitor voltages in all operating conditions.

B. Nonlinear Current Compensation and Power Factor

Correction With the Multilevel APF
These experiments assess the performance of the multilevel
APF. The shunt-connected multilevel APF (Fig. 1) is controlled
to compensate the current harmonics and regulate the power
factor (to be nearly unity). The current references of the APF
are generated to regulate the mean value of the dc voltage
UdcRef = 240 V, the power factor, and the ac line currents.

Fig. 14. Experimental results of the multilevel output currents i1 , i2 , and i3

of the active power filter. i1 has a displacement of 2 divisions, and i3 has a
displacement of 2 divisions (vertical, 12 A/div; horizontal, 10 ms/div).

The ac line current references iLRef and iLRef are the inputs of the optimal predictive controller (Fig. 3), which chooses

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 10, OCTOBER 2008

V. C ONCLUSION

Fig. 15. Experimental results of the ac line currents iL1 and iL2 (vertical,
12 A/div) and the ac line voltages UL1 and UL2 (vertical, 40 V/div) of the
active power filter. iL1 and UL1 have a displacement of 2 divisions, and iL2
and UL2 have a displacement of 2 divisions (horizontal, 10 ms/div).

Fig. 16. Experimental results of the dc voltage Udc of the active power filter
(vertical, 40 V/div; horizontal, 20 ms/div).

This paper has presented an optimal predictive control

method for the NPC multilevel converter, working as an APF
for power quality applications, and has compared the current
controller results with those of a robust sliding mode controller.
Experimental results obtained show that the robustness property of the sliding mode, which is particularly useful in the
presence of unknown disturbances, does not optimize the ripple
or the THD of the ac currents.
The proposed optimal predictive controllers, which predict in
real time the state space voltages and currents of the multilevel
converter and compute a quadratic cost function to choose the
optimal vector, present ac currents that track their references
with a smaller ripple and no steady-state error.
The capacitor voltages are correctly balanced and almost
indistinguishable, having a much smaller ripple than that of the
sliding mode controller. The predictive optimal vector selection
can reduce the mean value of the switching frequency and
lower the cost of the microprocessor and sampling devices
comparatively to those of the sliding mode controller for the
same level of the ac current ripple factor. The optimal predictive
controller also presents some robustness to industrial component tolerances, even with parameter deviations from +100%
to 50%.
The balancing of the capacitor voltage using redundant vectors is not assured in all operating conditions. Since all vectors
are analyzed for the capacitor voltage balancing, the predictive controller solves the problem of balancing the capacitor
voltages.
Since the optimal predictive controller achieves THD < 1%
and harmonic contents that are 46 dB below the fundamental,
this controller is a valuable addition for applications to enhance
power quality. The application of this controller as an APF
reduces the THD of the ac line current from 36% to 1% with
a near-unity power factor (0.997), significantly improving the
power quality.
R EFERENCES

the optimal vector to minimize the ac line current errors and

balance the capacitor voltages.
The experimental results of the nonlinear currents iR1 , iR2 ,
and iR3 [Fig. 13(a)] show that the THD is about 36%, and
the power factor is 0.91. The multilevel APF injects currents
(Fig. 14) to cancel the harmonic components of the nonlinear
currents. The THD of ac line currents is reduced from 36% to
nearly 1% [Fig. 13(b)].
Fig. 15 simultaneously shows the experimental results of the
ac line currents iL1 and iL2 with the ac line voltages UL1
and UL2 . The results indicate that the ac line voltage and the ac
line currents are in phase, showing that the power factor is near
unity. The power factor was improved from 0.910 (without the
APF) to 0.997 (using the APF).
The dc voltage Udc (Fig. 16) shows that the dc voltage
follows its references (UdcRef = 240 V) with almost no steadystate error (0.3%).
The optimization of the multilevel current control improves
the performance of the APF by reducing the THD of ac line
currents.

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J. Dionsio Barros (S04) received the Dipl.Ing. degree in systems and computer engineering from the
University of Madeira, Funchal, Portugal, in 1998,
and the M.Sc. degree in electrical and computer
engineering and the Ph.D. degree in electrical and
computer engineering from the Instituto Superior
Tcnico, Technical University of Lisbon, Lisbon,
Portugal, in 2002 and 2008, respectively.
He is currently an Assistant with the Department of Mathematics and Engineering, University
of Madeira, and a Researcher with the Center for
Innovation in Electrical and Energy Engineering. His main interests include
modeling, simulation, and control of multilevel converters applied to power
quality.

J. Fernando Silva (M92SM00) was born in

Mono, Portugal, in 1956. He received the
Dipl. Ing. degree in electrical engineering, the Ph.D.
degree in electrical and computer engineering (EEC),
and the Habilitation degree in EEC from the Instituto Superior Tcnico, Technical University of
Lisbon, Lisbon, Portugal, in 1980, 1990, and 2002,
respectively.
He is currently the Vice-President of the Department of EEC (DEEC) and an Associate Professor
of power electronics in the Energy Group of DEEC,
Technical University of Lisbon. He teaches power electronics, control of
switching power converter systems, and power quality. As the Leader of the
Power Electronics and Power Quality group of the Center for Innovation
in Electrical and Energy Engineering, his main research interests include
modeling, simulation, topologies, and advanced control of power electronics
systems and power quality. He supervised seven Ph.D. theses and is currently
cosupervising four Ph.D. students. He has authored two books (in Portuguese)
and more than 150 papers in international journals, books, and conferences with
reviewers.
Dr. Silva is a member of the Ordem dos Engenheiros, Portugal.