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Microprogrammed Control

MICROPROGRAMMED CONTROL

• Control Memory

• Sequencing Microinstructions

• Microprogram Example

• Microinstruction Format

• Design of Control Unit

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Microprogrammed Control Implementation of Control Unit

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS


Hardwired Control Unit Microprogrammed Control Unit
15 14 13 12 11 - 0 I Opcode Address

3x8
decoder Mapping
Logic Control Memory
7 6543 210
D0
D7 Control Address
logic control word
T15 gates Control signals
T0 specify
microoperations

15 14 . . . . 2 1 0
4 x 16 Decoder
decoder

4-bit Control signals specify


sequence
counter microoperations
(SC) ADD D1T4: DR ← M[AR]
D1T5: AC ← AC + DR, SC ← 0
Control signals of ADD instruction Control signals of ADD instruction
specify sequence of microops: specify sequence of microops:
DR ← M[AR] DR ← M[AR]
AC ← AC + DR AC ← AC + DR
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Microprogrammed Control Implementation of Control Unit

READ ONLY MEMORY (ROM)

Random Access Memory (RAM) Read Only Memory (ROM)

n data input lines


k address input lines

k address lines
2k words m x n ROM
Read (n bits/word) (m=2k)

Write
n data output lines
n data output lines

ROM Characteristics
- Perform read operation only, write operation is not possible
- Information stored in a ROM is made permanent during production

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Microprogrammed Control Implementation of Control Unit

MICROPROGRAMMED CONTROL UNIT

External Control
Next address Control Control
input generator address
memory word
(sequencer) register
(ROM)
(CAR)

Next-address information

Control Memory

Microinstruction Microoperation codes Next-address information

Microprogram :
Microinstruction

Sequencer: Logic circuit that determines the address of the next microinstruction

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Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING

Control Memory
CAR 
Fetch
routine
:
Indirect
routine
:
Execute
routine

- Microinstructions are stored in control memory in groups, each group


specifies a routine
- Each computer instruction has its own microprogram routine that
generates the microoperations needed to execute the instruction
- Address sequencing of control memory is capable of:
- Sequencing the microinstructions within the routine
- Branching from one routine to another based on the microinstruction
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Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers


bits logic select
Subroutine
Control address register register
(SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Memory


- Incrementing of the control address register
- Unconditional and conditional branches
- A facility for subroutine call and return
- A mapping process from the bits of the machine
instruction to an address for control memory
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Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers


bits logic select
Subroutine
Control address register register
(SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Memory


- Incrementing of the control address register
- Unconditional and conditional branches
- A facility for subroutine call and return
- A mapping process from the bits of the machine
instruction to an address for control memory
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Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers


bits logic select
Subroutine
Control address register register
(SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Memory


- Incrementing of the control address register
- Unconditional and conditional branches
- A facility for subroutine call and return
- A mapping process from the bits of the machine
instruction to an address for control memory
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Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers


bits logic select
Subroutine
Control address register register
(SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Memory


- Incrementing of the control address register
- Unconditional and conditional branches
- A facility for subroutine call and return
- A mapping process from the bits of the machine
instruction to an address for control memory
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Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers


bits logic select
Subroutine
Control address register register
(SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Memory


- Incrementing of the control address register
- Unconditional and conditional branches
- A facility for subroutine call and return
- A mapping process from the bits of the machine
instruction to an address for control memory
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Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers


bits logic select
Subroutine
register
Control address register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Problem 7-5: The system shown above uses a control memory of 1024 words of
32 bits each. The microinstruction has three fields as shown in the diagram. The
microoperation field has 16 bits.
a. How many bits are there in the branch address field and the select field?
b. If there are 16 status bits in the system, how many bits of the branch logic are
used to select a status bit?
c. How many bits are left to select an input for the multiplexers?
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Microprogrammed Control Sequencing

MAPPING OF INSTRUCTIONS

Machine OP-code
Instruction 1 0 1 1 Address 4-bit opcode

Mapping bits 0 x x x x 0 0

Microinstruction 0 1 0 1 1 0 0 7-bit address


address (for control memory
of 128 words)
OP-codes of Instructions
AND 0000
ADD 0001
LDA 0010 Control
memory
Address
Mapping bits 0 xxxx 00
0 0000 00 AND Routine

0 0001 00 ADD Routine

0 0010 00 LDA Routine

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Microprogrammed Control Sequencing

MAPPING OF INSTRUCTIONS

Problem 7-8: Formulate a mapping procedure that provides eight


consecutive microinstructions for each routine. The operation code
has six bits and the control memory has 2048 words.

Op-code (6 bits)
x x x x x x

0 0 x x x x x x 0 0 0
Microinstruction address (11 bits)

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Microprogrammed Control Microprogram

MICROPROGRAM EXAMPLE
Computer Configuration
PC DR
MUX
10 0 DR
AR
Address Memory
10 0 2048 x 16
PC

AC
MUX

15 0
6 0 6 0 DR
SBR CAR
AC
Control memory
128 x 20 Arithmetic
logic and
shift unit
Control unit
15 0
AC

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Microprogrammed Control Microprogram

MICROINSTRUCTION FORMAT

Machine instruction format


15 14 11 10 0
I Opcode Address

Sample machine instructions


Symbol OP-code Description
EA is the effective address
ADD 0000 AC ← AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC ← EA)
STORE 0010 M[EA] ← AC
EXCHANGE 0011 AC ← M[EA], M[EA] ← AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
Microoperations Next-address information AD: Address field

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Microprogrammed Control Microprogram

MICROINSTRUCTION FIELDS DESCRIPTION - F1,F2,F3

F1 F2 F3 CD BR AD
Microinstruction

F1 Microoperation Symbol F2 Microoperation Symbol F3 Microoperation Symbol


000 None NOP 000 None NOP 000 None NOP
001 AC ← AC + DR ADD 001 AC ← AC - DR SUB 001 AC ← AC ⊕ DR XOR
010 AC ← 0 CLRAC 010 AC ← AC ∨ DR OR 010 AC ← AC’ COM
011 AC ← AC + 1 INCAC 011 AC ← AC ∧ DR AND 011 AC ← shl AC SHL
100 AC ← DR DRTAC 100 DR ← M[AR] READ 100 AC ← shr AC SHR
101 AR ← DR(0-10) DRTAR 101 DR ← AC ACTDR 101 PC ← PC + 1 INCPC
110 AR ← PC PCTAR 110 DR ← DR + 1 INCDR 110 PC ← AR ARTPC
111 M[AR] ← DR WRITE 111 DR(0-10) ← PC PCTDR 111 Reserved

Two simultaneous microoperations:


DR  M[AR] with F2 = 100
and PC  PC + 1 with F3 = 101

 Microoperation fields = 000 100 101

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Microprogrammed Control Microprogram

MICROINSTRUCTION FIELDS DESCRIPTION - CD, BR

F1 F2 F3 CD BR AD
Microinstruction

CD Condition Symbol Comments


00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR ← AD if condition = 1
CAR ← CAR + 1 if condition = 0
01 CALL CAR ← AD, SBR ← CAR + 1 if condition = 1
CAR ← CAR + 1 if condition = 0
10 RET CAR ← SBR (Return from subroutine)
11 MAP CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0

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Microprogrammed Control Microprogram

SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler

Sample Format
five fields: label: micro-ops CD BR AD

Label: may be empty or may specify a symbolic


address terminated with a colon
Micro-ops: consists of one, two, or three symbols
separated by commas
CD: one of {U, I, S, Z}, where U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

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Microprogrammed Control Microprogram

SYMBOLIC MICROPROGRAM - FETCH ROUTINE -

F1 Symbol
During the fetch routine, read an instruction from memory, 000 NOP
map the opcode to microinstruction address, and update PC 001 ADD
010 CLRAC
011 INCAC
Sequence of microoperations for the fetch routine: 100 DRTAC
101 DRTAR
AR ← PC 110 PCTAR
DR ← M[AR], PC ← PC + 1 111 WRITE
AR ← DR(0-10), CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0
F2 Symbol F3 Symbol
000 NOP 000 NOP
Symbolic microprogram for the fetch routine: 001 SUB 001 XOR
010 OR 010 COM
ORG 64 011 AND 011 SHL
FETCH: PCTAR U JMP NEXT 100 READ 100 SHR
READ, INCPC U JMP NEXT 101 ACTDR 101 INCPC
DRTAR U MAP 110 INCDR 110 ARTPC
111 PCTDR 111

Binary microprogram translated by an assembler


CD Symbol BR Symbol
Binary 00 U 00 JMP
address F1 F2 F3 CD BR AD 01 I 01 CALL
1000000 110 000 000 00 00 1000001 10 S
10 RET
1000001 000 100 101 00 00 1000010 11 Z
1000010 101 000 000 00 11 0000000 11 MAP

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Microprogrammed Control Microprogram

SYMBOLIC MICROPROGRAM
• Control Memory: 128 20-bit words
• First 64 words: Routines for the 16 machine instructions
• Last 64 words: Used for other purpose (e.g., fetch routine and other routines)
• Mapping: Opcode XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram


Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH

ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH Symbol Opcode Description
OVER: NOP I CALL INDRCT ADD 0000 AC ← AC + M[EA]
ARTPC U JMP FETCH
BRANCH 0001 if (AC < 0) then (PC ← EA)
ORG 8 STORE 0010 M[EA] ← AC
STORE: NOP I CALL INDRCT EXCHANGE 0011 AC ← M[EA], M[EA] ← AC
ACTDR U JMP NEXT
WRITE U JMP FETCH

ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET

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Microprogrammed Control Microprogram

BINARY MICROPROGRAM

Address Binary Microinstruction


Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001


65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

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Microprogrammed Control

MICROPROGRAM

Problem 7-14: The following is symbolic microprogram for an instruction


in the computer defined in Chapter 7.

ORG 40
NOP S JMP FETCH
NOP Z JMP FETCH
NOP I CALL INDIRECT
ARTPC U JMP FETCH

a. Specify the operation performed when the instruction is executed.


b. Convert the four microinstructions into their equivalent binary form.

F1 Symbol F2 Symbol F3 Symbol CD Symbol BR Symbol


000 NOP 000 NOP 000 NOP 00 U 00 JMP
001 ADD 001 SUB 001 XOR 01 I 01 CALL
010 COM 10 S 10 RET
010 CLRAC 010 OR
11 Z 11 MAP
011 INCAC 011 AND 011 SHL
100 DRTAC 100 READ 100 SHR
101 DRTAR 101 ACTDR 101 INCPC
110 PCTAR 110 INCDR 110 ARTPC
111 WRITE 111 PCTDR 111

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Microprogrammed Control

MICROPROGRAM

Problem 7-16: Write a symbolic microprogram routine for the following


instruction in the computer defined in Chapter 7.

Symbol Opcode Symbolic Function Description


SUB 0101 AC ← AC – M [EA] Subtract

ORG 20
NOP I CALL INDIRECT
READ U JMP NEXT
SUB U JMP FETCH

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Microprogrammed Control Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING OF MICROOPERATION FIELDS -
F1 Symbol F2 Symbol F3 Symbol
000 NOP 000 NOP 000 NOP
F1 F2 F3 001 ADD 001 SUB 001 XOR
010 CLRAC 010 OR 010 COM
011 INCAC 011 AND 011 SHL
3 x 8 decoder 3 x 8 decoder 3 x 8 decoder 100 DRTAC 100 READ 100 SHR
7 6 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0 101 DRTAR 101 ACTDR 101 INCPC
110 PCTAR 110 INCDR 110 ARTPC
111 WRITE 111 PCTDR 111
AND
ADD AC
Arithmetic
logic and DR F1 Microoperation Symbol
DRTAC shift unit 101 AR ← DR(0-10) DRTAR
110 AR ← PC PCTAR
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC

0 1 F1 Microoperation Symbol
Select
Multiplexers 001 AC ← AC + DR ADD
100 AC ← DR DRTAC

F2 Microoperation Symbol
Load
AR Clock 011 AC ← AC ∧ DR AND

Problem 7-19: Show how outputs 5 and 6 of decoder F3 in the


above figure are to be connected to the program counter PC.
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Microprogrammed Control Design of Control Unit

MICROPROGRAM SEQUENCER

External
(MAP)
BR
L S1S0 Address Source
I0 3 2 1 0 00 CAR + 1
Input Load
I1 S1 MUX1 SBR 01 AD (JMP or CALL)
logic
T S0
10 SBR (Return)
Branch 11 MAP
Logic
1 Incrementer
I Test
S MUX2
Z Select
CAR
Clock
CD

Control memory

Microops CD BR AD
... ...

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Microprogrammed Control Design of Control Unit

MICROPROGRAM SEQUENCER

External
(MAP)
BR
L S1S0 Address Source
I0 3 2 1 0 00 CAR + 1
Input Load
I1 S1 MUX1 SBR 01 AD (JMP or CALL)
logic
T S0
10 SBR (Return)
11 MAP

1 Incrementer
I Test
S MUX2 CD Symbol
Z Select 00 U
CAR 01 I
Clock
10 S
CD
11 Z

BR Symbol T Function
Control memory 00 JMP 1 CAR ← AD
Microops CD BR AD 0 CAR ← CAR + 1
... ... 01 CALL 1 CAR ← AD, SBR ← CAR+1
0 CAR ← CAR + 1
10 RET X CAR ← SBR
11 MAP X CAR ← External

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Microprogrammed Control Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -

1 L L (load SBR with CAR + 1)


From I MUX2 Test
T for subroutine Call
CPU S Input
Z Select I0 logic S0 for next address
BR field I1
from S1 selection
Control Memory
CD field
from Control Memory

Input Logic
BR Input MUX 1 Load SBR S1S0 Address Source
Field I1I0T Meaning Source of Address S1S0 L 00 CAR + 1
01 AD (JMP or CALL)
00 000 next CAR+1 00 0 10 SBR (Return)
00 001 JMP AD 01 0 11 MAP
01 010 next CAR+1 00 0
01 011 CALL AD and SBR  CAR+1 0 1 1
10 10x RET SBR 10 0
11 11x MAP External 11 0

S1 = I1
S0 = I1I0 + I1’T

L = I1’I0T
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