MICROPROGRAMMED CONTROL
• Control Memory
• Sequencing Microinstructions
• Microprogram Example
• Microinstruction Format
1
Microprogrammed Control Implementation of Control Unit
3x8
decoder Mapping
Logic Control Memory
7 6543 210
D0
D7 Control Address
logic control word
T15 gates Control signals
T0 specify
microoperations
15 14 . . . . 2 1 0
4 x 16 Decoder
decoder
k address lines
2k words m x n ROM
Read (n bits/word) (m=2k)
Write
n data output lines
n data output lines
ROM Characteristics
- Perform read operation only, write operation is not possible
- Information stored in a ROM is made permanent during production
3
Microprogrammed Control Implementation of Control Unit
External Control
Next address Control Control
input generator address
memory word
(sequencer) register
(ROM)
(CAR)
Next-address information
Control Memory
Microprogram :
Microinstruction
Sequencer: Logic circuit that determines the address of the next microinstruction
4
Microprogrammed Control Sequencing
MICROINSTRUCTION SEQUENCING
Control Memory
CAR
Fetch
routine
:
Indirect
routine
:
Execute
routine
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Incrementer
select a status
bit
Microoperations
Branch address
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Incrementer
select a status
bit
Microoperations
Branch address
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Incrementer
select a status
bit
Microoperations
Branch address
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Incrementer
select a status
bit
Microoperations
Branch address
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Incrementer
select a status
bit
Microoperations
Branch address
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Incrementer
select a status
bit
Microoperations
Branch address
Problem 7-5: The system shown above uses a control memory of 1024 words of
32 bits each. The microinstruction has three fields as shown in the diagram. The
microoperation field has 16 bits.
a. How many bits are there in the branch address field and the select field?
b. If there are 16 status bits in the system, how many bits of the branch logic are
used to select a status bit?
c. How many bits are left to select an input for the multiplexers?
11
Microprogrammed Control Sequencing
MAPPING OF INSTRUCTIONS
Machine OP-code
Instruction 1 0 1 1 Address 4-bit opcode
Mapping bits 0 x x x x 0 0
12
Microprogrammed Control Sequencing
MAPPING OF INSTRUCTIONS
Op-code (6 bits)
x x x x x x
0 0 x x x x x x 0 0 0
Microinstruction address (11 bits)
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Microprogrammed Control Microprogram
MICROPROGRAM EXAMPLE
Computer Configuration
PC DR
MUX
10 0 DR
AR
Address Memory
10 0 2048 x 16
PC
AC
MUX
15 0
6 0 6 0 DR
SBR CAR
AC
Control memory
128 x 20 Arithmetic
logic and
shift unit
Control unit
15 0
AC
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Microprogrammed Control Microprogram
MICROINSTRUCTION FORMAT
Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
Microoperations Next-address information AD: Address field
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Microprogrammed Control Microprogram
F1 F2 F3 CD BR AD
Microinstruction
16
Microprogrammed Control Microprogram
F1 F2 F3 CD BR AD
Microinstruction
BR Symbol Function
00 JMP CAR ← AD if condition = 1
CAR ← CAR + 1 if condition = 0
01 CALL CAR ← AD, SBR ← CAR + 1 if condition = 1
CAR ← CAR + 1 if condition = 0
10 RET CAR ← SBR (Return from subroutine)
11 MAP CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0
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Microprogrammed Control Microprogram
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler
Sample Format
five fields: label: micro-ops CD BR AD
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Microprogrammed Control Microprogram
F1 Symbol
During the fetch routine, read an instruction from memory, 000 NOP
map the opcode to microinstruction address, and update PC 001 ADD
010 CLRAC
011 INCAC
Sequence of microoperations for the fetch routine: 100 DRTAC
101 DRTAR
AR ← PC 110 PCTAR
DR ← M[AR], PC ← PC + 1 111 WRITE
AR ← DR(0-10), CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0
F2 Symbol F3 Symbol
000 NOP 000 NOP
Symbolic microprogram for the fetch routine: 001 SUB 001 XOR
010 OR 010 COM
ORG 64 011 AND 011 SHL
FETCH: PCTAR U JMP NEXT 100 READ 100 SHR
READ, INCPC U JMP NEXT 101 ACTDR 101 INCPC
DRTAR U MAP 110 INCDR 110 ARTPC
111 PCTDR 111
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Microprogrammed Control Microprogram
SYMBOLIC MICROPROGRAM
• Control Memory: 128 20-bit words
• First 64 words: Routines for the 16 machine instructions
• Last 64 words: Used for other purpose (e.g., fetch routine and other routines)
• Mapping: Opcode XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH Symbol Opcode Description
OVER: NOP I CALL INDRCT ADD 0000 AC ← AC + M[EA]
ARTPC U JMP FETCH
BRANCH 0001 if (AC < 0) then (PC ← EA)
ORG 8 STORE 0010 M[EA] ← AC
STORE: NOP I CALL INDRCT EXCHANGE 0011 AC ← M[EA], M[EA] ← AC
ACTDR U JMP NEXT
WRITE U JMP FETCH
ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET
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Microprogrammed Control Microprogram
BINARY MICROPROGRAM
21
Microprogrammed Control
MICROPROGRAM
ORG 40
NOP S JMP FETCH
NOP Z JMP FETCH
NOP I CALL INDIRECT
ARTPC U JMP FETCH
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Microprogrammed Control
MICROPROGRAM
ORG 20
NOP I CALL INDIRECT
READ U JMP NEXT
SUB U JMP FETCH
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Microprogrammed Control Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING OF MICROOPERATION FIELDS -
F1 Symbol F2 Symbol F3 Symbol
000 NOP 000 NOP 000 NOP
F1 F2 F3 001 ADD 001 SUB 001 XOR
010 CLRAC 010 OR 010 COM
011 INCAC 011 AND 011 SHL
3 x 8 decoder 3 x 8 decoder 3 x 8 decoder 100 DRTAC 100 READ 100 SHR
7 6 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0 101 DRTAR 101 ACTDR 101 INCPC
110 PCTAR 110 INCDR 110 ARTPC
111 WRITE 111 PCTDR 111
AND
ADD AC
Arithmetic
logic and DR F1 Microoperation Symbol
DRTAC shift unit 101 AR ← DR(0-10) DRTAR
110 AR ← PC PCTAR
PCTAR
DRTAR
From From
PC DR(0-10) Load
AC
0 1 F1 Microoperation Symbol
Select
Multiplexers 001 AC ← AC + DR ADD
100 AC ← DR DRTAC
F2 Microoperation Symbol
Load
AR Clock 011 AC ← AC ∧ DR AND
MICROPROGRAM SEQUENCER
External
(MAP)
BR
L S1S0 Address Source
I0 3 2 1 0 00 CAR + 1
Input Load
I1 S1 MUX1 SBR 01 AD (JMP or CALL)
logic
T S0
10 SBR (Return)
Branch 11 MAP
Logic
1 Incrementer
I Test
S MUX2
Z Select
CAR
Clock
CD
Control memory
Microops CD BR AD
... ...
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Microprogrammed Control Design of Control Unit
MICROPROGRAM SEQUENCER
External
(MAP)
BR
L S1S0 Address Source
I0 3 2 1 0 00 CAR + 1
Input Load
I1 S1 MUX1 SBR 01 AD (JMP or CALL)
logic
T S0
10 SBR (Return)
11 MAP
1 Incrementer
I Test
S MUX2 CD Symbol
Z Select 00 U
CAR 01 I
Clock
10 S
CD
11 Z
BR Symbol T Function
Control memory 00 JMP 1 CAR ← AD
Microops CD BR AD 0 CAR ← CAR + 1
... ... 01 CALL 1 CAR ← AD, SBR ← CAR+1
0 CAR ← CAR + 1
10 RET X CAR ← SBR
11 MAP X CAR ← External
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Microprogrammed Control Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -
Input Logic
BR Input MUX 1 Load SBR S1S0 Address Source
Field I1I0T Meaning Source of Address S1S0 L 00 CAR + 1
01 AD (JMP or CALL)
00 000 next CAR+1 00 0 10 SBR (Return)
00 001 JMP AD 01 0 11 MAP
01 010 next CAR+1 00 0
01 011 CALL AD and SBR CAR+1 0 1 1
10 10x RET SBR 10 0
11 11x MAP External 11 0
S1 = I1
S0 = I1I0 + I1’T
L = I1’I0T
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