2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

A design of ring oscillator based PUF on FPGA

Filip Kodytek and Robert Lorencz
Czech Technical University
Department of Computer Systems
Prague, Thakurova 9
Email: kodytl@t.cvut.cz, lorencz@t.cvut.cz

during the manufacturing process to generate unpredictable

outputs. PUF concept is based on these random variations,
which cannot be controlled during the manufacturing process,
because they result from the effects of random and uncotrollable inuences. Therefore it is impossible or very difcult to
produce two identical devices.
There is a strong similarity with human biometrics such
as ngerprints. Just like any person may be identied by its
unique ngerprints, we are able to identify every electronic
device on the basis of its unique physical properties that PUF
uses as its source of randomness.
Since producing a PUF output depends on random local
mismatches between physical components of a device, the
outputs of one PUF may not be the same, when repeated. Some
errors may occur in the PUF output. These errors might be
caused by completely random noise or certain environmental
conditions such as changes in temperature or supply voltage
in case of a PUF on an integrated circuit.
If these errors occur in a limited quantity and we are using
PUF for identication purposes, we do not need to worry about
them. However, in case of using PUF for cryptographic key
generation, some additional steps to stabilize the PUF output
have to be taken. Some changes in the PUF design can be
made in order to stabilize the output and we can also correct
the output using error correcting codes to get the same output.
In 2001, the rst description and denition of general
concept of PUFs was made in Pappus dissertation thesis [10].
Since then, a wide variety of PUF designs has been proposed,
but the only ones we are interested in are those that can
be implemented on FPGA. The two major groups of PUFs
suitable for FPGA divided according to their sources of
randomness are delay-based and memory-based PUFs.
Delay-based PUFs exploit the random variations in delays
of logic gates and interconnects. One of the rst delay-based
PUFs is Arbiter PUF [6], which consists in a set up of a
race condition, where a signal propagates along two different
but symmetric paths. The result depends on which one of the
two paths is faster. Another examples of delay-based PUFs
are Ring Oscillator PUF (ROPUF) [13], [2], [9] and Glitch
PUF [14].
Since many electronic devices have embedded SRAM, a
very common PUF design is based on SRAM and use it as a
source of randomness [3], [11]. The basic principle of SRAM
PUF is based on the content of SRAM after power-up. Each
SRAM cell has a bias towards one of the possible values (0
or 1) and this bias is random and independent, hence they are

AbstractThis paper deals with design of Physical Unclonable

Functions (PUFs) based on FPGA. The goal was to propose
a cheap, efcient and secure device identication or even a
cryptographic key generation based on PUFs. Therefore, a
proposal of a ring oscillator (RO) based PUF producing more
output bits from one RO pair is presented. 24 Digilent Basys 2
FPGA boards were tested and statistically evaluated indicating
suitability of the proposed design for device identication.
Index TermsPUF, FPGA, ring oscillator

I. I NTRODUCTION
This paper describes a design of RO based PUF on
FPGA [7]. In this section we provide a motivation and
background that led to ivestigation of physical unclonable
functions (PUFs) and a brief introduction to the topic of PUFs.
Then we describe our contribution to this topic.
A. Motivation and background
Nowadays, various electronic devices are everywhere
around us in our everyday life [6]. We all use devices such as
mobile phones, credit cards and RFIDs to store personal data
ensuring us access to bank accounts or private areas. For this
reason, all these devices became targets for adversaries, which
raises problems with security and privacy protection. Classical
cryptography offers various measures against these issues, but
they all consist in the concept of a secret key. It is assumed
that the device is able to contain secret information, which
remains hidden to the potential adversary. The secret keys
are often stored in a non-volatile memory, which is usually
difcult to secure.
This approach may be problematic in many cases. Safe
storages of keys are usually complicated and expensive to
achieve. Non-volatile memory tends to be vulnerable to invasive attacks, because the key is stored in a digital form [2]. For
high level of security, electronic devices have to be protected
by expensive circuits, which are able to detect manipulation
with the device and moreover, they need to be continually
power supplied. Another disadvantage can be the cost of
even basic cryptographic operations for resource constrained
platforms such as RFID chips.
B. Physical Unclonable Functions
The above described issues were one of the motivations
that led to the development of PUFs. PUFs are increasingly
used in proposals of cryptographic protocols and security
architectures. PUF is a function based on physical properties,
which are unique for each device. It uses local mismatches and
differences between physical components of a device arising
978-1-4799-6780-3/15 $31.00 2015 IEEE
DOI 10.1109/DDECS.2015.21

37

The random variations in delays are reected in measured

frequencies of ROs. We can simply measure ring oscillators
frequency by using counters and some reference clock at
which we know its frequency. This frequency can be determined by the number of ring oscillators oscillations that are
recorded by the counter in a certain time specied by the
reference clock. From the resulting value in the counter we
can easily calculate the ring oscillators frequency.
Thus obtained frequencies of each RO can be used for
PUF. These frequencies are used depending on the particular
ROPUF proposal. In some ROPUF designs it is not necessary
to know the particular frequency of each RO, but we can
already use the resulting value in the counter.

MUX

counter
2

>?

Output
0 or 1

N oscillators
counter

Input

Fig. 1. Ring Oscillator PUF design [3].

B. Ring Oscillator PUF constructions

The rst type of ROPUF was proposed by Gassend et al. [2].
The measured frequencies of equal ROs on different devices
shows sufcient variation to act as a PUF output. However, the
inuence of environmental conditions on the frequency of ROs
is signicant and some additional technique to compensate
these inuences is required. Gassend et al. [2] proposed
a technique called compensated measuring. The main idea
behind compensated measuring is that environmental changes
will affect the frequencies of ROs approximately the same way,
therefore a ratio of measured frequencies of RO pairs can be
considered as the eventual PUF output.
This ROPUF construction based on the ratio of measured
frequencies proved to be effective in compensating the environmental changes. Nevertheless, this construction has some
drawbacks. Since their ROs are based on the same delay
circuit as the basic Arbiter PUF, their PUF is vulnerable
to modeling attacks and some countermeasures have to be
made. In addition, the result of frequency ratios in case of
compensated measuring are real values and cannot be used
directly as a bit string, hence they have to be processed in an
appropriate way to get a proper PUF output.
Another ROPUF construction proposed by Suh and Devadas [13] is shown in Fig. 1. Their ROPUF design consists of
n symmetric ROs that are connected to two multiplexers. Each
of multiplexers selects one of the ROs according to the input
signal and connects its output to the counter. Both counters
count oscillations of the selected ROs for a xed time interval.
The resulting values in both counters are compared and one
bit of the PUF output is produced based on the result of the
comparison. Since one comparison produces only one bit of
the PUF output, this whole process has to be repeated several
times with different selections of ROs to produce the complete
PUF output.
It is necessary that all of the ROs in this ROPUF construction are symmetric to each other in order to assure
that the comparison results are unpredictable. Due to the
symmetry of ROs the differences in their frequencies are
completely dependent on random variations in delays. The
frequency comparison can be considered as another form
of compensated measuring to eliminate the inuences of
environmental changes. Suh and Devadas [13] also proposed a
technique called 1-out-of-k masking, which reduce the number

suitable source of randomness for PUF. However some of the

modern FPGAs initialize their memory after power-up, so all
the randomness is lost. This is one of the reasons that led to
proposals of another memory-based PUFs that simulate SRAM
PUF behavior. These memory-based PUFs are for example
Buttery PUF [5], Latch PUF [12] and Flip-op PUF [8].
C. Our contribution
In this paper, we present RO based PUF, which uses 16bit counter values generated by RO pairs by selecting suitable
bit positions from these values for PUF. The advantage of
this design is that it is easy to implement, since the ROs no
longer need to be symmetric, and it produces more output bits
from one RO pair. We performed extensive measurements on
24 Digilent Basys 2 FPGA boards and statistically evaluated
the results. Our results show, that this ROPUF design is
suitable for device identication and can be even used for
cryptographic key generation, when it is combined with error
correction code.
D. Organization of the paper
The paper is organized as follows. We provide a brief
introduction to ROPUFs in Section II, since the proposed PUF
design is based on ROs. In Section III we present the proposed
RO based PUF proposal for device identication. The results
of evaluated measurements on 24 Digilent Basys 2 FPGA
boards are presented in Section IV. In Section V the paper
is concluded.
II. R ING O SCILLATOR PUF
A numerous PUF constructions based on ROs have been
proposed to this day, but it is not the goal of this paper to
introduce them all. This section describes the main principle
of ROPUFs that have been proposed so far.
A. Measuring a delay
Since ROPUF is a delay-based PUF, it benets from the
random variations in delays of logic gates and interconnects.
The method that is used in ROPUFs to measure delays is to use
some delay circuit and making it a self-oscillating loop. This
can be achieved by inverting the output of the delay circuit
and feeding it back into the delay circuits input [2]. These
oscillating circuits are usually called ROs.

38

Measurement circuit

fRO1
RO1

most significant bit

enable

1011 1001 0110 1100

OF

CE

least significant bit

highly stable positions

Counter1

very unstable positions

CLR
OF

fRO2
RO2

Overflow
detection

OF

CE

Q
C

the increasing stability

result

Fig. 3. The example behavior of positions stability in a 16-bit value.

RST

are represented in binary code, we can use the appropriately

selected part of each binary number for PUF output. It can
be assumed that if we make multiple measurements of one
RO pair, bits that are close to the least signicant bit (LSB)
will vary a lot for example due to environmental changes. On
the contrary, bits close to the most signicant bit (MSB) will
be stable and the environmental changes will have almost no
inuence on them. The more we will be close to the MSB,
the more stable these bits will be. The example of described
behavior of measured values is shown on 16-bit value in Fig. 3.
A similar concept of choosing suitable bits for PUF from
counter values was presented in the work by Bossuet et al. [1].
A. Bit stability
The stability si (RO) of bit at position i from a value
measured using one particular RO pair is determined as
follows:

if P (bi = 1) 0.5
P (bi = 1)
si (RO) =
(1)
1 P (bi = 1) if P (bi = 1) < 0.5,

Counter2
CLR

reset

Fig. 2. The method of measuring the number of cycles of ring oscillators in

the proposed ROPUF design.

of possible comparisons in order to get more stable output.

This technique is based on the selection of one RO pair with
the biggest difference in their frequencies from k oscillators.
Maiti and Schaumont [9] used the same design as Suh and
Devadas together with the technique 1-out-of-k masking to
increase the output stability, which is now based on congurable ROs instead of basic ROs. They consider the most stable
conguration out of k possible congurations of one RO pair,
not the most stable RO pair. The advantage of congurable
ROs is that they allow more efcient utilization of resources.
III. R ING O SCILLATOR PUF PROPOSAL
Our goal was to propose a PUF that is easy and effective
to implement. A different technique than frequency ratios or
comparisons in order to generate PUF output will be used in
this design. This technique does not require all ROs to be
symmetric. The PUF output will also be obtained based on
the selected RO pairs, but the problem of selecting particular
RO pairs is no longer present and on top of that, more bits for
the PUF output will be gained from each pair. This makes it
possible to produce a longer PUF output using less ROs.
The basic building element of the proposed ROPUF design
is a ve stage RO (1 NAND, 4 inverters). Instead of measuring
frequency of each RO using reference clock we choose one
RO pair and count their oscillations simultaneously using two
counters. As soon as one of these counters overows, the
measurement is stopped. The resulting value in the counter that
did not overow is used for further processing. This approach
is shown in Fig. 2.
When implementing the logic for detecting overow of one
of the counters and stopping the other one, the routes between
them may have different delays and in the meantime, before
the counter is stopped, it can perform some additional steps.
But since these two routes are the same for all RO pairs and
for all FPGAs, it will only increase the resulting counter value
by some constant offset.
Thus obtained measured counter values are used for PUF
and they are not modied in any way. Since these values

where P (bi = 1) stands for the probability of occurence of 1

at position i and is dened as:
P (bi = 1) =

k
1
bj,i ,
k j=1

(2)

where k is the number of executed measurements and bj,i

indicates the i-th bit of j-th measured value.
It is obvious, that each RO pair will have different stability
on various positions of measured values, since the ROs in this
design are no longer mutually symmetric. For this reason, if
we want to perform a suitable selection of positions for the
PUF output for all RO pairs, we have to determine the average
stability of each position. Provided we have n RO pairs, the
average stability si of position i is determined as:
n
1
si =
sj (ROj ),
(3)
n j=1
where ROj is j-th pair of ROs.
Based on the average stability si of each position we can
decide which bits are suitable for PUF output. Ideally, we
would like the stability si of selected bit positions to be equal
to 1, but we might not be able to achieve such stability, or
only at a few bits that are closest to the MSB. Therefore, it is
convenient to dene a threshold value sth according to which
we will select appropriate bit positions. For example, if we
choose sth = 0.95, then we select all positions from the MSB
to the rst position, where si < 0.95.

39

the increasing entropy

fRO1

Hintra > Hth

most
significant bit

Hinter > Hth

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
selected
positions

enable

RO1

1011 0110 1110 0111

fRO2
RO2

least
significant bit

.
.
.
.
.

pos = 9
w=3

multiplexer

s > sth

>

the increasing stability

fRO i
Measurement
circuit

fRO j

result

Bit
selection

out

10

fROn

ROn

Fig. 4. The example selection of suitable bit positions for PUF.

reset
sel

B. Entropy
So far we have selected appropriate bit positions based on
their stability si . However, in addition to their stability we have
to take into account their uniqueness among different FPGAs.
We may assume, that if we compare measured values from
two equally positioned RO pairs on two FPGAs, bits close
to the MSB will not differ, while bits approximately in the
middle between the most and the least signicant bits will be
different. It is unnecessary to consider bit positions close to
the LSB, since it is expected, that they will be different due
to their unstability.
The average entropy of bit position i within each FPGA
separately can be determined as follows:
m

Hintra (i) =

Fig. 5. The design of the proposed ROPUF.

The ideal value of Hintra and Hinter is 1 (it is the maximum

entropy for 1-bit message). Such value will guarantee us that
there is no correlation between bits on the same positions
among different FPGAs. For example, the lower the entropy
Hinter is, the higher is the probability of succesful estimation
of the bit at given position on another FPGA, provided we
already know this bit from one FPGA.
C. Method of selecting suitable bit positions for PUF
When selecting suitable bit positions for PUF, we have to
abide by both stability as well as their entropy. The stability is
increasing towards the MSB, while the entropy is decreasing
in the same direction. Therefore it is necessary to choose a
compromise between good entropy and high stability, where
both variables are close enough to their ideal value 1. Based
on the statistics, the selection of appropriate bits may look as
follows:
We proceed from the most to the least signicant bit
as long as the stability si is higher then the threshold
value sth determined by us. As soon as we come across a
position, where si < sth , we stop and return one position
back. Thus found position is denoted as variable pos.
Then we proceed from the position pos back towards the
MSB, however, this time we abide by the entropy Hintra
and Hinter . We proceed backwards until both entropies
satisfy our criteria (Hintra (i) > Hth Hinter (i) > Hth ).
This procedure is stopped as soon as the entropy is
no longer sufcient. The width w of our selection is
determined by the difference of the current position and
position pos.
This whole procedure is shown in Fig. 4.

1 
pj (k)log2 (pj (k)),
m j=1

(4)

k=0

where m is the number of FPGAs and pj (k) is the probability

of message k within the j-th FPGA. There are only 2 possible
messages, namely 0 and 1. The probability of their occurrence
we compute as:
n

pj (1) =

1
maj(ROj,k , i),
n

pj (0) = 1 pj (1),

(5)

k=1

where ROj,k represents the k-th RO pair on the j-th FPGA

and n is the number of RO pairs. maj(RO, i) is the majority
of the i-th position determined from k measurements evaluated
for each pair of ROs. The result is in this case either 1 or 0
and is dened as:
maj(RO, i) = round(

k
1
bj,i ),
k j=1

(6)

where round(x) rounds number x to integer.

The average entropy of bit position i of each of the n RO
pairs across different FPGAs can be determined using a similar
formula:
n

Hinter (i) =

D. Proposed ROPUF architecture

The maximum amount of bits that we
 are able to extract
using the above described method is n2 w. It is the number
of all possible combinations of RO pairs multiplied by the
number of bits, that we select from measured value from one
pair.
The simplied example of how this PUF design might look
like is shown in Fig. 5. One pair from n ROs is selected using
a multiplexer and input signal sel and this pair is then used
for measurement. The result of this measurement is processed
by the circuit bit selection, where a particular segment of the
whole result is withdrawn. We can simply concatenate thus
obtained segments and the nal bit string represents the PUF
output.

1 
pl (k)log2 (pl (k)),
n

(7)

l=1 k=0

where pl (k) this time is the probability of message k of

the l-th RO pair among different FPGAs. This probability is
determined similarly as in the case of Hintra , we just calculate
it for a particular RO pair among different FPGAs. pl (k) is
dened as:
m
1 
pl (1) =
maj(ROk,l , i), pl (0) = 1 pl (1). (8)
m
k=1

40

position(i)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

150 pairs of ring oscillators

si
Hintra
Hinter
1
0.1414
0
0.9996
0.9477
0.0557
0.9995
0.9944
0.0794
0.9985
0.9962
0.1657
0.9983
0.9992
0.2955
0.9950
0.9941
0.7183
0.9908
0.9958
0.9475
0.9815
0.9954
0.9663
0.9650
0.9946
0.9639
0.9297
0.9954
0.9681
0.8624
0.9943
0.9701
0.7268
0.9957
0.9728
0.5569
0.9932
0.9732
0.5139
0.9961
0.9654
0.5135
0.9957
0.9647
0.5140
0.9897
0.9613

P (bi = 1)
0.98
0.3663
0.5430
0.5336
0.4998
0.4765
0.5056
0.4959
0.4931
0.4997
0.4960
0.4985
0.5001
0.4985
0.4975
0.4967

position(i)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

450 pairs of ring oscillators

si
Hintra
Hinter
0.9999
0.5473
0.0132
0.9997
0.9831
0.0395
0.9995
0.9949
0.0937
0.9989
0.9979
0.1898
0.9980
0.9982
0.3598
0.9961
0.9973
0.6585
0.9920
0.9982
0.9232
0.9841
0.9986
0.9682
0.9677
0.9984
0.9692
0.9347
0.9983
0.9706
0.8709
0.9984
0.9707
0.7441
0.9981
0.9709
0.5691
0.9987
0.9706
0.5185
0.9982
0.9727
0.5180
0.9981
0.9663
0.5182
0.9972
0.9687

P (bi = 1)
0.8736
0.4239
0.5410
0.5248
0.5233
0.5233
0.5118
0.4978
0.4971
0.5047
0.5042
0.4969
0.5005
0.4996
0.4991
0.4977

TABLE I
M EASUREMENT RESULTS FOR 16- BIT COUNTER VALUES .

G. Inter-Hamming distance
Another important measure of the PUF quality is the
uniqueness generated responses among different FPGAs. We
determine this uniqueness via Inter-Hamming distance and is
dened as:

To prove that the PUF outputs generated this way are stable
and they differ among various FPGAs, we calculate their
bit error rate (BER), Intra-Hamming distance (HDintra ) and
Inter-Hamming distance (HDinter ).
E. Bit error rate
The verication of bit stability in this ROPUF design can
be done by calculating the bit error rate. For n-bit responses
of the i-th FPGA we dene BER as follows:
k
1 
HD(Rpi , Ri,j ),
(9)
BER(i) =
n k j=1

m1 m
1  
HDinter = m
HD(Rri , Rrj ) 100 [%]. (12)
2

IV. E XPERIMENTAL RESULTS

In this section, the results of evaluated measurements, which
were all realized on 24 Digilent Basys 2 FPGA boards, are
presented. For these measurements, we implemented a circuit
containing 300 ROs divided into two groups of 150 ROs. The
ROs used in our circuit are ordinary ve stage ROs and their
cycles are counted by 16-bit counters. On this circuit, we made
measurements starting with 150 RO pairs (each oscillator from
the rst group is paired with another unused oscillator from
the second group) and 1000 measurements were executed for
each pair. The next measurement was performed for 450 pairs
with 500 measurements for each pair.
At rst, we present the results of stability (si ), entropy
(Hintra , Hinter ) and bias (P (bi = 1)) for each position of
16-bit values. As can be seen in Table I, the entropy rises and
is closing to the ideal value of 1 (especially Hinter , Hintra
is high since position 2), while the stability is lowering with
increasing position. The bias is very close to the ideal value
of 0.5 on all positions apart from the rst few positions.
The next Table II presents the results for PUF that uses
different selections of positions. We used the same data that
we measured before and assembled PUF responses from them.
Thus created PUF responses were 150*w or 450*w bits long,
where w is the number of bits selected from each RO pair.
When calculating HDintra , we used the rst response as the
reference response. We calculated HDinter among all FPGAs
using mean responses from all obtained responses for each
FPGA. Since one of our goals is to achieve HDinter close
to 50%, it is desirable to select bits starting at position 7.
However, we need the PUF responses to be stable enough,
therefore we have to select bits, so that BER and HDintra are

where k is the number of responses from the PUF, HD is

the Hamming distance between two bit strings, Ri,j is the
j-th response from PUF on the i-th FPGA and Rp is the
mean response made from k responses. We determine Rp
from majorities for each position in n-bit responses.
The average bit error rate for m FPGAs is calculated as:
m
1 
BER(i) 100 [%].
(10)
BER =
m i=1
F. Intra-Hamming distance
In addition to stability of PUF responses we are interested
in how much the responses generated by given PUF are similar
to each other. BER expresses what is the probability of error
occurence in one bit, but not the similarity of responses. The
similarity between responses within each PUF is denoted as
Intra-Hamming distance. HDintra is estimated as:
HDintra =

i=1 j=i+1

m k
1 
HD(Rri , Ri,j ) 100 [%], (11)
m k i=1 j=1

where m is the number of FPGAs, Rr is the reference response

which the other responses are compared to and k is the number
of compared responses from each PUF. As Rr , we can use
either any response from given PUF or the mean response
made of several responses as the reference response (this may
result in lower HDintra ). There are several inuences that
affect the value of HDintra (and BER as well) such as changes
in voltage or temperature, which cause HDintra to be of
higher value.

41

150 pairs of ring oscillators

450 pairs of ring oscillators
positions
68
78
79
89
68
78
79
89
w [-]
3
2
3
2
3
2
3
2
BER [%]
1.09
1.38
2.09
2.67
0.92
1.19
1.87
2.41
HDintra [%]
1.61
2.05
3.1
3.95
1.37
1.78
2.79
3.6
HDintra interval [%]
0, 6.44
0, 7
0, 8.67
0, 10
0, 3.56
0, 4.56
0.74, 6.37
1.11, 8.22
HDinter [%]
44.27
49.15
49.31
49.70
42.69
48.42
48.94
49.96
HDinter interval [%] 36.67, 52.44 39.67, 58.33 42.22, 56.67 40.33, 58.33 34.67, 52.3 42.33, 56.11 44.74, 54.74 45.44, 54.67
TABLE II
T HE RESULTS OF STATISTICS CARRIED OUT FOR RESPONSES COMPOSED FROM VARIOUS BIT SELECTIONS .

FPGA 1

FPGA 2,3

temperature [ C]
BER [%]
HDintra [%]
minHDintra [%]
maxHDintra [%]
temperature [ C]
BER [%]
HDintra [%]
minHDintra [%]
maxHDintra [%]

36.2
0.3111
0.3745
0
1.1111
38.9
0.48
0.5854
0
1.3333

64.8
0.3518
0.5382
0
1.1111
66.5
0.31
0.6403
0
2

36.2 64.8
3.5317
3.8927
0
8
36.2 64.8
2.9766
3.3346
0
7.8889

determined stability and entropy for each position of 16-bit

counter value, indicating which positions are useful for PUF.
As the results indicate, we can generate PUF responses with
low HDintra and HDinter close enough to the ideal 50% by
selecting appropriate bit positions.
R EFERENCES
[1] Bossuet, L., Ngo, X. T., Cherif, Z., Fischer, V. A PUF based on a
transient effect ring oscillator and insensitive to locking phenomenon.
In IEEE Transactions on Emerging Topics in Computing, pages 3036,
March 2014.
[2] Gassend, B., Clarke, D., van Dijk, M., Devadas, S. Silicon Physical Random Functions. In ACM Conference on Computer and Communications
Security - CCS 2002, pages 148160. ACM, New York, NY, USA, 2002.
[3] Holcomb, D. E., Burleson, W. P., Fu, K. Power-Up SRAM State as
an Identifying Fingerprint and Source of True Random Numbers. IEEE
Transactions on Computers 58, 9, pages 1198-1210, 2009.
[4] Kodytek, F. Physical Unclonable Functions on FPGA. Bachelors thesis.
Czech Technical University in Prague, Faculty of Information Technology, 2014.
[5] Kumar, S., Guajardo, J., Maes, R., Schrijen, G.-J., Tuyls, P. Extended
abstract: The Buttery PUF Protecting IP on Every FPGA. In IEEE
International Symposium on Hardware-Oriented Security and Trust HOST 2008, pages 6770. IEEE, Washington, DC, USA, 2008.
[6] Lee, J. W., Lim, D., Gassend, B., Suh, G.E., van Dijk, M., Devadas, S.
A technique to build a secret key in integrated circuits for identication
and authentication applications. In Symposium on VLSI Circuits - VLSIC
2004, pages 176179, June 2004.
[7] Maes, R. Physically Unclonable Functions: Constructions, Properties
and Applications. PhD thesis, KU Leuven, 2012.
[8] Maes, R., Tuyls, P., Verbauwhede, I. Intrinsic PUFs from Flip-ops
on Recongurable Devices. In Benelux Workshop on Information and
System Security - WISSec 2008. Eindhoven, NL, 2008.
[9] Maiti, A., Schaumont, P. Improving the Quality of a Physical Unclonable
Function Using Congurable Ring Oscillators. In International Conference on Field Programmable Logic and Applications - FPL 2009, pages
703707, September 2009.
[10] Pappu, R. S. Physical One-Way Functions. Ph.D. thesis. Massachusetts
Institute of Technology, MA, USA, 2001.
[11] Platonov, M., Hlavac , J., Lorencz, R. Using Power-up SRAM State of
Atmel ATmega1284P Microcontrollers as Physical Unclonable Function
for Key Generation and Chip Identication. In The rst workshop on
Trustworthy manufacturing and utilization of secure devices TRUDEVICE 2013. Avignon, France, May 2013.
[12] Su, Y., Holleman, J., Otis, B. A 1.6pJ/bit 96% Stable Chip-ID Generating
Circuit using Process Variations. In IEEE International Solid-State
Circuits Conference - ISSCC 2007, pages 406611. IEEE, February
2007.
[13] Suh, G. E., Devadas, S. Physical Unclonable Functions for Device
Authentication and Secret Key Generation. In Design Automation Conference - DAC 2007, pages 914. ACM, New York, NY, USA, 2007.
[14] Suzuki, D., Shimizu, K. The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes. In Workshop on Cryptographic Hardware
and Embedded Systems - CHES 2010, pages 366382. Springer, 2010.

TABLE III
T HE STABILITY OF RESPONSES DURING DIFFERENT TEMPERATURE .

very small. Such bit positions, that fullll these requirements

are for example positions 78.
A. Inuence of temperature
The behavior of positions 78 was observed under different
temperatures. Due to limited possibilities, we executed these
measurements on 3 FPGAs only. The measurements were
performed for 450 pairs of ROs with 500 measurements for
each pair.
As we can see in Table III, BER and HDintra increases
due to temperature change, meaning that more errors occur
in PUF responses. There are also the results for each of the
temperatures separately. BER and HDintra are really small
and they are very close to the ideal 0%, if we calculate
them for PUF responses measured at stabilized temperature.
This implies, that even though the previous measurements
were performed under xed environmental conditions (stable
temperature), the temperature on all FPGAs increased during
the measurements, therefore the calculated values of BER and
HDintra were higher. This temperature variation is caused by
the ROs themselves.
V. C ONCLUSION
In this paper, we proposed RO based PUF, which is able
to provide more output bits from each RO pair and is not
dependent on the symmetry of ROs, implying that it is easy
to implement and that there are no restrictions for placement of
ROs. This ROPUF design selects suitable bits for PUF from
counter values obtained from the measurements on various
RO pairs. These positions are selected accordingly by their
entropy and stability. Using the proposed technique, we are
able to obtain more bits from each RO pair, therefore we can
produce longer PUF output.
According to the results, we can see that this ROPUF design
is suitable for FPGAs. All measurements were executed on 24
Digilent Basys 2 FPGA boards and statistically evaluated. We
made these measurements on the circuit with 300 ROs and

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