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SMR: 1977

First ICTP Regional Microelectronics Workshop


and Training on VHDL for Hardware Synthesis
and FPGA Design in Asia-Pacific
16 June 2008 - 11 July 2008
Kuala Lumpur - MALAYSIA
___________________________________________________________________

LABORATORY EXERCISES

Prepared and Edited by:


ICTP Multidisciplinary Laboratory
MLAB

Exercise1CombinationalCircuits
Giventhedatasheetscorrespondingtothefollowingdigitalcircuits:
1.1 Quadruple2InputExclusiveOrGates(CD54ACT86,TexasInstruments).
1.2 4BitMagnitudeComparator(74F85,PhilipsSemiconductors).
1.3 OctalBidirectionalBusTransceiver(SN54AHC245,TexasInstruments).
a) CreateandSimulateVHDLBehaviouralDescriptions(entityarchitecture).
b) DesignandSimulatea12BitMagnitudeComparatorusingacascadeofthree74F854
BitMagnitudeComparators.

Exercise2SequentialCircuits
Giventhedatasheetscorrespondingtothefollowingdigitalcircuits:
2.1 DualFlipFlop(HEF4013B,PhilipsSemiconductors).
2.2 ParallelLoad 8Bit Shift Register (ParallelIn SerialOut SN54LV165A, Texas
Instruments).
2.3 8BitShiftRegister withOutputRegister (SerialInParallelOut SN54LV594A,Texas
Instruments).
2.4 Synchronous 4Bit Up/Down Binary Presettable Counter (SN54AS169A, Texas
Instruments).
a)CreateandSimulateVHDLBehavioralDescriptions.

Exercise3FiniteStateMachine

DesignandsimulateaFourConsecutiveOnesDetectoraccordingtothefollowingtoplevel
schematicandfunctionaldescription:

INPUT
CLK

OUTPUT

RESET

Fig.1

Toplevelschematic

TheOUTPUTgoeshighonlywhentheINPUTissampled 1duringfourconsecutive
risingedgesoftheCLKandremainshightilltheINPUTbecomes0.Thecomponentis
asynchronouslyinitializedwithanactivehighRESET.

Exercise4DesignSimulationandSynthesis
4.1Aparkinglot,shownintheFig.2,hasspacefor10cars.Thereisonlyoneentrancetothe
parkinglot,consequentlyonecaratatimecanenterorexittheparking.Therearetwo
lightsensors,separatedbyonemeterinordertodetectifthecarisenteringorleavingthe
lot.ThereisasemaphorewithsignssayingFREEandFULL.

P
ligth

detector 1

'0'

ligth

detector 2

'1'

Fig.2ParkingLot

a)CreateandsimulateaVHDLdescriptiontocorrectlycommandthelightsaccordingto
theoccupancyoftheparkinglot.
b)Synthesizethedesignandsimulate(PostSynthesisSimulation).
4.2Thesameaspreviousexerciseexceptthatthereareanentranceandanexitgate,therefore
youmustsynchronizetheparallelactivitiesusinganentranceandanexitsemaphore.

Exercise5DesignSynthesisandImplementation
Design,SynthesizeandImplementontheProASIC3LCEvaluationBoard(A3P250PQ208
FPGA)aClockDividerSelectorthatallowsgenerating1Hz,2Hz,5Hzand10Hzclocks
fromtheonboard40MHzclock.
a)Usethegivenphysicaldesignconstraintfileforpinassignment.
b)UsetheonboardLEDsofbank1(IO_BANK1)toshowthegeneratedclock.
c)Usetheonboarddipswitchesofbank2(IO_BANK2)toselecttheclockdivider.

Exercise6DesignSynthesisandImplementation
SynthesizeandImplementontheProASIC3LCEvaluationBoard(A3P250PQ208FPGA)
theSerialInParallelOut8BitShiftRegister(SN54LV594A)designedinexercise2.
a)Usethegivenphysicaldesignconstraintfileforpinassignment.
b)Inputs:

shiftregisterinputclockisa2Hzclockgeneratedfromtheonboard40MHz
clock.

shiftregisterserialinputcomesfromKEY1onboardpushbutton(COL1=0).

shiftregisterclearcomesfromRESETonboardpushbutton(SW5).

c)Outputs:

shift register outputs are connected to the onboard LEDs of bank 1


(IO_BANK1).

Exercise7DesignSynthesisandImplementation
SynthesizeandImplementontheProASIC3LCEvaluationBoard(A3P250PQ208FPGA)
the4BitUp/DownBinaryPresettableCounter(SN54AS169A)designedinexercise2.
a)Usethegivenphysicaldesignconstraintfileforpinassignment.
b)Inputs:
counterinputclockisa2Hzclockgeneratedfromtheonboard40MHzclock.
initialvalueloadcomesfromKEY1onboardpushbutton(COL1=0).
counter data inputs come from the onboard dipswitches of bank 2
(IO_BANK2[3downto0])
up/downselectorcomesfromKEY2onboardpushbutton(COL1=0).
counting enable inputs come from the onboard dipswitches of bank 2
(IO_BANK2[7](ENP)andIO_BANK2[6](ENT)).
c)Outputs:

counterdataoutputsandripplecarryoutputareconnectedtotheonboard
LEDsofbank1(IO_BANK1).

Exercise8VHDLPackagesandStructuralDesign
a) Buildyourownpackage including,atleast, thefollowingtwocomponents: theClock
Divider Selector designed in exercise 5, and the 4Bit Up/Down Binary Presettable
Counterdesignedinexercise2.
b)CreateaVHDLStructuraldescription,usingyourpacket,forthe 4BitUp/DownBinary
PresettableCounter(SN54AS169A).SynthesizeandImplementthedesignfollowingthe
recommendationsgiveninexercise7.

Exercise9DigitalArithmetic
a) DesignasimpleArithmeticLogicUnitthatasynchronouslyperformssum,subtraction
andmultiplicationoperationswithinteger,signedandunsignedoperands.Theoperands
(inputs)aretwo8bitvectorsandtheresult(output)isa16bitvector(truncatedintotwo
8bit registers). Operands type (integer, unsigned or signed) and operation type (sum,
subtractionormultiplication)arealsoinputs.Operands,operandstypeandoperationtype
aregivenbytheuser.
b) SynthesiseandImplementthedesignontheProASIC3LCEvaluationBoard(A3P250
PQ208FPGA)usingtheonboardLEDs,dipswitchesandpushbuttonstoreadoperands
andtypeofoperandsandoperation,andtowritetheresultoftheoperation.

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