BHEEMA INSTITUTE OF TECHNOLOGY & SCIENCE

ALUR (ROAD), ADONI-518301, KURNOOL (DIST), A.P.

II-Mid Internal Examination [Theory Type]: Academic Year 2016-17
Year: II - B. Tech I Semester
Subject Name: STLD

Regd. No: .

Answer any 3 of the following Questions

Branch: ECE
Max. Marks: 30
3 x 10= 30 M

1. Simplify the Boolean function by using Q-M method F(ABCD)=m(0,2,3,6,7,8,10,12,13)

2. a) Reduce the following function using K-map technique.
F(A,B,C,D,E) = m(1,4,8,10,11,20,22,24,25,26)+d(0,12,16,17)
b) Design 4 Bit Binary Multiplier.
3. a) Explain about Magnitude Comparator.
b) Design 2-bit comparator using gates.
4. a) Draw the circuit for 3-to-8 Decoder and explain.
b) Construct and explain 4-to-16 Decoder using two 3-to-8 Decoders.
5. a) Write differences between combinational and sequential circuits.
b) Explain about S-R Flip-Flops.
6. Explain about following encoders.
a) Octal to Binary Encoder
b) Priority Encoder
7. Explain about following Converters.
a) Binary to BCD converter.
b) BCD to Excess-3 converter.
8. Draw and explain the working of following flip-flops.
a) RS b) Clocked RS c) D d) JK e) Clocked JK.
9. Write short notes on
a) Edge triggered flip-flop b) Master Slave flip-flop
10. Explain about Ring Counter and Shift Counter.
11. Comparison between PROM, PLA and PAL.
12. Illustrate how a PLA can be used for combinational logic design with reference to the functions:
F1 (a,b,c)= m(0,1,3,4)
F2 (a,b,c)= m(0,1,3,4,5)
Realize the same assuming, that a 3x4x2 PLA is available.
13. Illustrate how a PLA can be used for combinational logic design with reference to the functions:
F1 (a,b,c)= m(0,1,3,4)
F2 (a,b,c)= m(0,1,2,3,4,5)
Realize the same assuming, that a 3x4x2 PLA is available.
14. Illustrate how a PLA can be used for combinational logic design with reference to the functions:
F1 (a,b,c) = m(0,1,3,5)
F2 (a,b,c) = m(3,5,7)
Realize the same assuming, that a 3x4x2 PLA is available.
BHEEMA INSTITUTE OF TECHNOLOGY & SCIENCE
ALUR (ROAD), ADONI-518301, KURNOOL(DIST), A.P.
II-Mid Internal Examination [Objective Type]: Academic Year 2016-17
Year: II - B. Tech I Semester
Subject Name: STLD
Signature of Invigilator
Regd .No:

1. The dual of x + xy=x is

a) x + y b) x
c) x (x+y) =x d) (x+y) (x-y)=x
2. The dual of the exclusive OR gate is equal to
[
]
a) NAND gate b) X-OR gate c) X-NOR gate d)

Branch: ECE
Marks Obtained:
Maximum Marks:
10
Signature Of Examiner:

AND gate

3. The logic expression A-exclusive B is same as

a) AB+AB b)(A+B)(A+B) c)(A+B)(A+B) d)AB+(A+B)

4. Convert the following gray code 101101 to binary

a) 111011 b)011011 c)110110 d)010110
5. The number of cells in a 6-variabe K-map is
a) 6 b) 12 c) 36 d) 64
6. The Boolean expression X+XY=
a) X+Y b)X+XY c)Y+YX` d)XY+YX
7. Which of the following Boolean expression is incorrect ?
a) A+A=A+B b)A+AB=B c)(A+B)(A+C)=A=BC d)None
8. Solve A(A`+B)
a) AB b)A+B c)(AB)` d)(A+B)`
9. The minimum number of NAND gates required to realize X-OR gate are
a) 5
b) 4
c) 3
d) 6
10. Draw the logic diagram y=AB+CD+EF

11. The basic building blocks of combinational digital circuits are

a) Gates only b) Flip-Flops only c) Gate and Flip-Flops d) None
12. ROM is an example for
a) sequential circuit b) combinational circuit c)Both a and b d) None

13. The full adder can be implemented by using

a)Two half adders and one OR gate b)Two half adders and one AND gate
c)Only two half adders d)None
14. --------- number of selection lines are needed to implement 41 MUX

a)4 b)3 c)2 d)1

15. Decoder size can be defined as
a)12n b)2n1 c)n2n d)2nn
16. ------- gates are also called as universal gates
a) Only NAND gates b)Only NOR gates c) both a and b d)None
17. BCD to decimal decoder consists of ----inputs and -------outputs
[
]
a) Three, eight b) four, sixteen c) four , ten d) None
18. ((A)`)`=--------a) 0 b) 1 c) A d)None
19. Minimum number of NAND Gates required to realize half adder circuit
a) 4 b) 6 c) 5 d) 7
20. Minimum number of NAND Gates required to realize full adder circuit
a) 5
b) 7 c) 9 d) 10