Design for Testability (Test Generation)

Assignment #5
Due Date: Oct 14th, 2016
1) Describe the following:
a. Singular cover
b. Primitive D Cubes of Failure (PDF)
c. Propagation D Cube
2) Develop the singular cover, PDF (for a sa1 fault on one of the gate inputs) and
Propagation D Cube for the following gates:
a. 2 input NAND
b. 2 input NOR
c. 2 input AND
d. 2 input OR
e. 2 input XOR
3) For the circuit shown in Fig-1 compute the set of all test vectors that can detect each
of the following faults using Boolean difference.
a. e/0
b. e/1
c. c/0

Fig-1
4) For the circuit shown in Fig-2 use the D Algorithm to compute a test vector for the
fault b/1. Repeat for fault e/0.

Fig-2
5) For the same circuit shown in Fig-2 use the PODEM Algorithm to compute a test
vector for the fault b/1. Repeat for fault e/0.
6) Research and write a summary (max 1 page) of SOCRATES ATPG algorithm. Write
the summary in your own words (no cut & paste).