Design for Testability (Fault Simulation)

Assignment #4
Due Date: Oct 5th, 2016
1) For the circuit shown in Fig-1 perform serial fault simulation for 2 faults f (L s-a-1) and
g (H s-a-0). Start with any random test vector till you arrive at 2 set of test vectors
each for detecting faults at f and g. For serial fault simulation we consider one fault at
a time. Create a table (similar to Table 3.7 in the book) that lists the fault free circuit
and faulty circuit intermediate node results and test vectors.

Fig-1
2) For the same circuit in Fig-1, perform Parallel fault simulation to arrive at a test
pattern that can detect both faults. Create boxes to show bit-wise parallelism. Also
tabulate your results.
3) For the circuit shown in Fig-2 and two given stuck-at faults, use the parallel-pattern
single-fault propagation fault simulation (PPSFP) technique to identify which faults
can be detected by the given test patterns.

Fig-2

4) For the same circuit shown in Fig-2 perform deductive fault simulation and list all fault
lists for each node.
5) Create a table listing all possible Fault simulation techniques (covered in class) and
identify where they fit in terms of Speed, Memory footprint, Delay testing capabilities.
6) Which type of simulator will you use for:
(a) Verifying the architecture of a digital system
(b) Checking the design of an analog circuit
(c) Verifying the logic of an MOS bus
(d) Simulating the critical timing path of a large digital circuit, and
(e) Logic verification of a large digital circuit implemented with static CMOS gates.