Enriquez, Ma. Lynette C.

BSCpE V GF
1. Finite State Machine

Verilog Code for

FSM: (MOORE)
// 4-State Moore state machine
// A Moore machine's outputs are
dependent only on the current
state.
// The output is written only when
the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);
// Declare state register
reg
[2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2
= 2, S3 = 3, S4 = 4;
// Determine the next state
always @ (posedge clk or
posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:

if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or
posedge reset)
// Output depends only on the
state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac

Verilog Code for FSM: (MEALY)

FUNCTIONS
A. Moore: a Moore machine is a finite-state machine whose output values are
determined solely by its current state. This is in contrast to a Mealy machine, whose
output values are determined both by its current state and by the values of its inputs.
B. Mealy: a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. A Mealy machine is
a deterministic finite-state transducer: for each state and input, at most one transition
is possible.
2. Memory Blocks

Verilog Code:
module raminfr (clk, en, we, addr, di, do);
input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;

output [3:0] do;

reg [3:0] RAM [31:0];
reg [3:0] do;
always @(posedge clk)
begin
if (en) begin

if (we)
RAM[addr] <= di;

end
end
endmodule

do <= RAM[addr];

Functions:
The Memory block holds and delays its input by one major integration time step.
When placed in an iterator subsystem, it holds and delays its input by one iteration. This
block accepts continuous and discrete signals. The block accepts one input and
generates one output. Each signal can be scalar or vector. If the input is a vector, the
block holds and delays all elements of the vector by the same time step.
You specify the block output for the first time step using the Initial condition parameter.
Careful selection of this parameter can minimize unwanted output behavior. However,
you cannot specify the sample time. This block's sample time depends on the type of
solver used, or you can specify to inherit it. The Inherit sample time parameter
determines whether sample time is inherited or based on the solver.

System Overview:
3. Control Unit

Functions:
Control Unit (CU) is generally a sizable collection of complex digital circuitry
interconnecting and controlling the many execution units contained within a CPU. The
CU is normally the first CPU unit to accept from an externally stored computer program,
a single instruction. The CU then decodes this individual instruction into several
sequential that controls and coordinates the CPU's inner works to properly manipulate
the data. The design of these sequential steps are based on the needs of each
instruction and can range in number of steps, the order of execution, and which units are
enabled. Thus by only using a program of set instructions in memory, the CU will
configure all the CPU's data flows as needed to manipulate the data correctly between
instructions. This results in a computer that could run a complete program and requiring
no human intervention to make hardware changes between instructions (as had to be
done when using only punch cards for computations before stored programmed
computers with CUs where invented). These detailed steps from the CU dictate which of
the CPU's interconnecting hardware control signals to enable/disable or which CPU units
are selected/de-selected and the unit's proper order of execution as required by the
instruction's operation to produce the desired manipulated data.
4. MIPS Singlecycle Processor

Verilog Code

module PC(clk , instruction , zero ,

branch , jump , pc );

input clk ;

assign branchAdd = pcInc + ( branch <<

2);

input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;
wire[31:0] pcInc;
wire[31:0] Branch1 ;
wire[15:0] address;
wire[31:0] branchAdd;
reg[31:0] mux1;
wire select1 ;
wire[31:0] jumpAdd ;
output [31:0] pc ;
reg [31:0] pc ;

always@( branchAdd or pcInc or select1 )

begin
if ( select1 == 1 )
mux1 = branchAdd ;
else
mux1 = pcInc ;
end

assign select1 = branch & zero ;

assign pcInc = pc + 4 ;
assign address = instruction[15:0];
assign Branch1 =
{{16{address[15]}},address[15:0]} ; // sign
extension

assign jumpAdd = ( instruction[25:0] << 2 );

always@ ( jump or jumpAdd or mux1 )
begin
if ( jump == 1 )
npc = jumpAdd ;
else
npc = mux1;
end
always @(posedge clk )
pc <= npc;
endmodule

Functions:

MIPS Singlecycle Processor is a processor that carries out one instruction

in a single Clock cycle.

System Overview:

5. MIPS Multicycle Processor

Verilog Code:

module ALUControl(Opcode, ALUOp1, ALUOp0, Funct, Operation);

input ALUOp1, ALUOp0;
input [5:0] Funct, Opcode;
output [3:0] Operation;
reg [3:0] Operation;
always @ (ALUOp1, ALUOp0, Funct)
begin
if((ALUOp1==1'b0)&(ALUOp0==1'b0))
begin Operation <= 3'b010;
end
if(ALUOp0==1'b1) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0010;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0000;

end
if
((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0001;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b1)) begin Operation <= 4'b0111;

end

if

((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b1100;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0011;

end

if

(Opcode==6'b001000) begin //for add immediate Operation <= 4'b0010;

end

if

(Opcode==6'b001101) begin //for or immediate Operation <= 4'b0001;

end

if

(Opcode==6'b001100) begin // for andi Operation <= 4'b0000;

end

if

(Opcode==6'b001010) begin // for slti Operation <= 4'b0111;

end

end

endmodule

Functions:

break up instructions into separate steps

Each step takes a single clock cycle
Each functional unit can be used more than once in an instruction, as long as it is
used in different clock cycles
Reduces amount of hardware needed
Reduces average instruction time

6. 32 Bit ALU and test bench

Verilog Code

module logic_unit(d_out1,logic_u
nit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin

if(logic_unit== 1'b1)
begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 ==

1'b0)

begin

d_out1 = ( A | B);

end

else if(s0 == 1'b0 & s1 ==

1'b1) begind_out1 = ( A ^ B);
end

else

begin

d_out1 = ( A ^~ B);
end
end

else
begin

d_out1 = 4'b0000;

end

end
end

module`timescale 1ns / 1ps

module
arithmetic(d_out,A,B,cout,arithm
etic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;
input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always
@(s0,s1,c0,arithmetic_unit)
begin

if(arithmetic_unit)beginif(s1
== 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = A + 1'b1;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = D1;

cout = D0;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b1)
begin

d_out2 = D1 + 1'b1;

cout = D0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b0)
begin

d_out2 = L1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = L1 + 1'b1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = K1;

cout = K0;
end

else begin

d_out2 = K1 + 1'b1;

cout = K0;
end
end
else
begin

d_out2 = 4'b0000;
end
end

endmodule`timescale 1ns /
1ps
module
alu(CRY_OUT,DATA_OUT,CRY_
IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;

reg arithmetic_unit;
wire [3:0] DATA_OUT1;

wire [3:0] DATA_OUT2;

assign DATA_OUT = (MODE ?
DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(
DATA_OUT2),

.s0(SEL1),

.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),

.B(DATA_IN2),

.
logic_unit(logic_unit));
arithmetic
arithmetic_ins(.d_out(DATA_OU
T1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.
arithmetic_unit(arithmetic_unit));
always @(SEL1,SEL2,MODE)
begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;
end
else begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;
end
end
endmodule

7.

TEST BENCH FOR ALU:

8.
9. `timescale 1ns / 1ps
10.
module t_alu;
11.wire CRY_OUT;
12.
wire [3:0] DATA_OUT;
13.
reg CRY_IN;
14.
reg[3:0] DATA_IN1,DATA_IN2;
15.
reg SEL1,SEL2,MODE;
16.
alualu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
17.
initial
18.
begin
19.
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
20.
#500 SEL2 = 1'b0; SEL1 = 1'b0; CRY_IN = 1'b0;
21.
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
22.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
23.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
24.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
25.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
26.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
27.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
28.
#500 MODE = 1'b0;

29.
30.
31.
32.
33.
34.

#500 SEL1 = 1'b0; SEL2 = 1'b1;

#500 SEL1 = 1'b1; SEL2 = 1'b1;
#500 SEL1 = 1'b1; SEL2 = 1'b0;
#500 SEL1 = 1'b0; SEL2 = 1'b0;
End
Endmodule

35.

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55.
56.
57.
58. Titan, Jan Jennifer C.
59. BSCpE V-GF
1. Finite State Machine

Verilog Code for

FSM: (MOORE)
// 4-State Moore state machine
// A Moore machine's outputs are
dependent only on the current
state.
// The output is written only when
the state changes. (State
// transitions are synchronous.)
module seq_dect

(
input clk, data_in, reset,
output reg data_out
);
// Declare state register
reg
[2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2
= 2, S3 = 3, S4 = 4;
// Determine the next state

always @ (posedge clk or

posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
60.
61.
62.

if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;

63.
64.
65.
66.
67.

Verilog Code for FSM: (MEALY)

S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or
posedge reset)
// Output depends only on the
state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac

68.

FUNCTIONS
C. Moore: a Moore machine is a finite-state machine whose output values are
determined solely by its current state. This is in contrast to a Mealy machine, whose
output values are determined both by its current state and by the values of its inputs.
D. Mealy: a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. A Mealy machine is
a deterministic finite-state transducer: for each state and input, at most one transition
is possible.
69.
70.
2. Memory Blocks

Verilog Code:
71. module raminfr (clk, en, we, addr, di,
do);
72. input
clk;
73. input
we;
74. input
en;
75. input [4:0] addr;
76. input [3:0] di;
77. output [3:0] do;
78. reg [3:0] RAM [31:0];
79. reg [3:0] do;

80. always @(posedge clk)

81. begin
82. if (en) begin
83.
if (we)
84. RAM[addr] <= di;
85.
86.
do <= RAM[addr];
87. end
88. end
89.
endmodule

90.

Functions:
91.
The Memory block holds and delays its input by one major integration
time step. When placed in an iterator subsystem, it holds and delays its input by one
iteration. This block accepts continuous and discrete signals. The block accepts one
input and generates one output. Each signal can be scalar or vector. If the input is a
vector, the block holds and delays all elements of the vector by the same time step.
92.
You specify the block output for the first time step using the Initial
condition parameter. Careful selection of this parameter can minimize unwanted output
behavior. However, you cannot specify the sample time. This block's sample time
depends on the type of solver used, or you can specify to inherit it. The Inherit sample
time parameter determines whether sample time is inherited or based on the solver.

System Overview:
93.
3. Control Unit
94.

Functions:
95.
Control Unit (CU) is generally a sizable collection of complex digital
circuitry interconnecting and controlling the many execution units contained within a
CPU. The CU is normally the first CPU unit to accept from an externally stored computer
program, a single instruction. The CU then decodes this individual instruction into
several sequential that controls and coordinates the CPU's inner works to properly
manipulate the data. The design of these sequential steps are based on the needs of
each instruction and can range in number of steps, the order of execution, and which
units are enabled. Thus by only using a program of set instructions in memory, the CU
will configure all the CPU's data flows as needed to manipulate the data correctly
between instructions. This results in a computer that could run a complete program and
requiring no human intervention to make hardware changes between instructions (as
had to be done when using only punch cards for computations before stored
programmed computers with CUs where invented). These detailed steps from the CU
dictate which of the CPU's interconnecting hardware control signals to enable/disable or
which CPU units are selected/de-selected and the unit's proper order of execution as
required by the instruction's operation to produce the desired manipulated data.
96.
4. MIPS Singlecycle Processor

Verilog Code
97.
98. module PC(clk , instruction , zero ,
branch , jump , pc );
99. input clk ;
100.

101.
102.
103.
104.
105.
106.

input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;

107. wire[31:0] pcInc;

108. wire[31:0] Branch1 ;
109. wire[15:0] address;
110. wire[31:0] branchAdd;
111. reg[31:0] mux1;
112. wire select1 ;
113. wire[31:0] jumpAdd ;
114. output [31:0] pc ;
115. reg [31:0] pc ;
116.
117.
118. assign select1 = branch & zero ;
119. assign pcInc = pc + 4 ;
120. assign address = instruction[15:0];
121. assign Branch1 =
{{16{address[15]}},address[15:0]} ; //
sign extension
122. assign branchAdd = pcInc + ( branch
<< 2 ) ;
123.
124. always@( branchAdd or pcInc or
select1 )

125. begin
126.
if ( select1 == 1 )
127.
mux1 = branchAdd ;
128.
else
129.
mux1 = pcInc ;
130. end
131.
132. assign jumpAdd = ( instruction[25:0]
<< 2 );
133.
134. always@ ( jump or jumpAdd or
mux1 )
135. begin
136.
if ( jump == 1 )
137.
npc = jumpAdd ;
138.
else
139.
npc = mux1;
140. end
141.
142. always @(posedge clk )
143.
pc <= npc;
144. endmodule

Functions:

MIPS Singlecycle Processor is a processor that carries out one instruction

in a single Clock cycle.

System Overview:

5. MIPS Multicycle Processor

Verilog Code:

module ALUControl(Opcode, ALUOp1, ALUOp0, Funct, Operation);

input ALUOp1, ALUOp0;
input [5:0] Funct, Opcode;
output [3:0] Operation;
reg [3:0] Operation;
always @ (ALUOp1, ALUOp0, Funct)
begin
if((ALUOp1==1'b0)&(ALUOp0==1'b0))
begin Operation <= 3'b010;
end
if(ALUOp0==1'b1) begin Operation <= 4'b0110;
end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0010;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0000;

end
if
((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0001;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b1)) begin Operation <= 4'b0111;

end

if

((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b1100;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0011;

end

if

(Opcode==6'b001000) begin //for add immediate Operation <= 4'b0010;

end

if

(Opcode==6'b001101) begin //for or immediate Operation <= 4'b0001;

end

if

(Opcode==6'b001100) begin // for andi Operation <= 4'b0000;

end

if

(Opcode==6'b001010) begin // for slti Operation <= 4'b0111;

end

end

endmodule

Functions:

break up instructions into separate steps

Each step takes a single clock cycle
Each functional unit can be used more than once in an instruction, as long as it is
used in different clock cycles
Reduces amount of hardware needed
Reduces average instruction time

6. 32 Bit ALU and test bench

Verilog Code

module logic_unit(d_out1,logic_u
nit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin

if(logic_unit== 1'b1)
begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 ==

1'b0)

begin

d_out1 = ( A | B);
end

else if(s0 == 1'b0 & s1 ==

1'b1) begind_out1 = ( A ^ B);
end

else

begin

d_out1 = ( A ^~ B);
end
end

else
begin

d_out1 = 4'b0000;

end

end
end

module`timescale 1ns / 1ps

module
arithmetic(d_out,A,B,cout,arithm
etic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;

input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always
@(s0,s1,c0,arithmetic_unit)
begin

if(arithmetic_unit)beginif(s1
== 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = A + 1'b1;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = D1;

cout = D0;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b1)
begin

d_out2 = D1 + 1'b1;

cout = D0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b0)
begin

d_out2 = L1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = L1 + 1'b1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = K1;

cout = K0;
end

else begin

d_out2 = K1 + 1'b1;

cout = K0;
end
end
else
begin

d_out2 = 4'b0000;
end
end

endmodule`timescale 1ns /
1ps
module
alu(CRY_OUT,DATA_OUT,CRY_
IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;

reg arithmetic_unit;
wire [3:0] DATA_OUT1;
wire [3:0] DATA_OUT2;
assign DATA_OUT = (MODE ?
DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(
DATA_OUT2),

.s0(SEL1),


.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),

.B(DATA_IN2),

.
logic_unit(logic_unit));
arithmetic
arithmetic_ins(.d_out(DATA_OU
T1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.
arithmetic_unit(arithmetic_unit));
always @(SEL1,SEL2,MODE)
begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;
end
else begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;
end
end
endmodule

7.

TEST BENCH FOR ALU:

8.
9. `timescale 1ns / 1ps
10.
module t_alu;
11.wire CRY_OUT;
12.
wire [3:0] DATA_OUT;
13.
reg CRY_IN;
14.
reg[3:0] DATA_IN1,DATA_IN2;
15.
reg SEL1,SEL2,MODE;
16.
alualu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
17.
initial
18.
begin
19.
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
20.
#500 SEL2 = 1'b0; SEL1 = 1'b0; CRY_IN = 1'b0;
21.
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
22.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
23.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
24.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
25.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
26.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
27.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
28.
#500 MODE = 1'b0;
29.
#500 SEL1 = 1'b0; SEL2 = 1'b1;
30.
#500 SEL1 = 1'b1; SEL2 = 1'b1;
31.
#500 SEL1 = 1'b1; SEL2 = 1'b0;
32.
#500 SEL1 = 1'b0; SEL2 = 1'b0;

33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.

End
Endmodule

65. Badillo, Gee-ann.

66. BSCpE V GF
145. Finite State Machine

Verilog Code for

FSM: (MOORE)
// 4-State Moore state machine
// A Moore machine's outputs are
dependent only on the current
state.
// The output is written only when
the state changes. (State
// transitions are synchronous.)
module seq_dect

(
input clk, data_in, reset,
output reg data_out
);
// Declare state register
reg
[2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2
= 2, S3 = 3, S4 = 4;
// Determine the next state

always @ (posedge clk or

posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
67.
68.
69.

if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;

70.
71.
72.
73.
74.

Verilog Code for FSM: (MEALY)

S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or
posedge reset)
// Output depends only on the
state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac

75.

FUNCTIONS
E. Moore: a Moore machine is a finite-state machine whose output values are
determined solely by its current state. This is in contrast to a Mealy machine, whose
output values are determined both by its current state and by the values of its inputs.
F. Mealy: a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. A Mealy machine is
a deterministic finite-state transducer: for each state and input, at most one transition
is possible.
76.
77.
146. Memory Blocks

Verilog Code:
78. module raminfr (clk, en, we, addr, di,
do);
79. input
clk;
80. input
we;
81. input
en;
82. input [4:0] addr;
83. input [3:0] di;
84. output [3:0] do;
85. reg [3:0] RAM [31:0];
86. reg [3:0] do;

87. always @(posedge clk)

88. begin
89. if (en) begin
90.
if (we)
91. RAM[addr] <= di;
92.
93.
do <= RAM[addr];
94. end
95. end
96.
endmodule

97.

Functions:
98.
The Memory block holds and delays its input by one major integration
time step. When placed in an iterator subsystem, it holds and delays its input by one
iteration. This block accepts continuous and discrete signals. The block accepts one
input and generates one output. Each signal can be scalar or vector. If the input is a
vector, the block holds and delays all elements of the vector by the same time step.
99.
You specify the block output for the first time step using the Initial
condition parameter. Careful selection of this parameter can minimize unwanted output
behavior. However, you cannot specify the sample time. This block's sample time
depends on the type of solver used, or you can specify to inherit it. The Inherit sample
time parameter determines whether sample time is inherited or based on the solver.

System Overview:
100.
147. Control Unit
101.

Functions:
102. Control Unit (CU) is generally a sizable collection of complex digital
circuitry interconnecting and controlling the many execution units contained within a
CPU. The CU is normally the first CPU unit to accept from an externally stored computer
program, a single instruction. The CU then decodes this individual instruction into
several sequential that controls and coordinates the CPU's inner works to properly
manipulate the data. The design of these sequential steps are based on the needs of
each instruction and can range in number of steps, the order of execution, and which
units are enabled. Thus by only using a program of set instructions in memory, the CU
will configure all the CPU's data flows as needed to manipulate the data correctly
between instructions. This results in a computer that could run a complete program and
requiring no human intervention to make hardware changes between instructions (as
had to be done when using only punch cards for computations before stored
programmed computers with CUs where invented). These detailed steps from the CU
dictate which of the CPU's interconnecting hardware control signals to enable/disable or
which CPU units are selected/de-selected and the unit's proper order of execution as
required by the instruction's operation to produce the desired manipulated data.
103.
148. MIPS Singlecycle Processor

Verilog Code
104.
105.
module PC(clk , instruction ,
zero , branch , jump , pc );
106.
input clk ;
107.

108.
109.
110.
111.
112.
113.

input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;

114.
wire[31:0] pcInc;
115.
wire[31:0] Branch1 ;
116.
wire[15:0] address;
117.
wire[31:0] branchAdd;
118.
reg[31:0] mux1;
119.
wire select1 ;
120.
wire[31:0] jumpAdd ;
121.
output [31:0] pc ;
122.
reg [31:0] pc ;
123.
124.
125.
assign select1 = branch &
zero ;
126.
assign pcInc = pc + 4 ;
127.
assign address =
instruction[15:0];
128.
assign Branch1 =
{{16{address[15]}},address[15:0]} ; /
/ sign extension
129.
assign branchAdd = pcInc + (
branch << 2 ) ;
130.
131.
always@( branchAdd or
pcInc or select1 )

132.
begin
133.
if ( select1 == 1 )
134.
mux1 = branchAdd ;
135.
else
136.
mux1 = pcInc ;
137.
end
138.
139.
assign jumpAdd =
( instruction[25:0] << 2 );
140.
141.
always@ ( jump or jumpAdd
or mux1 )
142.
begin
143.
if ( jump == 1 )
144.
npc = jumpAdd ;
145.
else
146.
npc = mux1;
147.
end
148.
149.
always @(posedge clk )
150.
pc <= npc;
151.
endmodule

Functions:

MIPS Singlecycle Processor is a processor that carries out one instruction

in a single Clock cycle.

System Overview:

149. MIPS Multicycle Processor

Verilog Code:

module ALUControl(Opcode, ALUOp1, ALUOp0, Funct, Operation);

input ALUOp1, ALUOp0;
input [5:0] Funct, Opcode;
output [3:0] Operation;
reg [3:0] Operation;
always @ (ALUOp1, ALUOp0, Funct)
begin
if((ALUOp1==1'b0)&(ALUOp0==1'b0))
begin Operation <= 3'b010;
end
if(ALUOp0==1'b1) begin Operation <= 4'b0110;
end

if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0010;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0000;

end
if
((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0001;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b1)) begin Operation <= 4'b0111;

end

if

((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b1100;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0011;

end

if

(Opcode==6'b001000) begin //for add immediate Operation <= 4'b0010;

end

if

(Opcode==6'b001101) begin //for or immediate Operation <= 4'b0001;

end

if

(Opcode==6'b001100) begin // for andi Operation <= 4'b0000;

end

if

(Opcode==6'b001010) begin // for slti Operation <= 4'b0111;

end

end

endmodule

Functions:

break up instructions into separate steps

Each step takes a single clock cycle
Each functional unit can be used more than once in an instruction, as long as it is
used in different clock cycles
Reduces amount of hardware needed
Reduces average instruction time

150. 32 Bit ALU and test bench

Verilog Code

module logic_unit(d_out1,logic_u
nit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin

if(logic_unit== 1'b1)
begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 ==

1'b0)

begin

d_out1 = ( A | B);

end

else if(s0 == 1'b0 & s1 ==

1'b1) begind_out1 = ( A ^ B);
end

else

begin

d_out1 = ( A ^~ B);
end
end

else
begin

d_out1 = 4'b0000;

end

end
end

module`timescale 1ns / 1ps

module
arithmetic(d_out,A,B,cout,arithm
etic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;
input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always
@(s0,s1,c0,arithmetic_unit)
begin

if(arithmetic_unit)beginif(s1
== 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = A + 1'b1;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = D1;

cout = D0;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b1)
begin

d_out2 = D1 + 1'b1;

cout = D0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b0)
begin

d_out2 = L1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = L1 + 1'b1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = K1;

cout = K0;
end

else begin

d_out2 = K1 + 1'b1;

cout = K0;
end
end
else
begin

d_out2 = 4'b0000;
end
end

endmodule`timescale 1ns /
1ps
module
alu(CRY_OUT,DATA_OUT,CRY_
IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;

reg arithmetic_unit;
wire [3:0] DATA_OUT1;

wire [3:0] DATA_OUT2;

assign DATA_OUT = (MODE ?
DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(
DATA_OUT2),

.s0(SEL1),

.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),

.B(DATA_IN2),

.
logic_unit(logic_unit));
arithmetic
arithmetic_ins(.d_out(DATA_OU
T1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.
arithmetic_unit(arithmetic_unit));
always @(SEL1,SEL2,MODE)
begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;
end
else begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;
end
end
endmodule

151.

TEST BENCH FOR ALU:

152.
153.
`timescale 1ns / 1ps
154.
module t_alu;
155.
wire CRY_OUT;
156.
wire [3:0] DATA_OUT;
157.
reg CRY_IN;
158.
reg[3:0] DATA_IN1,DATA_IN2;
159.
reg SEL1,SEL2,MODE;
160.
alualu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
161.
initial
162.
begin
163.
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
164.
#500 SEL2 = 1'b0; SEL1 = 1'b0; CRY_IN = 1'b0;
165.
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
166.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
167.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
168.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
169.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
170.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
171.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
172.
#500 MODE = 1'b0;

173.
174.
175.
176.
177.
178.
179.
180.
181.
182.

#500 SEL1 = 1'b0; SEL2 = 1'b1;

#500 SEL1 = 1'b1; SEL2 = 1'b1;
#500 SEL1 = 1'b1; SEL2 = 1'b0;
#500 SEL1 = 1'b0; SEL2 = 1'b0;
End
Endmodule

183.
184.
185.
186.
187.
188.
189.

190. Anonuevo, Peniel L.

191. BSCpE V GF
1. Finite State Machine

if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:

Verilog Code for

FSM: (MOORE)
// 4-State Moore state machine
// A Moore machine's outputs are
dependent only on the current
state.
// The output is written only when
the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);
// Declare state register
reg
[2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2
= 2, S3 = 3, S4 = 4;
// Determine the next state
always @ (posedge clk or
posedge reset) begin

192.
193.
194.

if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)

state <= S4;

else
state <= S2;
S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or
posedge reset)
// Output depends only on the
state
always @ (state) begin
case (state)
S0:
195.
196.
197.
198.
199.

Verilog Code for FSM: (MEALY)

data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac

200.

FUNCTIONS
G. Moore: a Moore machine is a finite-state machine whose output values are
determined solely by its current state. This is in contrast to a Mealy machine, whose
output values are determined both by its current state and by the values of its inputs.
H. Mealy: a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. A Mealy machine is
a deterministic finite-state transducer: for each state and input, at most one transition
is possible.
201.
202.
2. Memory Blocks

Verilog Code:
203. module raminfr (clk, en, we, addr, di,
do);
204. input
clk;
205. input
we;
206. input
en;
207. input [4:0] addr;
208. input [3:0] di;
209. output [3:0] do;
210. reg [3:0] RAM [31:0];
211. reg [3:0] do;

212.
213.
214.
215.
216.
217.
218.
219.
220.
221.

always @(posedge clk)

begin
if (en) begin
if (we)
RAM[addr] <= di;
do <= RAM[addr];
end
end
endmodule

222.

Functions:
223. The Memory block holds and delays its input by one major integration
time step. When placed in an iterator subsystem, it holds and delays its input by one
iteration. This block accepts continuous and discrete signals. The block accepts one
input and generates one output. Each signal can be scalar or vector. If the input is a
vector, the block holds and delays all elements of the vector by the same time step.
224. You specify the block output for the first time step using the Initial
condition parameter. Careful selection of this parameter can minimize unwanted output
behavior. However, you cannot specify the sample time. This block's sample time
depends on the type of solver used, or you can specify to inherit it. The Inherit sample
time parameter determines whether sample time is inherited or based on the solver.

System Overview:
225.
3. Control Unit
226.

Functions:
227. Control Unit (CU) is generally a sizable collection of complex digital
circuitry interconnecting and controlling the many execution units contained within a
CPU. The CU is normally the first CPU unit to accept from an externally stored computer
program, a single instruction. The CU then decodes this individual instruction into
several sequential that controls and coordinates the CPU's inner works to properly
manipulate the data. The design of these sequential steps are based on the needs of
each instruction and can range in number of steps, the order of execution, and which
units are enabled. Thus by only using a program of set instructions in memory, the CU
will configure all the CPU's data flows as needed to manipulate the data correctly
between instructions. This results in a computer that could run a complete program and
requiring no human intervention to make hardware changes between instructions (as
had to be done when using only punch cards for computations before stored
programmed computers with CUs where invented). These detailed steps from the CU
dictate which of the CPU's interconnecting hardware control signals to enable/disable or
which CPU units are selected/de-selected and the unit's proper order of execution as
required by the instruction's operation to produce the desired manipulated data.
228.
4. MIPS Singlecycle Processor

Verilog Code
229.
230. module PC(clk , instruction , zero ,
branch , jump , pc );
231. input clk ;
232.

233.
234.
235.
236.
237.
238.

input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;

239. wire[31:0] pcInc;

240. wire[31:0] Branch1 ;
241. wire[15:0] address;
242. wire[31:0] branchAdd;
243. reg[31:0] mux1;
244. wire select1 ;
245. wire[31:0] jumpAdd ;
246. output [31:0] pc ;
247. reg [31:0] pc ;
248.
249.
250. assign select1 = branch & zero ;
251. assign pcInc = pc + 4 ;
252. assign address = instruction[15:0];
253. assign Branch1 =
{{16{address[15]}},address[15:0]} ; //
sign extension
254. assign branchAdd = pcInc + ( branch
<< 2 ) ;
255.
256. always@( branchAdd or pcInc or
select1 )

257. begin
258.
if ( select1 == 1 )
259.
mux1 = branchAdd ;
260.
else
261.
mux1 = pcInc ;
262. end
263.
264. assign jumpAdd = ( instruction[25:0]
<< 2 );
265.
266. always@ ( jump or jumpAdd or
mux1 )
267. begin
268.
if ( jump == 1 )
269.
npc = jumpAdd ;
270.
else
271.
npc = mux1;
272. end
273.
274. always @(posedge clk )
275.
pc <= npc;
276. endmodule

Functions:

MIPS Singlecycle Processor is a processor that carries out one instruction

in a single Clock cycle.

System Overview:

5. MIPS Multicycle Processor

Verilog Code:

module ALUControl(Opcode, ALUOp1, ALUOp0, Funct, Operation);

input ALUOp1, ALUOp0;
input [5:0] Funct, Opcode;
output [3:0] Operation;
reg [3:0] Operation;
always @ (ALUOp1, ALUOp0, Funct)
begin
if((ALUOp1==1'b0)&(ALUOp0==1'b0))
begin Operation <= 3'b010;
end
if(ALUOp0==1'b1) begin Operation <= 4'b0110;
end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0010;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0000;

end
if
((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0001;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b1)) begin Operation <= 4'b0111;

end

if

((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b1100;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0011;

end

if

(Opcode==6'b001000) begin //for add immediate Operation <= 4'b0010;

end

if

(Opcode==6'b001101) begin //for or immediate Operation <= 4'b0001;

end

if

(Opcode==6'b001100) begin // for andi Operation <= 4'b0000;

end

if

(Opcode==6'b001010) begin // for slti Operation <= 4'b0111;

end

end

endmodule

Functions:

break up instructions into separate steps

Each step takes a single clock cycle
Each functional unit can be used more than once in an instruction, as long as it is
used in different clock cycles
Reduces amount of hardware needed
Reduces average instruction time

6. 32 Bit ALU and test bench

Verilog Code

module logic_unit(d_out1,logic_u
nit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin

if(logic_unit== 1'b1)
begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 ==

1'b0)

begin

d_out1 = ( A | B);
end

else if(s0 == 1'b0 & s1 ==

1'b1) begind_out1 = ( A ^ B);
end

else

begin

d_out1 = ( A ^~ B);
end
end

else
begin

d_out1 = 4'b0000;

end

end
end

module`timescale 1ns / 1ps

module
arithmetic(d_out,A,B,cout,arithm
etic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;

input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always
@(s0,s1,c0,arithmetic_unit)
begin

if(arithmetic_unit)beginif(s1
== 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = A + 1'b1;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = D1;

cout = D0;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b1)
begin

d_out2 = D1 + 1'b1;

cout = D0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b0)
begin

d_out2 = L1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = L1 + 1'b1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = K1;

cout = K0;
end

else begin

d_out2 = K1 + 1'b1;

cout = K0;
end
end
else
begin

d_out2 = 4'b0000;
end
end

endmodule`timescale 1ns /
1ps
module
alu(CRY_OUT,DATA_OUT,CRY_
IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;

reg arithmetic_unit;
wire [3:0] DATA_OUT1;
wire [3:0] DATA_OUT2;
assign DATA_OUT = (MODE ?
DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(
DATA_OUT2),

.s0(SEL1),


.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),

.B(DATA_IN2),

.
logic_unit(logic_unit));
arithmetic
arithmetic_ins(.d_out(DATA_OU
T1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.
arithmetic_unit(arithmetic_unit));
always @(SEL1,SEL2,MODE)
begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;
end
else begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;
end
end
endmodule

7.

TEST BENCH FOR ALU:

8.
9. `timescale 1ns / 1ps
10.
module t_alu;
11.wire CRY_OUT;
12.
wire [3:0] DATA_OUT;
13.
reg CRY_IN;
14.
reg[3:0] DATA_IN1,DATA_IN2;
15.
reg SEL1,SEL2,MODE;
16.
alualu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
17.
initial
18.
begin
19.
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
20.
#500 SEL2 = 1'b0; SEL1 = 1'b0; CRY_IN = 1'b0;
21.
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
22.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
23.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
24.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
25.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
26.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
27.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
28.
#500 MODE = 1'b0;
29.
#500 SEL1 = 1'b0; SEL2 = 1'b1;
30.
#500 SEL1 = 1'b1; SEL2 = 1'b1;
31.
#500 SEL1 = 1'b1; SEL2 = 1'b0;
32.
#500 SEL1 = 1'b0; SEL2 = 1'b0;

33.
34.
35.

End
Endmodule

36.

37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58. Hepana, Jerome V.
59. BSCpE V GF
1. Finite State Machine

Verilog Code for

FSM: (MOORE)
// 4-State Moore state machine
// A Moore machine's outputs are
dependent only on the current
state.
// The output is written only when
the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);

// Declare state register

reg
[2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2
= 2, S3 = 3, S4 = 4;
// Determine the next state
always @ (posedge clk or
posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)

state <= S1;

else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
60.
61.
62.

if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else

63.
64.
65.
66.
67.

Verilog Code for FSM: (MEALY)

state <= S2;

endcase // case (state)
end // always @ (posedge clk or
posedge reset)
// Output depends only on the
state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac

68.

FUNCTIONS
I.

Moore: a Moore machine is a finite-state machine whose output values are

determined solely by its current state. This is in contrast to a Mealy machine, whose
output values are determined both by its current state and by the values of its inputs.
J. Mealy: a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. A Mealy machine is
a deterministic finite-state transducer: for each state and input, at most one transition
is possible.
69.
70.
2. Memory Blocks

Verilog Code:
71. module raminfr (clk, en, we, addr, di,
do);
72. input
clk;
73. input
we;
74. input
en;
75. input [4:0] addr;
76. input [3:0] di;
77. output [3:0] do;
78. reg [3:0] RAM [31:0];
79. reg [3:0] do;

80. always @(posedge clk)

81. begin
82. if (en) begin
83.
if (we)
84. RAM[addr] <= di;
85.
86.
do <= RAM[addr];
87. end
88. end
89.
endmodule

90.

Functions:
91.
The Memory block holds and delays its input by one major integration
time step. When placed in an iterator subsystem, it holds and delays its input by one
iteration. This block accepts continuous and discrete signals. The block accepts one
input and generates one output. Each signal can be scalar or vector. If the input is a
vector, the block holds and delays all elements of the vector by the same time step.
92.
You specify the block output for the first time step using the Initial
condition parameter. Careful selection of this parameter can minimize unwanted output
behavior. However, you cannot specify the sample time. This block's sample time
depends on the type of solver used, or you can specify to inherit it. The Inherit sample
time parameter determines whether sample time is inherited or based on the solver.

System Overview:
93.
3. Control Unit
94.

Functions:
95.
Control Unit (CU) is generally a sizable collection of complex digital
circuitry interconnecting and controlling the many execution units contained within a
CPU. The CU is normally the first CPU unit to accept from an externally stored computer
program, a single instruction. The CU then decodes this individual instruction into
several sequential that controls and coordinates the CPU's inner works to properly
manipulate the data. The design of these sequential steps are based on the needs of
each instruction and can range in number of steps, the order of execution, and which
units are enabled. Thus by only using a program of set instructions in memory, the CU
will configure all the CPU's data flows as needed to manipulate the data correctly
between instructions. This results in a computer that could run a complete program and
requiring no human intervention to make hardware changes between instructions (as
had to be done when using only punch cards for computations before stored
programmed computers with CUs where invented). These detailed steps from the CU
dictate which of the CPU's interconnecting hardware control signals to enable/disable or
which CPU units are selected/de-selected and the unit's proper order of execution as
required by the instruction's operation to produce the desired manipulated data.
96.
4. MIPS Singlecycle Processor

Verilog Code
97.
98. module PC(clk , instruction , zero ,
branch , jump , pc );
99. input clk ;
100.

101.
102.
103.
104.
105.
106.

input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;

107. wire[31:0] pcInc;

108. wire[31:0] Branch1 ;
109. wire[15:0] address;
110. wire[31:0] branchAdd;
111. reg[31:0] mux1;
112. wire select1 ;
113. wire[31:0] jumpAdd ;
114. output [31:0] pc ;
115. reg [31:0] pc ;
116.
117.
118. assign select1 = branch & zero ;
119. assign pcInc = pc + 4 ;
120. assign address = instruction[15:0];
121. assign Branch1 =
{{16{address[15]}},address[15:0]} ; //
sign extension
122. assign branchAdd = pcInc + ( branch
<< 2 ) ;
123.
124. always@( branchAdd or pcInc or
select1 )

125. begin
126.
if ( select1 == 1 )
127.
mux1 = branchAdd ;
128.
else
129.
mux1 = pcInc ;
130. end
131.
132. assign jumpAdd = ( instruction[25:0]
<< 2 );
133.
134. always@ ( jump or jumpAdd or
mux1 )
135. begin
136.
if ( jump == 1 )
137.
npc = jumpAdd ;
138.
else
139.
npc = mux1;
140. end
141.
142. always @(posedge clk )
143.
pc <= npc;
144. endmodule

Functions:

MIPS Singlecycle Processor is a processor that carries out one instruction

in a single Clock cycle.

System Overview:

5. MIPS Multicycle Processor

Verilog Code:

module ALUControl(Opcode, ALUOp1, ALUOp0, Funct, Operation);

input ALUOp1, ALUOp0;
input [5:0] Funct, Opcode;
output [3:0] Operation;
reg [3:0] Operation;
always @ (ALUOp1, ALUOp0, Funct)
begin
if((ALUOp1==1'b0)&(ALUOp0==1'b0))
begin Operation <= 3'b010;
end
if(ALUOp0==1'b1) begin Operation <= 4'b0110;
end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0010;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0000;

end
if
((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0001;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b1)) begin Operation <= 4'b0111;

end

if

((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b1100;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0011;

end

if

(Opcode==6'b001000) begin //for add immediate Operation <= 4'b0010;

end

if

(Opcode==6'b001101) begin //for or immediate Operation <= 4'b0001;

end

if

(Opcode==6'b001100) begin // for andi Operation <= 4'b0000;

end

if

(Opcode==6'b001010) begin // for slti Operation <= 4'b0111;

end

end

endmodule

Functions:

break up instructions into separate steps

Each step takes a single clock cycle
Each functional unit can be used more than once in an instruction, as long as it is
used in different clock cycles
Reduces amount of hardware needed
Reduces average instruction time

6. 32 Bit ALU and test bench

Verilog Code

module logic_unit(d_out1,logic_u
nit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin

if(logic_unit== 1'b1)
begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 ==

1'b0)

begin

d_out1 = ( A | B);
end

else if(s0 == 1'b0 & s1 ==

1'b1) begind_out1 = ( A ^ B);
end

else

begin

d_out1 = ( A ^~ B);
end
end

else
begin

d_out1 = 4'b0000;

end

end
end

module`timescale 1ns / 1ps

module
arithmetic(d_out,A,B,cout,arithm
etic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;

input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always
@(s0,s1,c0,arithmetic_unit)
begin

if(arithmetic_unit)beginif(s1
== 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = A + 1'b1;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = D1;

cout = D0;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b1)
begin

d_out2 = D1 + 1'b1;

cout = D0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b0)
begin

d_out2 = L1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = L1 + 1'b1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = K1;

cout = K0;
end

else begin

d_out2 = K1 + 1'b1;

cout = K0;
end
end
else
begin

d_out2 = 4'b0000;
end
end

endmodule`timescale 1ns /
1ps
module
alu(CRY_OUT,DATA_OUT,CRY_
IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;

reg arithmetic_unit;
wire [3:0] DATA_OUT1;
wire [3:0] DATA_OUT2;
assign DATA_OUT = (MODE ?
DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(
DATA_OUT2),

.s0(SEL1),


.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),

.B(DATA_IN2),

.
logic_unit(logic_unit));
arithmetic
arithmetic_ins(.d_out(DATA_OU
T1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.
arithmetic_unit(arithmetic_unit));
always @(SEL1,SEL2,MODE)
begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;
end
else begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;
end
end
endmodule

7.

TEST BENCH FOR ALU:

8.
9. `timescale 1ns / 1ps
10.
module t_alu;
11.wire CRY_OUT;
12.
wire [3:0] DATA_OUT;
13.
reg CRY_IN;
14.
reg[3:0] DATA_IN1,DATA_IN2;
15.
reg SEL1,SEL2,MODE;
16.
alualu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
17.
initial
18.
begin
19.
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
20.
#500 SEL2 = 1'b0; SEL1 = 1'b0; CRY_IN = 1'b0;
21.
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
22.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
23.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
24.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
25.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
26.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
27.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
28.
#500 MODE = 1'b0;
29.
#500 SEL1 = 1'b0; SEL2 = 1'b1;
30.
#500 SEL1 = 1'b1; SEL2 = 1'b1;
31.
#500 SEL1 = 1'b1; SEL2 = 1'b0;
32.
#500 SEL1 = 1'b0; SEL2 = 1'b0;

33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.

End
Endmodule

63. Badillo, Gee-ann.

64. BSCpE V GF
65. Finite State Machine

Verilog Code for

FSM: (MOORE)
// 4-State Moore state machine
// A Moore machine's outputs are
dependent only on the current
state.
// The output is written only when
the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);

// Declare state register

reg
[2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2
= 2, S3 = 3, S4 = 4;
// Determine the next state
always @ (posedge clk or
posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)

state <= S1;

else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
66.
67.
68.

if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else

69.
70.
71.
72.
73.

Verilog Code for FSM: (MEALY)

state <= S2;

endcase // case (state)
end // always @ (posedge clk or
posedge reset)
// Output depends only on the
state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac

74.

FUNCTIONS
K. Moore: a Moore machine is a finite-state machine whose output values are
determined solely by its current state. This is in contrast to a Mealy machine, whose
output values are determined both by its current state and by the values of its inputs.
L. Mealy: a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. A Mealy machine is
a deterministic finite-state transducer: for each state and input, at most one transition
is possible.
75.
76.
77. Memory Blocks

Verilog Code:
78. module raminfr (clk, en, we, addr, di,
do);
79. input
clk;
80. input
we;
81. input
en;
82. input [4:0] addr;
83. input [3:0] di;
84. output [3:0] do;
85. reg [3:0] RAM [31:0];
86. reg [3:0] do;

87. always @(posedge clk)

88. begin
89. if (en) begin
90.
if (we)
91. RAM[addr] <= di;
92.
93.
do <= RAM[addr];
94. end
95. end
96.
endmodule

97.

Functions:
98.
The Memory block holds and delays its input by one major integration
time step. When placed in an iterator subsystem, it holds and delays its input by one
iteration. This block accepts continuous and discrete signals. The block accepts one
input and generates one output. Each signal can be scalar or vector. If the input is a
vector, the block holds and delays all elements of the vector by the same time step.
99.
You specify the block output for the first time step using the Initial
condition parameter. Careful selection of this parameter can minimize unwanted output
behavior. However, you cannot specify the sample time. This block's sample time
depends on the type of solver used, or you can specify to inherit it. The Inherit sample
time parameter determines whether sample time is inherited or based on the solver.

System Overview:
100.
101. Control Unit
102.

Functions:
103. Control Unit (CU) is generally a sizable collection of complex digital
circuitry interconnecting and controlling the many execution units contained within a
CPU. The CU is normally the first CPU unit to accept from an externally stored computer
program, a single instruction. The CU then decodes this individual instruction into
several sequential that controls and coordinates the CPU's inner works to properly
manipulate the data. The design of these sequential steps are based on the needs of
each instruction and can range in number of steps, the order of execution, and which
units are enabled. Thus by only using a program of set instructions in memory, the CU
will configure all the CPU's data flows as needed to manipulate the data correctly
between instructions. This results in a computer that could run a complete program and
requiring no human intervention to make hardware changes between instructions (as
had to be done when using only punch cards for computations before stored
programmed computers with CUs where invented). These detailed steps from the CU
dictate which of the CPU's interconnecting hardware control signals to enable/disable or
which CPU units are selected/de-selected and the unit's proper order of execution as
required by the instruction's operation to produce the desired manipulated data.
104.
105. MIPS Singlecycle Processor

Verilog Code
106.
107. module PC(clk , instruction , zero ,
branch , jump , pc );
108. input clk ;
109.

110.
111.
112.
113.
114.
115.

input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;

116. wire[31:0] pcInc;

117. wire[31:0] Branch1 ;
118. wire[15:0] address;
119. wire[31:0] branchAdd;
120. reg[31:0] mux1;
121. wire select1 ;
122. wire[31:0] jumpAdd ;
123. output [31:0] pc ;
124. reg [31:0] pc ;
125.
126.
127. assign select1 = branch & zero ;
128. assign pcInc = pc + 4 ;
129. assign address = instruction[15:0];
130. assign Branch1 =
{{16{address[15]}},address[15:0]} ; //
sign extension
131. assign branchAdd = pcInc + ( branch
<< 2 ) ;
132.
133. always@( branchAdd or pcInc or
select1 )

134. begin
135.
if ( select1 == 1 )
136.
mux1 = branchAdd ;
137.
else
138.
mux1 = pcInc ;
139. end
140.
141. assign jumpAdd = ( instruction[25:0]
<< 2 );
142.
143. always@ ( jump or jumpAdd or
mux1 )
144. begin
145.
if ( jump == 1 )
146.
npc = jumpAdd ;
147.
else
148.
npc = mux1;
149. end
150.
151. always @(posedge clk )
152.
pc <= npc;
153. endmodule

Functions:

MIPS Singlecycle Processor is a processor that carries out one instruction

in a single Clock cycle.

System Overview:

154. MIPS Multicycle Processor

Verilog Code:

module ALUControl(Opcode, ALUOp1, ALUOp0, Funct, Operation);

input ALUOp1, ALUOp0;
input [5:0] Funct, Opcode;
output [3:0] Operation;
reg [3:0] Operation;
always @ (ALUOp1, ALUOp0, Funct)
begin
if((ALUOp1==1'b0)&(ALUOp0==1'b0))
begin Operation <= 3'b010;
end
if(ALUOp0==1'b1) begin Operation <= 4'b0110;
end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0010;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0000;

end
if
((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0001;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b1)) begin Operation <= 4'b0111;

end

if

((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b1100;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0011;

end

if

(Opcode==6'b001000) begin //for add immediate Operation <= 4'b0010;

end

if

(Opcode==6'b001101) begin //for or immediate Operation <= 4'b0001;

end

if

(Opcode==6'b001100) begin // for andi Operation <= 4'b0000;

end

if

(Opcode==6'b001010) begin // for slti Operation <= 4'b0111;

end

end

endmodule

Functions:

break up instructions into separate steps

Each step takes a single clock cycle
Each functional unit can be used more than once in an instruction, as long as it is
used in different clock cycles
Reduces amount of hardware needed
Reduces average instruction time

155. 32 Bit ALU and test bench

Verilog Code

module logic_unit(d_out1,logic_u
nit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin

if(logic_unit== 1'b1)
begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 ==

1'b0)

begin

d_out1 = ( A | B);
end

else if(s0 == 1'b0 & s1 ==

1'b1) begind_out1 = ( A ^ B);
end

else

begin

d_out1 = ( A ^~ B);
end
end

else
begin

d_out1 = 4'b0000;

end

end
end

module`timescale 1ns / 1ps

module
arithmetic(d_out,A,B,cout,arithm
etic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;

input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always
@(s0,s1,c0,arithmetic_unit)
begin

if(arithmetic_unit)beginif(s1
== 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = A + 1'b1;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = D1;

cout = D0;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b1)
begin

d_out2 = D1 + 1'b1;

cout = D0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b0)
begin

d_out2 = L1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = L1 + 1'b1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = K1;

cout = K0;
end

else begin

d_out2 = K1 + 1'b1;

cout = K0;
end
end
else
begin

d_out2 = 4'b0000;
end
end

endmodule`timescale 1ns /
1ps
module
alu(CRY_OUT,DATA_OUT,CRY_
IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;

reg arithmetic_unit;
wire [3:0] DATA_OUT1;
wire [3:0] DATA_OUT2;
assign DATA_OUT = (MODE ?
DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(
DATA_OUT2),

.s0(SEL1),


.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),

.B(DATA_IN2),

.
logic_unit(logic_unit));
arithmetic
arithmetic_ins(.d_out(DATA_OU
T1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.
arithmetic_unit(arithmetic_unit));
always @(SEL1,SEL2,MODE)
begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;
end
else begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;
end
end
endmodule

156.

TEST BENCH FOR ALU:

157.
158.
`timescale 1ns / 1ps
159.
module t_alu;
160.
wire CRY_OUT;
161.
wire [3:0] DATA_OUT;
162.
reg CRY_IN;
163.
reg[3:0] DATA_IN1,DATA_IN2;
164.
reg SEL1,SEL2,MODE;
165.
alualu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
166.
initial
167.
begin
168.
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
169.
#500 SEL2 = 1'b0; SEL1 = 1'b0; CRY_IN = 1'b0;
170.
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
171.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
172.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
173.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
174.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
175.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
176.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
177.
#500 MODE = 1'b0;
178.
#500 SEL1 = 1'b0; SEL2 = 1'b1;
179.
#500 SEL1 = 1'b1; SEL2 = 1'b1;
180.
#500 SEL1 = 1'b1; SEL2 = 1'b0;
181.
#500 SEL1 = 1'b0; SEL2 = 1'b0;

182.
183.
184.
185.
186.
187.
188.
189.
190.
191.
192.
193.
194.
195.
196.
197.
198.
199.
200.
201.
202.
203.
204.
205.
206.
207.
208.
209.
210.
211.

End
Endmodule

212. Purio, Melvin Adrian C.

213. BSCpE V GF
1. Finite State Machine

Verilog Code for

FSM: (MOORE)
// 4-State Moore state machine
// A Moore machine's outputs are
dependent only on the current
state.
// The output is written only when
the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);

// Declare state register

reg
[2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2
= 2, S3 = 3, S4 = 4;
// Determine the next state
always @ (posedge clk or
posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)

state <= S1;

else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
214.
215.
216.

if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else

217.
218.
219.
220.
221.

Verilog Code for FSM: (MEALY)

state <= S2;

endcase // case (state)
end // always @ (posedge clk or
posedge reset)
// Output depends only on the
state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule // moore_mac

222.

FUNCTIONS
M. Moore: a Moore machine is a finite-state machine whose output values are
determined solely by its current state. This is in contrast to a Mealy machine, whose
output values are determined both by its current state and by the values of its inputs.
N. Mealy: a Mealy machine is a finite-state machine whose output values are
determined both by its current state and the current inputs. A Mealy machine is
a deterministic finite-state transducer: for each state and input, at most one transition
is possible.
223.
224.
2. Memory Blocks

Verilog Code:
225. module raminfr (clk, en, we, addr, di,
do);
226. input
clk;
227. input
we;
228. input
en;
229. input [4:0] addr;
230. input [3:0] di;
231. output [3:0] do;
232. reg [3:0] RAM [31:0];
233. reg [3:0] do;

234.
235.
236.
237.
238.
239.
240.
241.
242.
243.

always @(posedge clk)

begin
if (en) begin
if (we)
RAM[addr] <= di;
do <= RAM[addr];
end
end
endmodule

244.

Functions:
245. The Memory block holds and delays its input by one major integration
time step. When placed in an iterator subsystem, it holds and delays its input by one
iteration. This block accepts continuous and discrete signals. The block accepts one
input and generates one output. Each signal can be scalar or vector. If the input is a
vector, the block holds and delays all elements of the vector by the same time step.
246. You specify the block output for the first time step using the Initial
condition parameter. Careful selection of this parameter can minimize unwanted output
behavior. However, you cannot specify the sample time. This block's sample time
depends on the type of solver used, or you can specify to inherit it. The Inherit sample
time parameter determines whether sample time is inherited or based on the solver.

System Overview:
247.
3. Control Unit
248.

Functions:
249. Control Unit (CU) is generally a sizable collection of complex digital
circuitry interconnecting and controlling the many execution units contained within a
CPU. The CU is normally the first CPU unit to accept from an externally stored computer
program, a single instruction. The CU then decodes this individual instruction into
several sequential that controls and coordinates the CPU's inner works to properly
manipulate the data. The design of these sequential steps are based on the needs of
each instruction and can range in number of steps, the order of execution, and which
units are enabled. Thus by only using a program of set instructions in memory, the CU
will configure all the CPU's data flows as needed to manipulate the data correctly
between instructions. This results in a computer that could run a complete program and
requiring no human intervention to make hardware changes between instructions (as
had to be done when using only punch cards for computations before stored
programmed computers with CUs where invented). These detailed steps from the CU
dictate which of the CPU's interconnecting hardware control signals to enable/disable or
which CPU units are selected/de-selected and the unit's proper order of execution as
required by the instruction's operation to produce the desired manipulated data.
250.
4. MIPS Singlecycle Processor

Verilog Code
251.
252. module PC(clk , instruction , zero ,
branch , jump , pc );
253. input clk ;
254.

255.
256.
257.
258.
259.
260.

input[31:0] instruction ;
reg[31:0] npc;
input zero ;
input jump ;
input branch ;

261. wire[31:0] pcInc;

262. wire[31:0] Branch1 ;
263. wire[15:0] address;
264. wire[31:0] branchAdd;
265. reg[31:0] mux1;
266. wire select1 ;
267. wire[31:0] jumpAdd ;
268. output [31:0] pc ;
269. reg [31:0] pc ;
270.
271.
272. assign select1 = branch & zero ;
273. assign pcInc = pc + 4 ;
274. assign address = instruction[15:0];
275. assign Branch1 =
{{16{address[15]}},address[15:0]} ; //
sign extension
276. assign branchAdd = pcInc + ( branch
<< 2 ) ;
277.
278. always@( branchAdd or pcInc or
select1 )

279. begin
280.
if ( select1 == 1 )
281.
mux1 = branchAdd ;
282.
else
283.
mux1 = pcInc ;
284. end
285.
286. assign jumpAdd = ( instruction[25:0]
<< 2 );
287.
288. always@ ( jump or jumpAdd or
mux1 )
289. begin
290.
if ( jump == 1 )
291.
npc = jumpAdd ;
292.
else
293.
npc = mux1;
294. end
295.
296. always @(posedge clk )
297.
pc <= npc;
298. endmodule

Functions:

MIPS Singlecycle Processor is a processor that carries out one instruction

in a single Clock cycle.

System Overview:

5. MIPS Multicycle Processor

Verilog Code:

module ALUControl(Opcode, ALUOp1, ALUOp0, Funct, Operation);

input ALUOp1, ALUOp0;
input [5:0] Funct, Opcode;
output [3:0] Operation;
reg [3:0] Operation;
always @ (ALUOp1, ALUOp0, Funct)
begin
if((ALUOp1==1'b0)&(ALUOp0==1'b0))
begin Operation <= 3'b010;
end
if(ALUOp0==1'b1) begin Operation <= 4'b0110;
end

if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0010;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b0)) begin Operation <= 4'b0110;

end
if

((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0000;

end
if
((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b0)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0001;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b0)&( Funct[
3]==1'b1)) begin Operation <= 4'b0111;

end

if

((ALUOp1==1'b1)&(Funct[0]==1'b1)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b1100;

end

if
((ALUOp1==1'b1)&(Funct[0]==1'b0)&(Funct[1]==1'b1)&(Funct[2]==1'b1)&( Funct[
3]==1'b0)) begin Operation <= 4'b0011;

end

if

(Opcode==6'b001000) begin //for add immediate Operation <= 4'b0010;

end

if

(Opcode==6'b001101) begin //for or immediate Operation <= 4'b0001;

end

if

(Opcode==6'b001100) begin // for andi Operation <= 4'b0000;

end

if

(Opcode==6'b001010) begin // for slti Operation <= 4'b0111;

end

end

endmodule

Functions:

break up instructions into separate steps

Each step takes a single clock cycle
Each functional unit can be used more than once in an instruction, as long as it is
used in different clock cycles
Reduces amount of hardware needed
Reduces average instruction time

6. 32 Bit ALU and test bench

Verilog Code

module logic_unit(d_out1,logic_u
nit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin

if(logic_unit== 1'b1)
begin

if(s0 == 1'b0 & s1 == 1'b0)

begin

d_out1 = ( A & B);

end

else if(s0 == 1'b1 & s1 ==

1'b0)

begin

d_out1 = ( A | B);

end

else if(s0 == 1'b0 & s1 ==

1'b1) begind_out1 = ( A ^ B);
end

else

begin

d_out1 = ( A ^~ B);
end
end

else
begin

d_out1 = 4'b0000;

end

end
end

module`timescale 1ns / 1ps

module
arithmetic(d_out,A,B,cout,arithm
etic_unit,s0,s1,c0,M);
inout [3:0] d_out;
output cout;
input s0,s1,c0,M,arithmetic_unit;
input [3:0] A,B;wire [3:0] d_out;
reg cout;
wire s0,s1,c0,M,arithmetic_unit;
wire [3:0] A,B;wire [3:0]D1;
wire D0;
wire [3:0]L1;
wire L0;
wire [3:0]K1;
wire K0;
reg [3:0] d_out2;
reg [3:0] temp;
reg en;
assign {D0,D1} = A + B;
assign {L0,L1} = (A + (~B));
assign {K0,K1} = ((~A) + B);
assign d_out = d_out2;
always
@(s0,s1,c0,arithmetic_unit)
begin

if(arithmetic_unit)beginif(s1
== 1'b0 & s0 == 1'b0 & c0 == 1'b0)
begin

d_out2 = A;

end

else if(s1 == 1'b0 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = A + 1'b1;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = D1;

cout = D0;
end

else if(s1 == 1'b0 & s0 ==

1'b1 & c0 == 1'b1)
begin

d_out2 = D1 + 1'b1;

cout = D0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b0)
begin

d_out2 = L1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b0 & c0 == 1'b1)
begin

d_out2 = L1 + 1'b1;

cout = L0;
end

else if(s1 == 1'b1 & s0 ==

1'b1 & c0 == 1'b0)
begin

d_out2 = K1;

cout = K0;
end

else begin

d_out2 = K1 + 1'b1;

cout = K0;
end
end
else
begin

d_out2 = 4'b0000;
end
end

endmodule`timescale 1ns /
1ps
module
alu(CRY_OUT,DATA_OUT,CRY_
IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
output CRY_OUT;
output [3:0] DATA_OUT;
input CRY_IN;
input [3:0] DATA_IN1,DATA_IN2;
input SEL1,SEL2,MODE;
reg logic_unit;

reg arithmetic_unit;
wire [3:0] DATA_OUT1;

wire [3:0] DATA_OUT2;

assign DATA_OUT = (MODE ?
DATA_OUT1 : DATA_OUT2);
logic_unit logic_unit_ins(.d_out1(
DATA_OUT2),

.s0(SEL1),

.s1(SEL2),

.c0(CRY_IN),

.A(DATA_IN1),

.B(DATA_IN2),

.
logic_unit(logic_unit));
arithmetic
arithmetic_ins(.d_out(DATA_OU
T1),

.cout(CRY_OUT),

.s0(SEL1),

.s1(SEL2),

.A(DATA_IN1),

.B(DATA_IN2),

.c0(CRY_IN),

.M(MODE),

.
arithmetic_unit(arithmetic_unit));
always @(SEL1,SEL2,MODE)
begin

if(MODE == 1'b0)

begin

logic_unit = 1'b1;

arithmetic_unit = 1'b0;
end
else begin

logic_unit = 1'b0;

arithmetic_unit = 1'b1;
end
end
endmodule

7.

TEST BENCH FOR ALU:

8.
9. `timescale 1ns / 1ps
10.
module t_alu;
11.wire CRY_OUT;
12.
wire [3:0] DATA_OUT;
13.
reg CRY_IN;
14.
reg[3:0] DATA_IN1,DATA_IN2;
15.
reg SEL1,SEL2,MODE;
16.
alualu_ins(CRY_OUT,DATA_OUT,CRY_IN,DATA_IN1,DATA_IN2,SEL1,S
EL2,MODE);
17.
initial
18.
begin
19.
DATA_IN1 = 4'b1011;DATA_IN2 = 4'b0011;MODE = 1'b1;
20.
#500 SEL2 = 1'b0; SEL1 = 1'b0; CRY_IN = 1'b0;
21.
#500 SEL2 = 1'b0; SEL1 = 1'b0 ; CRY_IN = 1'b1;
22.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b0;
23.
#500 SEL2 = 1'b0; SEL1 = 1'b1 ; CRY_IN = 1'b1;
24.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b0;
25.
#500 SEL2 = 1'b1; SEL1 = 1'b0 ; CRY_IN = 1'b1;
26.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b0;
27.
#500 SEL2 = 1'b1; SEL1 = 1'b1 ; CRY_IN = 1'b1;
28.
#500 MODE = 1'b0;
29.
#500 SEL1 = 1'b0; SEL2 = 1'b1;
30.
#500 SEL1 = 1'b1; SEL2 = 1'b1;
31.
#500 SEL1 = 1'b1; SEL2 = 1'b0;
32.
#500 SEL1 = 1'b0; SEL2 = 1'b0;
33.
End
34.
Endmodule
35.
36.