82

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

Optimal Pulse-Width Modulation

for Three-Level Inverters
Thomas Brckner, Student Member, IEEE, and Donald Grahame Holmes, Senior Member, IEEE

AbstractThe three-level neutral-point-clamped voltage source

inverter is widely used in high power, medium voltage applications.
This paper studies continuous and discontinuous pulse-width modulation for this inverter. Detailed analysis of discontinuous modulation shows that the average switching frequency is not directly
proportional to the carrier or sampling frequency, since additional
switching transitions occur between different regions of discontinuity. At typical switching frequencies for high power applications
(up to 2 kHz) these additional transitions contribute significantly
to the inverters total losses, so that a proper comparison of the
harmonic performance can only be carried out under constant loss
conditions with varying carrier frequency. This comparison is performed for a typical industrial medium voltage inverter. The paper
then considers the major issues of neutral-point voltage balancing
and loss distribution within the inverter, for the identified optimal
modulation schemes.
Index TermsDiscontinuous modulation, pulse-width modulation (PWM), three-level inverter.

I. INTRODUCTION

HREE-LEVEL inverters are of particular interest for high

power applications. One of the most common topologies is the three-level neutral-point-clamped voltage source
inverter (NPC VSI) shown in Fig. 1, which is widely used in
medium voltage drives for rolling mills, marine, and traction
applications. For this topology and in these situations, the
modulation strategies that are used have to take into account the
requirements of the typical switching frequencies of insulated
gate bipolar transistor (IGBT) and integrated gate-commutated
thyristor (IGCT) inverters (500 Hz up to 2 kHz), and the need
for neutral-point potential control, as a basic requirement for
any industrial inverter of this power level.
Inverter modulation schemes have been the subject of research for more than two decades, and during this time there
have been considerable advances in understanding as to how
the modulation process works. A comprehensive review of continuous and discontinuous modulation for two-level inverters
was presented in 1990 by Kolar [1] and in 1991 by van der
Broeck [2] and later extended by other authors [3]. Steinke proposed a pulse-width modulation (PWM) scheme for a threelevel inverter including neutral-point potential control in 1992

Fig. 1.

Three-level NPC VSI.

[4], and three-level discontinuous schemes have been evaluated

by a number of authors such as Kaku [5].
Most often, PWM schemes are compared by considering the
harmonic distortion produced by different schemes when operating with the same effective switching frequency. Commonly,
the assumption is made that the average switching frequency of
discontinuous PWM is 2/3 that of continuous PWM. Hence, harmonic distortion factors for discontinuous modulation schemes
are usually converted by a factor of 2/3 or
, depending on
the quality criterion used. But a detailed analysis of these modulation processes reveals that the average switching frequency for
discontinuous modulation is not exactly proportional to the carrier frequency, especially for the rather small switching frequencies of up to 2 kHz that are of interest for three-level inverters.
In fact, the only basis for a proper harmonic comparison is with
a matched constant loss condition.
This paper presents an evaluation of continuous and discontinuous modulation strategies for three-level inverters operating
under precisely matched loss conditions. The schemes are then
compared with respect to lowest harmonic distortion, highest
achievable output power, and ability to control the neutral-point
potential.
II. THREE-LEVEL INVERTER MODULATION SCHEMES

Manuscript received July 16, 2003; revised July 13, 2004. This paper was
presented at the IEEE Power Electronics Specialists Conference (PESC03),
Acapulco, 2003. Recommended by Associate Editor J. W. Kolar.
T. Brckner is with the Institute of Energy and Automation, Technical University of Berlin, Berlin 10587, Germany (e-mail: thomas.brueckner@gmx.net).
D. G. Holmes is with the Department of Electrical and Computer Systems Engineering, Monash University, Clayton 3800, Australia (e-mail:
grahame.holmes@eng.monash.edu.au).
Digital Object Identifier 10.1109/TPEL.2004.839831

A. Optimal Modulation Principles

The space vector diagram for a three-level inverter is shown
in Fig. 2, with 19 vectors and 27 switch states. It is now well
accepted that all optimal modulation strategies for this inverter
use the three-nearest space vectors to create a switched output
representation of the reference waveform. These space vectors

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BRCKNER AND HOLMES: OPTIMAL PULSE WIDTH MODULATION

83

Fig. 3. Carrier-based phase disposition modulation with asymmetric regular

sampled sine reference.
Fig. 2.

Space vector diagram for a three-level inverter.

form the vertices of the internal triangle of Fig. 2 within which

the reference phasor resides at the time of sampling.
Over the years, the merits of carrier-based modulation versus
space vector modulation (SVM) have been argued at length.
However, it is now also generally accepted that carrier-based
modulation with two co-phasal carrier signals as depicted
in Fig. 3called phase disposition modulationis equivalent to the three-nearest space vector modulation, and that
asymmetric regular sampling is superior to symmetric regular
sampling because of the reduced number of harmonics that are
created by this sampling process [6].

means treating the inner hexagon as a two-level inverter utilizing

either the upper (0 to ) or the lower set ( to 0) of redundant
switch states. For example the switching sequence for subsector
E in Fig. 2 is
and
return, or
and return. In contrast the sequence of three-level SVM is
and back. Since the sequence of
two-level SVM starts from the origin, the six extra transitions
between the equivalent null vectors are avoided. However, to
control the neutral-point voltage and distribute losses between
inverter switches, the carrier bands must be alternated at regular
intervals, and this introduces some additional switching transitions.

B. Continuous Modulation Schemes

Given the equivalence of carrier-based and space vector modulation schemes, it is clear that the known continuous modulation strategies only differ in the placement of the active vectors
within the sampling period. Centering the two middle vectors
in each sampling period is well known to be the superior approach [6], and this has been industry practice for space vector
modulation for many years. Therefore this approach will be referred to as SVM throughout the paper. The equivalent reference waveform for carrier-based modulation of a three-level inverter [see Fig. 4(a)] was already reported in 1990 by Steinke
[7], and a good derivation from two-level SVM concepts with
a modified common mode offset is given in [8]. In contrast to
the SVM of a two-level inverter, the switching sequences do not
start and end in the origin of the space vector diagram, but at
the vectors situated on the inner hexagon, e.g.,
.
These vectors are therefore called equivalent null vectors. For
example, the switching sequence for subsector A in Fig. 2 is
and return. It should
be noted that the average switching frequency is slightly higher
than the carrier frequency since six additional transitions are required over one fundamental period. These transitions occur as
the start and end point of the vector sequences move between
the equivalent null vectors, e.g., from the switch state
to
. In the reference-carrier-plot of Fig. 3, two extra transitions per phase ( six transitions for three phases) can be seen,
where the reference moves across the carrier bands.
An interesting alternative for small modulation depths
is to use a two-level SVM reference shifted into one single carrier band [see Fig. 4(b)]. This

C. Discontinuous Modulation Schemes

From two-level modulation theory, three basic discontinuous
modulation schemes are known: 120 , 60 , and 30 discontinuous pulse width modulation (DPWM). For all of these methods
the total duration of discontinuity per phase is 120 electrical degrees, but for 60 and 30 DPWM the clamping period is split up
into
and
intervals, respectively. Also, while 120
DPWM bounds the references to either the positive or negative
rail exclusively, 60 and 30 DPWM use both dc rails. Comprehensive analyses of these variations can be found in numerous
references [1][3], [6].
The same strategies as for two-level modulation have also
been reported for three-level inverters. But since the inverter offers the additional clamping point of the neutral tap, the variety
of possible strategies increases. Two different ways to apply
the knowledge from two-level discontinuous modulation to the
three-level inverter can be identified in literature. As an example, these ideas are explained for the 60 DPWM strategy.
The simplest and conventional approach is to use the unchanged reference waveform taken from the two-level inverter
[5], with sinusoidal target, offset and final reference waveforms
as depicted in Fig. 4(c). Given a set of sinusoidal references

(1)

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

Fig. 4. Reference waveforms for carrier-based modulation: (a) three-level SVM (M = 0:9), (b) two-level SVM in one carrier band (M = 0:5), (c) conventional
60 DPWM (M = 0:9), and (d) alternative three-level 60 DPWM (M = 0:9).

the common mode offset is calculated by

sign

where
(2)

if
if

where
if
if
if

if

and the reference voltage with the maximum absolute value is

clamped to the nearest, either positive or negative dc rail. The
approach creates 60 clamping periods in the vicinity of the
peak current, which can be shifted for
to adjust for
power factors
. For example phase A is clamped to the
positive dc rail for
as indicated in Fig. 2. It is interesting
to note with this scheme that the vector
is only
used as the equivalent null vector for modulation of subsectors
A, B, D, and E in Fig. 2, while sectors C and F are modulated
with effective null vectors taken from the centers of the adjacent
hexagons.
The second approach is to apply the offset calculation
to transformed references, similar to the approach used for
continuous three-level SVM [9], [10]. The sinusoidal references1 are shifted into a virtual common carrier band spanning
using

(3)
where
delivers the remainder of the division
.
This transformation can be understood as moving the null vector
from the origin to the appropriate vectors situated on the inner
hexagon. The offset calculation being adjusted to the narrower
carrier region is then applied to the transformed references
sign

(4)

1In case the modulation depth is in the range of 1 < M < 1:155, an offset
centering the middle vectors has to be applied to the sinusoidal references prior
to transformation.

Again, the reference with the absolute maximum value is

clamped to the nearest boundary of the virtual carrier band. The
offset is finally added to the original references. In contrast to
conventional 60 DPWM this results in a waveform that clamps
to all three voltage levels, positive rail, negative rail, and neutral tap, as shown in Fig. 4(d). The number, placement and duration of the clamping periods are dependent on modulation depth.
The grey shaded sectors in Fig. 2 are clamped to the active rails,
while the white sectors are clamped to zero. Vector sequences
for all subsectors A to F start at
, which is exactly the same behavior as for continuous modulation. It also
becomes obvious that for
only zero-level clamping
occurs, while for maximum modulation depth the scheme returns to the previous version [see Fig. 4(c)].
Both of these approaches are also applicable to 120 DPWM.
However, for 30 DPWM, only the unchanged reference waveform from the two-level inverter situation can be used, since the
application of the offset calculation to transformed references
yields various absurd variations.
III. ANALYZING LOSSES FOR DIFFERENT MODULATION
STRATEGIES
A. Theoretical Considerations
For high power inverters, harmonic distortion and semiconductor losses are equally important criteria for the evaluation
of modulation strategies. While harmonic distortion can be
determined by factors as HDF [3] or weighted THD, precise adjustment for losses requires a thorough analysis of space vector
sequences or reference waveforms throughout the fundamental
cycle. In fact, to properly investigate a discontinuous modulation strategys potential for reduction of switching losses, three

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85

Fig. 5. Reference waveforms for carrier-based modulation at small modulation depth (M = 0:5): (c) conventional 60 DPWM, (d) alternative three-level 60
DPWM, (e) 60 DPWM in one carrier band, and (f) zero-clamped 60 DPWM.
TABLE I
SWITCHING SEQUENCES OF 60 DPWM SCHEMES AT SMALL MODULATIONS DEPTHS

It shall be noted that the start and end points of the vector sequences cannot be clearly defined in this situation.
Depending upon definition either (+ + +=000= 0 00) or the vectors on the inner hexagon (+00=0 0 0) etc.
can be considered the (equivalent) null vectors.

properties of the reference waveform must be considered: 1) the

position of the clamping periods with respect to the peak phase
current, 2) the duration of the clamping periods, and 3) the
number of zero crossings, i.e., carrier band changes. In general,
clamping in the vicinity of the peak phase current is most advantageous. However, although every phase is always clamped
for 120 over a complete fundamental cycle, the duration of the
individual clamping intervals (e.g.,
or
) affects
the number of switching transitions. Essentially, the shorter
the clamping periods the more extra transitions are required.
And finally, as for continuous modulation, every carrier band
change invokes one additional switching transition. At the
low switching frequencies of high power inverters these extra
transitions make up a significant part of the total losses and
cannot be disregarded when comparing the benefits of the
various discontinuous modulation schemes.
For dynamic drive applications such as rolling mills, small
modulation depths are as crucial as large modulation depths,
with one of the most critical operating points being zero speed
(
,
). Hence, it is necessary to determine the performance of the various strategies throughout the entire modulation range, as their characteristics do change with modula-

tion depth. For example, the alternative three-level 60 DPWM

has four short clamping intervals at a large modulation depth
[see Fig. 4(d)], while the conventional 60 DPWM has two 60
clamping intervals [see Fig. 4(c)]. At small , both 60 discontinuous schemes clamp for
[see Fig. 5(c) and (d)], but
only the conventional strategy places the clamping periods in
). On the
the vicinity of the peak phase current (for
other hand, the conventional method requires six carrier band
changes per phase per fundamental cycle (for
), as seen
in Fig. 5(c).
One measure to avoid some of these additional switching
transitions is obvious, since similar to two-level SVM the reference can be shifted into one carrier band for low modulation
depths
[see Fig. 5(e)]. A second alternative is
to clamp the phases to the neutral point instead of connecting
them to the positive and negative dc rails [see Fig. 5(f)]. Close
inspection of the reference waveforms in Fig. 5(c), (e), and (f)
shows that they only differ in square-wave offset functions at
triple the fundamental frequency. The switching sequences of
the three versions are given in Table I. The two new variations neither alter the vector sequences of the conventional 60
DPWM, nor change the on-time of the vectors, but simply utilize

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

other redundant switch states.2 The switched line-to-line output

voltage waveforms remain unchanged. Hence, there is no effect
on line-to-line harmonics but there is a benefit for total semiconductor losses, loss distribution and neutral-point potential control. Strategies with references shifted into one carrier band [see
Figs. 4(b) and 5(e)] are especially useful at zero speed.
This more detailed analysis suggests that simply scaling the
carrier frequencies is not an appropriate basis for harmonic
comparison of different discontinuous modulation strategies,
and a more precise base condition needs to be established.
In general, the limiting factor for high power inverters is the
semiconductor losses. The design of the cooling system, the
heatsinks, and the thermal data of the semiconductors determine the maximum amount of losses to be dissipated and
hence the maximum switching frequency. (In most cases the
raw device switching speeds and current ratings would allow
a higher switching frequency and output power than can be
practically achieved.) Therefore a better basis for comparing
the harmonic performance of different modulation strategies
is to evaluate them operating with exact constant total losses.
With this approach each scheme at every modulation depth is
operated at its maximum allowable switching frequency, and
their harmonic performance under these conditions is then
compared.
B. Simulative Investigations
The proposed comparison is carried out with the aid of extensive time-domain MATLAB simulations. The mathematical
description of a three-phase three-level inverter is implemented
in an M-file and solved numerically. Semiconductor losses are
, half dc-link
calculated from instantaneous phase currents
, and junction temperatures , based on approxvoltages
imations of datasheet values [11]

Fig. 6. Harmonic performance of continuous and discontinuous PWM

schemes for constant pulse ratio f =f = 21.

With the model described above simulations are performed

for the different modulation strategies and over the entire range
. In a first step all simulations
of operation
are carried out for a constant pulse ratio of
. With
the knowledge of the losses obtained from the first simulations
in a second step the pulse ratios are adapted such that the desired constant loss condition is achieved. Continuous three-level
SVM, switching at a constant frequency of
Hz, is
taken as the loss benchmark, and the pulse ratios of the other
schemes are modified to match the losses of SVM at each point
over the entire modulation range. Beside losses and junction
temperatures the harmonic spectra of the switched line-to-line
voltage are calculated for every modulation scheme.
IV. HARMONIC PERFORMANCE UNDER CONSTANT
LOSS CONDITIONS

(5)
(6)
where
and
denote the semiconductor on-state behavior
and
,
,
are fitting constants. Conduction
losses of IGBTs
and diodes
, turn-on losses
and turn-off losses
of IGBTs, and recovery losses
of diodes are taken into account. The calculated losses are accumulated over a number of fundamental periods and are also
fed into a thermal model of the converter. The model consists
of a network of paralleled thermal resistances
and capacitances
, where each series junction-to-ambient is built of
four internal
-elements for junction-to-case (IGBT or
diode separately) and two common elements per module for
case-to-ambient. A detailed description of such a thermal model
is given in [12]. It enables a good estimate of the junction temand
peratures of the inverter switches and diodes. Values for
for junction-to-heatsink are taken from the datasheet [11].
Furthermore, a water-cooled heatsink of the type Eupec KW51
with
K/kW heatsink-to-ambient at a water flow rate of
l/min is assumed.

2From Fig. 2 it can be observed that for M

0:5775, i.e., within the inner
hexagon, two complete sets of redundant switch states always adjoin each triangle.

In this paper, results for a typical industrial medium voltage

inverter with
and
A, utilizing Eupec
FZ 1200 R33 KF2 IGBTs, are presented. As an easy measure
to compare the waveform quality of the different modulation
schemes, the weighted total harmonic distortion, normalized to
the line-to-line voltage at
, is used. It is defined by

(7)
where is the modulation depth and
denotes the nth harmonic of the line-to-line voltage. This criterion is qualitatively
equivalent to HDDF introduced by Fukuda [13]. HDF curves
found in other references [1][3] essentially differ only because
they are squared.
Fig. 6 shows the
for a constant pulse ratio of
. The majority of the curves in Fig. 6 are familiar and
are included in this paper for reference. Note that the switching
frequency of the discontinuous schemes has not been adjusted
by 3/2, and hence, their
is substantially greater than
that of continuous SVM as would be expected. However, the
performance of all discontinuous strategies lies within the same
range, consistent with previous results.

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87

Fig. 8. Average junction temperatures in a three-level NPC VSI at large

= 600 A, f = 1050 Hz, pf = 1,
modulation depth (V = 3400 V, I
M = 1:15, ambient temperature #a = 37 C, Eupec FZ 1200 R33 KF2).
Fig. 7. Harmonic performance of continuous and discontinuous PWM
schemes for constant losses (NPC VSI with Eupec FZ 1200 R33 KF2,
V = 3400 V, I
= 600 A, pf = 1, f = 50 Hz, varying pulse ratio,
f =f = 21 for three-level SVM).

Fig. 7 shows the effect of adjusting the pulse ratio for each
scheme to achieve constant losses. It should be noted that this
quantitative result is specific to the investigated inverter since
the losses (and thus the nonlinear semiconductor characteristics)
determine as to how much the pulse ratio of each scheme can be
adjusted. However, the basic information of Fig. 7 is valid for
any inverter for medium voltage applications. As expected, the
harmonic distortion of the discontinuous schemes is now similar
to continuous SVM, but there is also considerably more spread
between the various discontinuous schemes themselves. For the
example of 60 DPWM, the allowable increase in switching frequency for the alternative three-level scheme is lower than that
achievable using conventional 60 DPWM, resulting in a higher
harmonic distortion. For
both schemes are equivalent, operating at the same carrier frequency. For smaller modulation depths (down to
) the alternative three-level
method splits the 60 clamping periods apart, and places an increasing portion around the zero crossings instead of around the
peak phase current. Extra transitions due to the shorter clamping
periods partially compensate for the additional transitions because of the more frequent carrier-band changes required with
the conventional method. But from Fig. 7, it can be observed that
, clamping in the vicinity of the peak phase
for about
current clearly outweighs the alternative three-level schemes
advantage of fewer extra switching transitions. With the alternative three-level scheme, there is also no possibility of shifting
the clamping region for
, which would further affect
the losses for
.
As predicted in Section III the zero-clamped alternative for
is advantageous over the conventionally clamped 60
small
DPWM scheme. This performance gain (compare curves 2 and
4 in Fig. 7) is purely due to the saving of four extra transitions
per phase per fundamental cycle. This example highlights the
significance of the extra switching transitions, though the comparison in the previous paragraph may have led to the opposite
conclusion.
The 60 DPWM shifted into one carrier band yields equivalent results as the zero clamped version, if two carrier-band
changes per fundamental cycle are assumed for neutral-point

potential control. For the same reason the pulse ratio of twolevel SVM has not been adjusted in Fig. 7 compared to Fig. 6.
To summarize the results, 120 and 60 DPWM schemes
have been found to be superior to 30 DPWM schemes, and
unchanged reference waveforms taken from two-level inverters
yield better performances than the alternative three-level approach. However, what is more surprising is that over nearly the
entire modulation range, none of the discontinuous strategies
are superior to the two continuous SVM schemes of two-level
at low modulation depths and three-level at higher modulation
depths. Indeed, only conventional 120 and 60 DPWM strategies achieve a comparable harmonic performance. Finally, at
very large modulation depths
most discontinuous
schemes are advantageous over SVM, again with the conventional 60 DPWM strategy showing the best performance.
V. LOSS DISTRIBUTION
Apart from total losses, the distribution of semiconductor
losses amongst the devices is also a crucial issue. In fact, the
losses in the most stressed device essentially limit the switching
frequency and the output power.
The four most critical operating points of the three-level NPC
VSI are maximum and minimum modulation depth, at power
factors of
and
, as identified in [14]. Applying
conventional continuous modulation methods, it has been found
that for each of these cases one group of devices reaches its maximum junction temperature while the other devices stay much
cooler. Different types of continuous and discontinuous modulation affect this junction temperature distribution.
At the maximum modulation depth of
, all symmetrical schemes distribute losses in an equivalent manner as SVM
or ordinary sine-triangle modulation, shown in Fig. 8. Therefore
the maximum output power achievable at this operating point is
equivalent for all symmetrical PWM methods.3 At small modulation depths three basic types of junction temperature distributions can be identified. Their characteristics are summarized in
Table II.4
3The loss distribution has been compared with the precisely matched loss conditions used to evaluate the harmonic performance of the different modulation
strategies.
4For 120 discontinuous methods an equal share of positive and negative rail
clamping is assumed to achieve symmetry.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005

TABLE II
JUNCTION TEMPERATURE DISTRIBUTION OF MODULATION SCHEMES

Fig. 9. Average junction temperatures in a three-level NPC VSI at small

modulation depth (V = 3400 V, I
= 600 A, f = 1050 Hz, pf = 1,
M = 0:05, ambient temperature #a = 37 C, Eupec FZ 1200 R33 KF2).

The reasons for the different behaviors of the different strategies can be found in their reference waveforms. Unlike the members of Group 1 the reference functions of conventional discontinuous modulation methods (Group 2) assume negative values
for significant nonclamped periods to realize a positive sinusoidal target. This results in drastic relief of the most stressed
NPC diodes
at
,
and of the inner switches
at
,
. Also, the overall junction temperature
distribution is much better. However, it can be further improved
by the modulation methods that shift references into one carrier
band (Group 3). Fig. 9 shows the junction temperature distribution at a small modulation depth for the harmonically superior
SVM strategies. The two-level SVM is assumed to alternate between both carrier bands at half the fundamental frequency. The
reference stays in the upper carrier band, realizing positive and
negative sinusoidal target voltages for equal amounts of time,
respectively, in the lower carrier band. This strategy belonging
to Group 3 distributes the semiconductor losses far more evenly
than for simple three-level SVM (Group 1), thus opening the
possibility of an output power increase at low modulation depth.
Two-level SVM is also well suited for the most critical operthe instantaneous values
ating point of zero speed. With
of the target voltage remain nearly unchanged over long periods.
However, the references can alternate between the carrier bands
frequently, thus distributing the losses to all inverter switches.
VI. NEUTRAL-POINT POTENTIAL CONTROL
The ability to control the neutral-point potential is an essential requirement in any industrial inverter today. For symmet-

rical modulation schemes and under ideal conditions the dc-capacitor voltages naturally balance over one fundamental cycle.
Within the fundamental cycle there is a low-frequency ripple,
which is dependent on the modulation scheme and operating
point [15]. However, dynamic changes, nonideal switching of
the inverter, and unbalanced load can cause a steady drift of the
neutral-point potential. Therefore a neutral-point potential control strategy is necessary. The main task is to maintain long-term
stability without creating additional switching transitions. It is
of minor importance to suppress any low-frequency ripple.
Except for the schemes that shift references into one carrier
band, the PWM methods do not inherently allow to control the
neutral-point potential. Three-level SVM defines a fixed 50/50
share of on-time for the redundant switch states of the equivalent
and
] to optimize the harmonic
null vectors [e.g.,
performance. These switch states drive neutral-point currents in
the opposite direction and their on-time ratio must be manipulated to affect the neutral-point potential. An easy realization to
do so is to add a feedback-controlled common dc offset to the
reference voltages [16].
Discontinuous schemes for larger modulation depths utilize
only one of the two redundant switch states of the equivalent
null vectors within one sampling period. Nevertheless, with conventional 60 DPWM the previous approach can be used, with
the dc offset added to the target sine wave (1) before calculation
of the final reference waveform (2). Variations of the clamping
periods, using longer positive clamping at the expense of negative clamping or vice versa, and neutral-point control, have been
with
achieved [17]. Modulation schemes for small values of
references shifted into one carrier band, e.g., two-level SVM,
allow a straight-forward control for the neutral-point potential
by alternating the references between both carrier bands as required [4]. Here the task of potential control is prior to the task
of loss distribution.
In summary, neutral-point control can be achieved with the
favorable modulation methods. However, in the cases of threelevel SVM and 60 DPWM the harmonic performance is expected to deteriorate. For the sake of completeness it is also
noted that for 60 DPWM and two-level SVM the low frequency
ripple of the neutral-point potential is increased compared to
three-level SVM. This can influence the design of the dc-link capacitors typically being film capacitors in medium voltage converters. In contrast the rms values of the capacitor currents are
not affected by the considered modulation schemes [18].
VII. CONCLUSION
Continuous and discontinuous modulation schemes for
the three-level NPC voltage source inverter have been analyzed. Since high-power applications are of most interest
for three-level inverters special attention has been given to
considering second order effects at low pulse ratios. It has been
found that additional switching transitions in discontinuous
modulation schemes affect the increase in switching frequency
that can be achieved compared to continuous modulation.
Therefore a precise comparison of harmonic performance must
be on the basis of exactly equal switching losses. Comparisons
under this condition have shown that three-level continuous
SVM (having centered middle vectors) is superior over nearly
, while two-level
the entire modulation range
SVM using the inner hexagon and conventional 60 DPWM

BRCKNER AND HOLMES: OPTIMAL PULSE WIDTH MODULATION

yield the best performance at low and very large modulation

depths, respectively.
Furthermore, two-level SVM using the inner hexagon
(reference waveforms shifted into one carrier band) enables
best loss distribution at low modulation depths and zero speed.
Long-term stability of the neutral-point potential can be guaranteed with the three superior PWM schemes. Hence, for optimal
performance the modulation control of a modern high-power
inverter must be adaptive, selecting the most favorable PWM
scheme for its current operating condition from these three
strategies.

89

[15] N. Celanovic and D. Boroyevich, A comprehensive study of neutralpoint voltage balancing problem in three-level neutral-point-clamped
voltage source PWM inverters, IEEE Trans. Power Electron., vol. 15,
no. 2, pp. 242249, Mar. 2000.
[16] C. Newton and M. Sumner, Neutral point control for multi-level inverters: theory, design and operational limitations, in Proc. IEEE Industrial Applications Soc. Annu. Meeting, New Orleans, LA, 1997, pp.
13361343.
[17] L. Helle, S. Munk-Nielsen, and P. Enjeti, Generalized discontinuous
dc-link balancing modulation strategy for three-level inverters, in Proc.
Power Conversion Conf., Osaka, Japan, 2002, pp. 359366.
[18] J. W. Kolar and U. Drofenik, A new switching loss reduced discontinuous PWM scheme for a unidirectional three-phase/switch/level boosttype (VIENNA) rectifier, in Proc. IEEE Int. Telecommunications Engergy Conf., Copenhagen, Denmark, 1999, pp. 490499.

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Thomas Brckner (S99) was born in Heidenau,

Germany, in 1973. He received the Dipl.-Ing. degree
in electrical engineering from Dresden University of
Technology, Dresden, Germany, in 1999.
From 1996 to 1997, he was a Guest Student at the
Virginia Power Electronics Center, Virginia Polytechnic Institute and State University, Blacksburg.
Since 1998, he has worked on several projects for
ABB in Germany and Switzerland. In 2002, he was a
Visiting Researcher at Monash University, Clayton,
Australia. Currently, he is with the Department
of Electrical Engineering and Computer Science, Technical University of
Berlin, Berlin, Germany. His research interests include topologies, devices, and
controls for high-power conversion.

Donald Grahame Holmes (M88SM03) received the B.S. and M.S. degrees in power systems
engineering from the University of Melbourne, Melbourne, Australia, in 1974 and 1979, respectively,
and the Ph.D. degree in PWM theory for power electronic converters from Monash University, Clayton,
Australia, in 1998.
In 1984, he joined Monash University to work in
the area of power electronics, and he now heads the
Power Electronics Research Group, ECSE Department. The present interests of this group include fundamental modulation theory and its application to the operation of energy conversion systems, current regulators for drive systems and PWM rectifiers, active
filter systems for quality of supply improvement, resonant converters, currentsource inverters for drive systems, and multilevel converters. He has a strong
commitment and interest in the control and operation of electrical power converters. He has made a significant contribution to the understanding of PWM
theory through his publications and has developed close ties with the international research community in the area. He has published over 100 papers at
international conferences and in professional journals, and has recently co-authored a major reference textbook in the area of PWM. He also regularly reviews
papers for all major IEEE TRANSACTIONS in his area.
Dr. Holmes is an active member of the IPC and IDC Committees of the IEEE
Industrial Applications Society, and is a member of the Adcom of the IEEE
Power Electronics Society.