Name: Chaitanyakumar Rajeshkumar Shah

Net-Id: crs562
University Id: N11802972
Course Name: Advanced Computer Hardware Design
Lab 1 Left Rotate and Right Rotate
Left Rotate
Test 1
a = 10110011110000111111110000000010
b = 00000000, Which is 0bit left rotate.

Test 2
a = 10110011110000111111110000000010
b = 00000001, Which is 1bit left rotate.

Test 3
a = 10110011110000111111110000000010
b = 10000010, Which is 2bit left rotate.

Test 4
a = 10110011110000111111110000000010
b = 01000011, Which is 3bit left rotate.

Test 5
a = 10110011110000111111110000000010
b = 00100100, Which is 4bit left rotate.

Test 6
a = 11100010101011110000101010101010
b = 00000101, Which is 5bit left rotate.

Test 7
a = 11100010101011110000101010101010
b = 00000110, Which is 6bit left rotate.

Test 8
a = 11100010101011110000101010101010
b = 10000111, Which is 7bit left rotate.

Test 9
a = 11100010101011110000101010101010
b = 01001000, Which is 8bit left rotate.

Test 10
a = 11100010101011110000101010101010
b = 00101001, Which is 9bit left rotate.

Test 11
a = 11111111111111110000000000000000
b = 00001010, Which is 10bit left rotate.

Test 12
a = 11111111111111110000000000000000
b = 00001011, Which is 11bit left rotate.

Test 13
a = 11111111111111110000000000000000
b = 10001100, Which is 12bit left rotate.

Test 14
a = 11111111111111110000000000000000
b = 01001101, Which is 13bit left rotate.

Test 15
a = 11111111111111110000000000000000
b = 00101110, Which is 14bit left rotate.

Test 16
a = 11110000111100001111000011110000
b = 00001111, Which is 15bit left rotate.

Test 17
a = 11110000111100001111000011110000
b = 00010000, Which is 16bit left rotate.

Test 18
a = 11110000111100001111000011110000
b = 10010001, Which is 17bit left rotate.

Test 19
a = 11110000111100001111000011110000
b = 01010010, Which is 18bit left rotate.

Test 20
a = 11110000111100001111000011110000
b = 00110011, Which is 19bit left rotate.

Test 21
a = 00111100111100111100111100111100
b = 00010100, Which is 20bit left rotate.

Test 22
a = 00111100111100111100111100111100
b = 00010101, Which is 21bit left rotate.

Test 23
a = 00111100111100111100111100111100
b = 10010110, Which is 22bit left rotate.

Test 24
a = 00111100111100111100111100111100
b = 01010111, Which is 23bit left rotate.

Test 25
a = 00111100111100111100111100111100
b = 00111000, Which is 24bit left rotate.

Test 26
a = 00110011001100110011001100110011
b = 00011001, Which is 25bit left rotate.

Test 27
a = 00110011001100110011001100110011
b = 00011010, Which is 26bit left rotate.

Test 28
a = 00110011001100110011001100110011
b = 10011011, Which is 27bit left rotate.

Test 29
a = 00110011001100110011001100110011
b = 01011100, Which is 28bit left rotate.

Test 30
a = 00110011001100110011001100110011
b = 00111101, Which is 29bit left rotate.

Test 31
a = 11111111000000001111000011001010
b = 00011110, Which is 30bit left rotate.

Test 32
a = 11111111000000001111000011001010
b = 00011111, Which is 31bit left rotate.

Right Rotate
Test 1
a = 10110011110000111111110000000010
b = 00000000, Which is 0bit right rotate.

Test 2
a = 10110011110000111111110000000010
b = 00000001, Which is 1bit right rotate.

Test 3
a = 10110011110000111111110000000010
b = 10000010, Which is 2bit right rotate.

Test 4
a = 10110011110000111111110000000010
b = 01000011, Which is 3bit right rotate.

Test 5
a = 10110011110000111111110000000010
b = 00100100, Which is 4bit right rotate.

Test 6
a = 11100010101011110000101010101010
b = 00000101, Which is 5bit right rotate.

Test 7
a = 11100010101011110000101010101010
b = 00000110, Which is 6bit right rotate.

Test 8
a = 11100010101011110000101010101010
b = 10000111, Which is 7bit right rotate.

Test 9
a = 11100010101011110000101010101010
b = 01001000, Which is 8bit right rotate.

Test 10
a = 11100010101011110000101010101010
b = 00101001, Which is 9bit right rotate.

Test 11
a = 11111111111111110000000000000000
b = 00001010, Which is 10bit right rotate.

Test 12
a = 11111111111111110000000000000000
b = 00001011, Which is 11bit right rotate.

Test 13
a = 11111111111111110000000000000000
b = 10001100, Which is 12bit right rotate.

Test 14
a = 11111111111111110000000000000000
b = 01001101, Which is 13bit right rotate.

Test 15
a = 11111111111111110000000000000000
b = 00101110, Which is 14bit right rotate.

Test 16
a = 11110000111100001111000011110000
b = 00001111, Which is 15bit right rotate.

Test 17
a = 11110000111100001111000011110000
b = 00010000, Which is 16bit right rotate.

Test 18
a = 11110000111100001111000011110000
b = 10010001, Which is 17bit right rotate.

Test 19
a = 11110000111100001111000011110000
b = 01010010, Which is 18bit right rotate.

Test 20
a = 11110000111100001111000011110000
b = 00110011, Which is 19bit right rotate.

Test 21
a = 00111100111100111100111100111100
b = 00010100, Which is 20bit right rotate.

Test 22
a = 00111100111100111100111100111100
b = 00010101, Which is 21bit right rotate.

Test 23
a = 00111100111100111100111100111100
b = 10010110, Which is 22bit right rotate.

Test 24
a = 00111100111100111100111100111100
b = 01010111, Which is 23bit right rotate.

Test 25
a = 00111100111100111100111100111100
b = 00111000, Which is 24bit right rotate.

Test 26
a = 00110011001100110011001100110011
b = 00011001, Which is 25bit right rotate.

Test 27
a = 00110011001100110011001100110011
b = 00011010, Which is 26bit right rotate.

Test 28
a = 00110011001100110011001100110011
b = 10011011, Which is 27bit right rotate.

Test 29
a = 00110011001100110011001100110011
b = 01011100, Which is 28bit right rotate.

Test 30
a = 00110011001100110011001100110011
b = 00111101, Which is 29bit right rotate.

Test 31
a = 11111111000000001111000011001010
b = 00011110, Which is 30bit right rotate.

Test 32
a = 11111111000000001111000011001010
b = 00011111, Which is 31bit right rotate.

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Synthesis and Implementation:

In my design I used 32 to 1 multiplexer but for the select line I used 8 select line instead of 5 for
providing more than 31 integer value.
So my multiplexer uses its hardware perfectly but the multiplexer needs only last 5 select line I
am wasting 3 select line which are 7, 6 and 5 and for that I got waring in ISE.
In the synthesis ISE provide waring about not using the 3 select lines but in post-route phase it
does not provide any waring because for that 3 non usable select line got input from the user.
The cause for this difference is wasting the hardware, increasing the area of the hardware and
increase the power consumption of the hardware because of the 3 non usable select line.
Left Rotate
After Synthesis
Number of Slice LUTs used = 96
After Post-route phase
Number of Slice LUTs used = 80
Right Rotate
After Synthesis
Number of Slice LUTs used = 96
After Post-route phase
Number of Slice LUTs used = 80

Timing Simulation
Left Rotate
Test 1
a = 11100010101011110000101010101010
b = 00000101, Which is 5bit left rotate.

Test 2
a = 11100010101011110000101010101010
b = 00000110, Which is 6bit left rotate.

Test 3
a = 11100010101011110000101010101010
b = 10000111, Which is 7bit left rotate.

Test 4
a = 11100010101011110000101010101010
b = 01001000, Which is 8bit left rotate.

Test 5
a = 11100010101011110000101010101010
b = 00101001, Which is 9bit left rotate.

Propagation Delay
Minimum Propagation Delay = 9.850 ns
Maximum Propagation Delay = 11.658 ns
I can run my circuit with minimum (fastest) of 9.850 ns propagation delay.

Right Rotate
Test 1
a = 11111111111111110000000000000000
b = 00001010, Which is 10bit right rotate.

Test 2
a = 11111111111111110000000000000000
b = 00001011, Which is 11bit right rotate.

Test 3
a = 11111111111111110000000000000000
b = 10001100, Which is 12bit right rotate.

Test 4
a = 11111111111111110000000000000000
b = 01001101, Which is 13bit right rotate.

Test 5
a = 11111111111111110000000000000000
b = 00101110, Which is 14bit right rotate.

Propagation Delay
Minimum Propagation Delay = 9.760 ns
Maximum Propagation Delay = 11.283 ns
I can run my circuit with minimum (fastest) of 9.760 ns propagation delay.

Glitches

A glitch is an invalid output of the digital circuit at particular input.

Glitches are generated due to large propagation delay.

YouTube Link
https://www.youtube.com/watch?v=zYIC_Oa9rlc